[PATCH 12/12] drm/i915: Add CSC correction for CHV/BSW

Kausal Malladi
2015-07-03T03:31:47Z

CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.

This patch does the following:
1. Adds the core function to program CSC correction values for
CHV/BSW platform
2. Adds CSC correction macros/defines

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kausal Malladi <Kausal.Malladi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_atomic.c | 2 +
drivers/gpu/drm/i915/intel_color_manager.c | 110 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 9 +++
drivers/gpu/drm/i915/intel_drv.h | 2 +
5 files changed, 127 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58a1414..7476132 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7904,14 +7904,18 @@ enum skl_disp_power_wells {
#define PIPEA_CGM_CONTROL (VLV_DISPLAY_BASE + 0x67A00)
#define PIPEA_CGM_GAMMA_MIN (VLV_DISPLAY_BASE + 0x67000)
#define PIPEA_CGM_DEGAMMA_MIN (VLV_DISPLAY_BASE + 0x66000)
+#define PIPEA_CGM_CSC_MIN (VLV_DISPLAY_BASE + 0x67900)
#define CGM_OFFSET 0x2000
#define GAMMA_OFFSET 0x2000
#define DEGAMMA_OFFSET 0x2000
+#define CGM_CSC_OFFSET 0x2000
#define _PIPE_CGM_CONTROL(pipe) \
(PIPEA_CGM_CONTROL + (pipe * CGM_OFFSET))
#define _PIPE_GAMMA_BASE(pipe) \
(PIPEA_CGM_GAMMA_MIN + (pipe * GAMMA_OFFSET))
#define _PIPE_DEGAMMA_BASE(pipe) \
(PIPEA_CGM_DEGAMMA_MIN + (pipe * DEGAMMA_OFFSET))
+#define _PIPE_CSC_BASE(pipe) \
+ (PIPEA_CGM_CSC_MIN + (pipe * CGM_CSC_OFFSET))

#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 570af9d..8a90d59 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -480,6 +480,8 @@ int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
return intel_color_manager_set_gamma(dev, &crtc->base, val);
if (property == config->prop_palette_before_ctm)
return intel_color_manager_set_degamma(dev, &crtc->base, val);
+ if (property == config->prop_ctm)
+ return intel_color_manager_set_csc(dev, &crtc->base, val);

DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index 21c499f..25045b3 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,105 @@

#include "intel_color_manager.h"

+s16 get_csc_s3_12_format(s32 csc_value)
+{
+ s16 csc_int_value;
+ u16 csc_fract_value;
+ s16 csc_s3_12_format;
+
+ if (csc_value > 0) {
+ csc_value += CHV_CSC_FRACT_ROUNDOFF;
+ if (csc_value > CHV_CSC_COEFF_MAX)
+ csc_value = CHV_CSC_COEFF_MAX;
+ } else {
+ csc_value = -csc_value;
+ csc_value += CHV_CSC_FRACT_ROUNDOFF;
+ if (csc_value > CHV_CSC_COEFF_MAX + 1)
+ csc_value = CHV_CSC_COEFF_MAX + 1;
+ csc_value = -csc_value;
+ }
+
+ csc_int_value = csc_value >> CHV_CSC_COEFF_SHIFT;
+ csc_int_value <<= CHV_CSC_COEFF_INT_SHIFT;
+ if (csc_value < 0)
+ csc_int_value |= CSC_COEFF_SIGN;
+ csc_fract_value = csc_value;
+ csc_fract_value >>= CHV_CSC_COEFF_FRACT_SHIFT;
+ csc_s3_12_format = csc_int_value | csc_fract_value;
+
+ return csc_s3_12_format;
+}
+
+int chv_set_csc(struct drm_device *dev, uint64_t blob_id,
+ struct drm_crtc *crtc)
+{
+ struct drm_ctm *csc_data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_property_blob *blob;
+ struct drm_mode_config *config = &dev->mode_config;
+ u32 reg;
+ enum pipe pipe;
+ s32 word, temp;
+ int ret, count = 0;
+
+ blob = drm_property_lookup_blob(dev, blob_id);
+ if (!blob) {
+ DRM_ERROR("Invalid Blob ID\n");
+ return -EINVAL;
+ }
+
+ csc_data = (struct drm_ctm *)blob->data;
+ if (csc_data->version != CHV_CSC_DATA_STRUCT_VERSION) {
+ DRM_ERROR("Invalid CSC Data struct version\n");
+ return -EINVAL;
+ }
+
+ pipe = to_intel_crtc(crtc)->pipe;
+
+ /* Disable CSC functionality */
+ reg = _PIPE_CGM_CONTROL(pipe);
+ I915_WRITE(reg, I915_READ(reg) & (~CGM_CSC_EN));
+
+ DRM_DEBUG_DRIVER("Disabled CSC Functionality on Pipe %c\n",
+ pipe_name(pipe));
+
+ reg = _PIPE_CSC_BASE(pipe);
+ while (count < CSC_MAX_VALS) {
+ word = get_csc_s3_12_format(csc_data->ctm_coeff[count]);
+
+ /*
+ * Last value to be written in 1 register.
+ * Otherwise, each pair of CSC values go
+ * into 1 register
+ */
+ if (count != (CSC_MAX_VALS - 1)) {
+ count++;
+ temp = get_csc_s3_12_format(csc_data->ctm_coeff[count]);
+ word |= temp;
+ }
+ I915_WRITE(reg, word);
+ reg += 4;
+ count++;
+ }
+
+ DRM_DEBUG_DRIVER("All CSC values written to registers\n");
+
+ /* Enable CSC functionality */
+ reg = _PIPE_CGM_CONTROL(pipe);
+ I915_WRITE(reg, I915_READ(reg) | CGM_CSC_EN);
+ DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n", pipe_name(pipe));
+
+ ret = drm_property_replace_global_blob(dev, &blob,
+ sizeof(struct drm_ctm), (void *) csc_data,
+ &crtc->base, config->prop_ctm);
+ if (ret) {
+ DRM_ERROR("Error updating CSC blob\n");
+ return -EFAULT;
+ }
+
+ return ret;
+}
+
int chv_set_degamma(struct drm_device *dev, uint32_t blob_id,
struct drm_crtc *crtc)
{
@@ -269,6 +368,17 @@ int chv_set_gamma(struct drm_device *dev, uint32_t blob_id,
return ret;
}

+int intel_color_manager_set_csc(struct drm_device *dev,
+ struct drm_mode_object *obj, uint32_t blob_id)
+{
+ struct drm_crtc *crtc = obj_to_crtc(obj);
+
+ if (IS_CHERRYVIEW(dev))
+ return chv_set_csc(dev, blob_id, crtc);
+
+ return -EINVAL;
+}
+
int intel_color_manager_set_gamma(struct drm_device *dev,
struct drm_mode_object *obj, uint32_t blob_id)
{
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index 64468c1..a596175 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -33,6 +33,7 @@
#define CHV_PLATFORM_STRUCT_VERSION 1
#define CHV_GAMMA_DATA_STRUCT_VERSION 1
#define CHV_DEGAMMA_DATA_STRUCT_VERSION 1
+#define CHV_CSC_DATA_STRUCT_VERSION 1

#define CHV_MAX_PALETTE_CAPS_BEFORE_CTM 1
#define CHV_MAX_PALETTE_CAPS_AFTER_CTM 2
@@ -55,11 +56,19 @@
#define CHV_DEGAMMA_MSB_SHIFT 2
#define CHV_DEGAMMA_GREEN_SHIFT 16

+#define CSC_MAX_VALS 9
#define CHV_CSC_COEFF_MAX_PRECISION 12
#define CHV_CSC_COEFF_MAX_INT 7
#define CHV_CSC_COEFF_MIN_INT -7
+#define CHV_CSC_COEFF_MAX ((7 << 16) + 0xFFFF)
+#define CHV_CSC_FRACT_ROUNDOFF (1 << 3)
+#define CHV_CSC_COEFF_SHIFT 16
+#define CHV_CSC_COEFF_FRACT_SHIFT 4
+#define CHV_CSC_COEFF_INT_SHIFT 12
+#define CSC_COEFF_SIGN (1 << 15)

/* CHV CGM Block */
/* Bit 2 to be enabled in CGM block for CHV */
#define CGM_GAMMA_EN 4
#define CGM_DEGAMMA_EN 1
+#define CGM_CSC_EN 2
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f47d9d6..dc30d56 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1457,5 +1457,7 @@ int intel_color_manager_set_gamma(struct drm_device *dev,
struct drm_mode_object *obj, uint32_t blob_id);
int intel_color_manager_set_degamma(struct drm_device *dev,
struct drm_mode_object *obj, uint32_t blob_id);
+int intel_color_manager_set_csc(struct drm_device *dev,
+ struct drm_mode_object *obj, uint32_t blob_id);

#endif /* __INTEL_DRV_H__ */