From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sivakumar Thulasimani Subject: Re: [PATCH 3/9] drm/i915: Simplify CHV pipe A power well code Date: Fri, 10 Jul 2015 16:43:54 +0530 Message-ID: <559FA8F2.2000102@intel.com> References: <1435580756-20154-1-git-send-email-ville.syrjala@linux.intel.com> <1435580756-20154-4-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0498129098==" Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 07D7C6E3C3 for ; Fri, 10 Jul 2015 04:13:57 -0700 (PDT) In-Reply-To: <1435580756-20154-4-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0498129098== Content-Type: multipart/alternative; boundary="------------040103020008050204080803" This is a multi-part message in MIME format. --------------040103020008050204080803 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Reviewed-by: Sivakumar Thulasimani On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > The pipe A power well is the "disp2d" well on CHV and pipe B and C well= s > don't even exist. Thereforce we can remove the checks for pipe A vs. > others and just assume it's always pipe A. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 47 ++++++++++++++----------= --------- > 1 file changed, 20 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/= i915/intel_runtime_pm.c > index 932d963..1bd947a 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -1042,53 +1042,46 @@ out: > static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_= priv, > struct i915_power_well *power_well) > { > + WARN_ON_ONCE(power_well->data !=3D PIPE_A); > + > chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0)= ; > } > =20 > static void chv_pipe_power_well_enable(struct drm_i915_private *dev_p= riv, > struct i915_power_well *power_well) > { > - WARN_ON_ONCE(power_well->data !=3D PIPE_A && > - power_well->data !=3D PIPE_B && > - power_well->data !=3D PIPE_C); > + WARN_ON_ONCE(power_well->data !=3D PIPE_A); > =20 > chv_set_pipe_power_well(dev_priv, power_well, true); > =20 > - if (power_well->data =3D=3D PIPE_A) { > - spin_lock_irq(&dev_priv->irq_lock); > - valleyview_enable_display_irqs(dev_priv); > - spin_unlock_irq(&dev_priv->irq_lock); > + spin_lock_irq(&dev_priv->irq_lock); > + valleyview_enable_display_irqs(dev_priv); > + spin_unlock_irq(&dev_priv->irq_lock); > =20 > - /* > - * During driver initialization/resume we can avoid restoring the > - * part of the HW/SW state that will be inited anyway explicitly. > - */ > - if (dev_priv->power_domains.initializing) > - return; > + /* > + * During driver initialization/resume we can avoid restoring the > + * part of the HW/SW state that will be inited anyway explicitly. > + */ > + if (dev_priv->power_domains.initializing) > + return; > =20 > - intel_hpd_init(dev_priv); > + intel_hpd_init(dev_priv); > =20 > - i915_redisable_vga_power_on(dev_priv->dev); > - } > + i915_redisable_vga_power_on(dev_priv->dev); > } > =20 > static void chv_pipe_power_well_disable(struct drm_i915_private *dev_= priv, > struct i915_power_well *power_well) > { > - WARN_ON_ONCE(power_well->data !=3D PIPE_A && > - power_well->data !=3D PIPE_B && > - power_well->data !=3D PIPE_C); > - > - if (power_well->data =3D=3D PIPE_A) { > - spin_lock_irq(&dev_priv->irq_lock); > - valleyview_disable_display_irqs(dev_priv); > - spin_unlock_irq(&dev_priv->irq_lock); > - } > + WARN_ON_ONCE(power_well->data !=3D PIPE_A); > + > + spin_lock_irq(&dev_priv->irq_lock); > + valleyview_disable_display_irqs(dev_priv); > + spin_unlock_irq(&dev_priv->irq_lock); > =20 > chv_set_pipe_power_well(dev_priv, power_well, false); > =20 > - if (power_well->data =3D=3D PIPE_A) > - vlv_power_sequencer_reset(dev_priv); > + vlv_power_sequencer_reset(dev_priv); > } > =20 > /** --=20 regards, Sivakumar --------------040103020008050204080803 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

Reviewed= -by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote:
From: Ville Syrj=C3=A4l=C3=A4 <ville.syrj=
ala@linux.intel.com>

The pipe A power well is the "disp2d" well on CHV and pipe B and C wells
don't even exist. Thereforce we can remove the checks for pipe A vs.
others and just assume it's always pipe A.

Signed-off-by: Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.in=
tel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 47 ++++++++++++++-------------=
------
 1 file changed, 20 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i9=
15/intel_runtime_pm.c
index 932d963..1bd947a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1042,53 +1042,46 @@ out:
 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_pri=
v,
 					struct i915_power_well *power_well)
 {
+	WARN_ON_ONCE(power_well->data !=3D PIPE_A);
+
 	chv_set_pipe_power_well(dev_priv, power_well, power_well->count >=
 0);
 }
=20
 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv=
,
 				       struct i915_power_well *power_well)
 {
-	WARN_ON_ONCE(power_well->data !=3D PIPE_A &&
-		     power_well->data !=3D PIPE_B &&
-		     power_well->data !=3D PIPE_C);
+	WARN_ON_ONCE(power_well->data !=3D PIPE_A);
=20
 	chv_set_pipe_power_well(dev_priv, power_well, true);
=20
-	if (power_well->data =3D=3D PIPE_A) {
-		spin_lock_irq(&dev_priv->irq_lock);
-		valleyview_enable_display_irqs(dev_priv);
-		spin_unlock_irq(&dev_priv->irq_lock);
+	spin_lock_irq(&dev_priv->irq_lock);
+	valleyview_enable_display_irqs(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
=20
-		/*
-		 * During driver initialization/resume we can avoid restoring the
-		 * part of the HW/SW state that will be inited anyway explicitly.
-		 */
-		if (dev_priv->power_domains.initializing)
-			return;
+	/*
+	 * During driver initialization/resume we can avoid restoring the
+	 * part of the HW/SW state that will be inited anyway explicitly.
+	 */
+	if (dev_priv->power_domains.initializing)
+		return;
=20
-		intel_hpd_init(dev_priv);
+	intel_hpd_init(dev_priv);
=20
-		i915_redisable_vga_power_on(dev_priv->dev);
-	}
+	i915_redisable_vga_power_on(dev_priv->dev);
 }
=20
 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_pri=
v,
 					struct i915_power_well *power_well)
 {
-	WARN_ON_ONCE(power_well->data !=3D PIPE_A &&
-		     power_well->data !=3D PIPE_B &&
-		     power_well->data !=3D PIPE_C);
-
-	if (power_well->data =3D=3D PIPE_A) {
-		spin_lock_irq(&dev_priv->irq_lock);
-		valleyview_disable_display_irqs(dev_priv);
-		spin_unlock_irq(&dev_priv->irq_lock);
-	}
+	WARN_ON_ONCE(power_well->data !=3D PIPE_A);
+
+	spin_lock_irq(&dev_priv->irq_lock);
+	valleyview_disable_display_irqs(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
=20
 	chv_set_pipe_power_well(dev_priv, power_well, false);
=20
-	if (power_well->data =3D=3D PIPE_A)
-		vlv_power_sequencer_reset(dev_priv);
+	vlv_power_sequencer_reset(dev_priv);
 }
=20
 /**


--=20
regards,
Sivakumar
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