From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sivakumar Thulasimani Subject: Re: [PATCH 4/9] drm/i915: Refactor VLV display power well init/deinit Date: Fri, 10 Jul 2015 16:52:20 +0530 Message-ID: <559FAAEC.2050801@intel.com> References: <1435580756-20154-1-git-send-email-ville.syrjala@linux.intel.com> <1435580756-20154-5-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0615222692==" Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A6A77A122 for ; Fri, 10 Jul 2015 04:22:28 -0700 (PDT) In-Reply-To: <1435580756-20154-5-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0615222692== Content-Type: multipart/alternative; boundary="------------050901030407040204080407" This is a multi-part message in MIME format. --------------050901030407040204080407 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Reviewed-by: Sivakumar Thulasimani On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > We do the exact same steps around the disp2d/pipe A power well > enable/disable on VLV and CHV. Refactor the shared code into > some helpers. > > Note that this means we now call vlv_power_sequencer_reset() before > turning off the power well, whereas before we did it after. That > doesn't matter though since vlv_power_sequencer_reset() just resets > the power sequencer software tracking and doesn't touch the hardware > at all. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 52 +++++++++++++++---------= --------- > 1 file changed, 23 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/= i915/intel_runtime_pm.c > index 1bd947a..6393b76 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -835,12 +835,8 @@ static bool vlv_power_well_enabled(struct drm_i915= _private *dev_priv, > return enabled; > } > =20 > -static void vlv_display_power_well_enable(struct drm_i915_private *dev= _priv, > - struct i915_power_well *power_well) > +static void vlv_display_power_well_init(struct drm_i915_private *dev_p= riv) > { > - WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DISP2D); > - > - vlv_set_power_well(dev_priv, power_well, true); > =20 > spin_lock_irq(&dev_priv->irq_lock); > valleyview_enable_display_irqs(dev_priv); > @@ -858,18 +854,33 @@ static void vlv_display_power_well_enable(struct = drm_i915_private *dev_priv, > i915_redisable_vga_power_on(dev_priv->dev); > } > =20 > +static void vlv_display_power_well_deinit(struct drm_i915_private *dev= _priv) > +{ > + spin_lock_irq(&dev_priv->irq_lock); > + valleyview_disable_display_irqs(dev_priv); > + spin_unlock_irq(&dev_priv->irq_lock); > + > + vlv_power_sequencer_reset(dev_priv); > +} > + > +static void vlv_display_power_well_enable(struct drm_i915_private *dev= _priv, > + struct i915_power_well *power_well) > +{ > + WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DISP2D); > + > + vlv_set_power_well(dev_priv, power_well, true); > + > + vlv_display_power_well_init(dev_priv); > +} > + > static void vlv_display_power_well_disable(struct drm_i915_private *d= ev_priv, > struct i915_power_well *power_well) > { > WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DISP2D); > =20 > - spin_lock_irq(&dev_priv->irq_lock); > - valleyview_disable_display_irqs(dev_priv); > - spin_unlock_irq(&dev_priv->irq_lock); > + vlv_display_power_well_deinit(dev_priv); > =20 > vlv_set_power_well(dev_priv, power_well, false); > - > - vlv_power_sequencer_reset(dev_priv); > } > =20 > static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *d= ev_priv, > @@ -1054,20 +1065,7 @@ static void chv_pipe_power_well_enable(struct dr= m_i915_private *dev_priv, > =20 > chv_set_pipe_power_well(dev_priv, power_well, true); > =20 > - spin_lock_irq(&dev_priv->irq_lock); > - valleyview_enable_display_irqs(dev_priv); > - spin_unlock_irq(&dev_priv->irq_lock); > - > - /* > - * During driver initialization/resume we can avoid restoring the > - * part of the HW/SW state that will be inited anyway explicitly. > - */ > - if (dev_priv->power_domains.initializing) > - return; > - > - intel_hpd_init(dev_priv); > - > - i915_redisable_vga_power_on(dev_priv->dev); > + vlv_display_power_well_init(dev_priv); > } > =20 > static void chv_pipe_power_well_disable(struct drm_i915_private *dev_= priv, > @@ -1075,13 +1073,9 @@ static void chv_pipe_power_well_disable(struct d= rm_i915_private *dev_priv, > { > WARN_ON_ONCE(power_well->data !=3D PIPE_A); > =20 > - spin_lock_irq(&dev_priv->irq_lock); > - valleyview_disable_display_irqs(dev_priv); > - spin_unlock_irq(&dev_priv->irq_lock); > + vlv_display_power_well_deinit(dev_priv); > =20 > chv_set_pipe_power_well(dev_priv, power_well, false); > - > - vlv_power_sequencer_reset(dev_priv); > } > =20 > /** --=20 regards, Sivakumar --------------050901030407040204080407 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

Reviewed= -by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote:
From: Ville Syrj=C3=A4l=C3=A4 <ville.syrj=
ala@linux.intel.com>

We do the exact same steps around the disp2d/pipe A power well
enable/disable on VLV and CHV. Refactor the shared code into
some helpers.

Note that this means we now call vlv_power_sequencer_reset() before
turning off the power well, whereas before we did it after. That
doesn't matter though since vlv_power_sequencer_reset() just resets
the power sequencer software tracking and doesn't touch the hardware
at all.

Signed-off-by: Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.in=
tel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 52 +++++++++++++++------------=
------
 1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i9=
15/intel_runtime_pm.c
index 1bd947a..6393b76 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -835,12 +835,8 @@ static bool vlv_power_well_enabled(struct drm_i915_p=
rivate *dev_priv,
 	return enabled;
 }
=20
-static void vlv_display_power_well_enable(struct drm_i915_private *dev_p=
riv,
-					  struct i915_power_well *power_well)
+static void vlv_display_power_well_init(struct drm_i915_private *dev_pri=
v)
 {
-	WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DISP2D);
-
-	vlv_set_power_well(dev_priv, power_well, true);
=20
 	spin_lock_irq(&dev_priv->irq_lock);
 	valleyview_enable_display_irqs(dev_priv);
@@ -858,18 +854,33 @@ static void vlv_display_power_well_enable(struct dr=
m_i915_private *dev_priv,
 	i915_redisable_vga_power_on(dev_priv->dev);
 }
=20
+static void vlv_display_power_well_deinit(struct drm_i915_private *dev_p=
riv)
+{
+	spin_lock_irq(&dev_priv->irq_lock);
+	valleyview_disable_display_irqs(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
+
+	vlv_power_sequencer_reset(dev_priv);
+}
+
+static void vlv_display_power_well_enable(struct drm_i915_private *dev_p=
riv,
+					  struct i915_power_well *power_well)
+{
+	WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DISP2D);
+
+	vlv_set_power_well(dev_priv, power_well, true);
+
+	vlv_display_power_well_init(dev_priv);
+}
+
 static void vlv_display_power_well_disable(struct drm_i915_private *dev_=
priv,
 					   struct i915_power_well *power_well)
 {
 	WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DISP2D);
=20
-	spin_lock_irq(&dev_priv->irq_lock);
-	valleyview_disable_display_irqs(dev_priv);
-	spin_unlock_irq(&dev_priv->irq_lock);
+	vlv_display_power_well_deinit(dev_priv);
=20
 	vlv_set_power_well(dev_priv, power_well, false);
-
-	vlv_power_sequencer_reset(dev_priv);
 }
=20
 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_=
priv,
@@ -1054,20 +1065,7 @@ static void chv_pipe_power_well_enable(struct drm_=
i915_private *dev_priv,
=20
 	chv_set_pipe_power_well(dev_priv, power_well, true);
=20
-	spin_lock_irq(&dev_priv->irq_lock);
-	valleyview_enable_display_irqs(dev_priv);
-	spin_unlock_irq(&dev_priv->irq_lock);
-
-	/*
-	 * During driver initialization/resume we can avoid restoring the
-	 * part of the HW/SW state that will be inited anyway explicitly.
-	 */
-	if (dev_priv->power_domains.initializing)
-		return;
-
-	intel_hpd_init(dev_priv);
-
-	i915_redisable_vga_power_on(dev_priv->dev);
+	vlv_display_power_well_init(dev_priv);
 }
=20
 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_pri=
v,
@@ -1075,13 +1073,9 @@ static void chv_pipe_power_well_disable(struct drm=
_i915_private *dev_priv,
 {
 	WARN_ON_ONCE(power_well->data !=3D PIPE_A);
=20
-	spin_lock_irq(&dev_priv->irq_lock);
-	valleyview_disable_display_irqs(dev_priv);
-	spin_unlock_irq(&dev_priv->irq_lock);
+	vlv_display_power_well_deinit(dev_priv);
=20
 	chv_set_pipe_power_well(dev_priv, power_well, false);
-
-	vlv_power_sequencer_reset(dev_priv);
 }
=20
 /**


--=20
regards,
Sivakumar
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