From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sivakumar Thulasimani Subject: Re: [PATCH 5/9] drm/i915: Clear out DPLL state from pipe config in DSI get config Date: Fri, 10 Jul 2015 17:15:37 +0530 Message-ID: <559FB061.60208@intel.com> References: <1435580756-20154-1-git-send-email-ville.syrjala@linux.intel.com> <1435580756-20154-6-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0885742561==" Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id C6A7F6E48D for ; Fri, 10 Jul 2015 04:45:39 -0700 (PDT) In-Reply-To: <1435580756-20154-6-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0885742561== Content-Type: multipart/alternative; boundary="------------080503070303090800050306" This is a multi-part message in MIME format. --------------080503070303090800050306 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Reviewed-by: Sivakumar Thulasimani On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > VLV/CHV don't use the DPLL with DSI, so just clear out the DPLL state > from the pipe_config in intel_dsi_get_config(). This avoids spurious > state checker warnings. We already did it this way for DPLL_MD, but do > it for DPLL too. > > Toss in a WARN to intel_dsi_pre_enable() to make sure the ref clocks > are enabled however. Supposedly they have some meaning to DSI too. > We now keep the ref clocks always enabled while the disp2d well is > enabled. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_dsi.c | 15 +++++---------- > 1 file changed, 5 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/in= tel_dsi.c > index 36e2148..92bb252 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -421,18 +421,12 @@ static void intel_dsi_pre_enable(struct intel_enc= oder *encoder) > =20 > /* Disable DPOunit clock gating, can stall pipe > * and we need DPLL REFA always enabled */ > - tmp =3D I915_READ(DPLL(pipe)); > - tmp |=3D DPLL_REF_CLK_ENABLE_VLV; > - I915_WRITE(DPLL(pipe), tmp); > - > - /* update the hw state for DPLL */ > - intel_crtc->config->dpll_hw_state.dpll =3D DPLL_INTEGRATED_REF_CLK_VL= V | > - DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; > - > tmp =3D I915_READ(DSPCLK_GATE_D); > tmp |=3D DPOUNIT_CLOCK_GATE_DISABLE; > I915_WRITE(DSPCLK_GATE_D, tmp); > =20 > + WARN_ON((I915_READ(DPLL(pipe)) & DPLL_REF_CLK_ENABLE_VLV) =3D=3D 0); > + > /* put device in ready state */ > intel_dsi_device_ready(encoder); > =20 > @@ -635,9 +629,10 @@ static void intel_dsi_get_config(struct intel_enco= der *encoder, > DRM_DEBUG_KMS("\n"); > =20 > /* > - * DPLL_MD is not used in case of DSI, reading will get some default = value > - * set dpll_md =3D 0 > + * DPLL is not used in case of DSI, reading will getsome default valu= e. > + * Clear the state to keep the state checker happy. > */ > + pipe_config->dpll_hw_state.dpll =3D 0; > pipe_config->dpll_hw_state.dpll_md =3D 0; > =20 > pclk =3D vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); --=20 regards, Sivakumar --------------080503070303090800050306 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

Reviewed= -by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>


On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote:
From: Ville Syrj=C3=A4l=C3=A4 <ville.syrj=
ala@linux.intel.com>

VLV/CHV don't use the DPLL with DSI, so just clear out the DPLL state
from the pipe_config in intel_dsi_get_config(). This avoids spurious
state checker warnings. We already did it this way for DPLL_MD, but do
it for DPLL too.

Toss in a WARN to intel_dsi_pre_enable() to make sure the ref clocks
are enabled however. Supposedly they have some meaning to DSI too.
We now keep the ref clocks always enabled while the disp2d well is
enabled.

Signed-off-by: Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.in=
tel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/inte=
l_dsi.c
index 36e2148..92bb252 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -421,18 +421,12 @@ static void intel_dsi_pre_enable(struct intel_encod=
er *encoder)
=20
 	/* Disable DPOunit clock gating, can stall pipe
 	 * and we need DPLL REFA always enabled */
-	tmp =3D I915_READ(DPLL(pipe));
-	tmp |=3D DPLL_REF_CLK_ENABLE_VLV;
-	I915_WRITE(DPLL(pipe), tmp);
-
-	/* update the hw state for DPLL */
-	intel_crtc->config->dpll_hw_state.dpll =3D DPLL_INTEGRATED_REF_CL=
K_VLV |
-		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
-
 	tmp =3D I915_READ(DSPCLK_GATE_D);
 	tmp |=3D DPOUNIT_CLOCK_GATE_DISABLE;
 	I915_WRITE(DSPCLK_GATE_D, tmp);
=20
+	WARN_ON((I915_READ(DPLL(pipe)) & DPLL_REF_CLK_ENABLE_VLV) =3D=3D 0)=
;
+
 	/* put device in ready state */
 	intel_dsi_device_ready(encoder);
=20
@@ -635,9 +629,10 @@ static void intel_dsi_get_config(struct intel_encode=
r *encoder,
 	DRM_DEBUG_KMS("\n");
=20
 	/*
-	 * DPLL_MD is not used in case of DSI, reading will get some default va=
lue
-	 * set dpll_md =3D 0
+	 * DPLL is not used in case of DSI, reading will getsome default value.
+	 * Clear the state to keep the state checker happy.
 	 */
+	pipe_config->dpll_hw_state.dpll =3D 0;
 	pipe_config->dpll_hw_state.dpll_md =3D 0;
=20
 	pclk =3D vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);


--=20
regards,
Sivakumar
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