From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sivakumar Thulasimani Subject: Re: [PATCH 6/9] drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable Date: Fri, 10 Jul 2015 18:03:39 +0530 Message-ID: <559FBBA3.9040906@intel.com> References: <1435580756-20154-1-git-send-email-ville.syrjala@linux.intel.com> <1435580756-20154-7-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1243865407==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id EBACA8A450 for ; Fri, 10 Jul 2015 05:33:41 -0700 (PDT) In-Reply-To: <1435580756-20154-7-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============1243865407== Content-Type: multipart/alternative; boundary="------------000506030200050109040808" This is a multi-part message in MIME format. --------------000506030200050109040808 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Reviewed-by: Sivakumar Thulasimani On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV, > and having VGA mode enabled causes some problems for CHV. So let's just > pull the code to configure those bits into the disp2d well enable hook. > With the DPLL disable code also fixed to leave those bits alone we > should now have a consistent DPLL state all the time even if the DPLL > is disabled. > > This also neatly removes some duplicated code between the VLV and > CHV codepaths. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 45 ++++++++++++++++++------= --------- > 1 file changed, 24 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/= i915/intel_runtime_pm.c > index 6393b76..2142ae6 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -837,6 +837,25 @@ static bool vlv_power_well_enabled(struct drm_i915= _private *dev_priv, > =20 > static void vlv_display_power_well_init(struct drm_i915_private *dev_= priv) > { > + enum pipe pipe; > + > + /* > + * Enable the CRI clock source so we can get at the > + * display and the reference clock for VGA > + * hotplug / manual detection. Supposedly DSI also > + * needs the ref clock up and running. > + * > + * CHV DPLL B/C have some issues if VGA mode is enabled. > + */ > + for_each_pipe(dev_priv->dev, pipe) { > + u32 val =3D I915_READ(DPLL(pipe)); > + > + val |=3D DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; > + if (pipe !=3D PIPE_A) > + val |=3D DPLL_INTEGRATED_CRI_CLK_VLV; > + > + I915_WRITE(DPLL(pipe), val); > + } > =20 > spin_lock_irq(&dev_priv->irq_lock); > valleyview_enable_display_irqs(dev_priv); > @@ -888,13 +907,7 @@ static void vlv_dpio_cmn_power_well_enable(struct = drm_i915_private *dev_priv, > { > WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_BC); > =20 > - /* > - * Enable the CRI clock source so we can get at the > - * display and the reference clock for VGA > - * hotplug / manual detection. > - */ > - I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS = | > - DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); > + /* since ref/cri clock was enabled */ > udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ > =20 > vlv_set_power_well(dev_priv, power_well, true); > @@ -937,22 +950,12 @@ static void chv_dpio_cmn_power_well_enable(struct= drm_i915_private *dev_priv, > WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_BC && > power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_D); > =20 > - /* > - * Enable the CRI clock source so we can get at the > - * display and the reference clock for VGA > - * hotplug / manual detection. > - */ > - if (power_well->data =3D=3D PUNIT_POWER_WELL_DPIO_CMN_BC) { > + if (power_well->data =3D=3D PUNIT_POWER_WELL_DPIO_CMN_BC) > phy =3D DPIO_PHY0; > - I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS= | > - DPLL_REF_CLK_ENABLE_VLV); > - I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS= | > - DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); > - } else { > + else > phy =3D DPIO_PHY1; > - I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS= | > - DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); > - } > + > + /* since ref/cri clock was enabled */ > udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ > vlv_set_power_well(dev_priv, power_well, true); > =20 --=20 regards, Sivakumar --------------000506030200050109040808 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

Reviewed= -by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote:
From: Ville Syrj=C3=A4l=C3=A4 <ville.syrj=
ala@linux.intel.com>

Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV,
and having VGA mode enabled causes some problems for CHV. So let's just
pull the code to configure those bits into the disp2d well enable hook.
With the DPLL disable code also fixed to leave those bits alone we
should now have a consistent DPLL state all the time even if the DPLL
is disabled.

This also neatly removes some duplicated code between the VLV and
CHV codepaths.

Signed-off-by: Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.in=
tel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 45 ++++++++++++++++++---------=
------
 1 file changed, 24 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i9=
15/intel_runtime_pm.c
index 6393b76..2142ae6 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -837,6 +837,25 @@ static bool vlv_power_well_enabled(struct drm_i915_p=
rivate *dev_priv,
=20
 static void vlv_display_power_well_init(struct drm_i915_private *dev_pri=
v)
 {
+	enum pipe pipe;
+
+	/*
+	 * Enable the CRI clock source so we can get at the
+	 * display and the reference clock for VGA
+	 * hotplug / manual detection. Supposedly DSI also
+	 * needs the ref clock up and running.
+	 *
+	 * CHV DPLL B/C have some issues if VGA mode is enabled.
+	 */
+	for_each_pipe(dev_priv->dev, pipe) {
+		u32 val =3D I915_READ(DPLL(pipe));
+
+		val |=3D DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+		if (pipe !=3D PIPE_A)
+			val |=3D DPLL_INTEGRATED_CRI_CLK_VLV;
+
+		I915_WRITE(DPLL(pipe), val);
+	}
=20
 	spin_lock_irq(&dev_priv->irq_lock);
 	valleyview_enable_display_irqs(dev_priv);
@@ -888,13 +907,7 @@ static void vlv_dpio_cmn_power_well_enable(struct dr=
m_i915_private *dev_priv,
 {
 	WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_BC);
=20
-	/*
-	 * Enable the CRI clock source so we can get at the
-	 * display and the reference clock for VGA
-	 * hotplug / manual detection.
-	 */
-	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
-		   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
+	/* since ref/cri clock was enabled */
 	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
=20
 	vlv_set_power_well(dev_priv, power_well, true);
@@ -937,22 +950,12 @@ static void chv_dpio_cmn_power_well_enable(struct d=
rm_i915_private *dev_priv,
 	WARN_ON_ONCE(power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_BC &=
;&
 		     power_well->data !=3D PUNIT_POWER_WELL_DPIO_CMN_D);
=20
-	/*
-	 * Enable the CRI clock source so we can get at the
-	 * display and the reference clock for VGA
-	 * hotplug / manual detection.
-	 */
-	if (power_well->data =3D=3D PUNIT_POWER_WELL_DPIO_CMN_BC) {
+	if (power_well->data =3D=3D PUNIT_POWER_WELL_DPIO_CMN_BC)
 		phy =3D DPIO_PHY0;
-		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
-			   DPLL_REF_CLK_ENABLE_VLV);
-		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
-			   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
-	} else {
+	else
 		phy =3D DPIO_PHY1;
-		I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS |
-			   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
-	}
+
+	/* since ref/cri clock was enabled */
 	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 	vlv_set_power_well(dev_priv, power_well, true);
=20


--=20
regards,
Sivakumar
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