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From: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 9/9] drm/i915: Disable DSI PLL before reconfiguring it
Date: Mon, 13 Jul 2015 11:47:05 +0530	[thread overview]
Message-ID: <55A357E1.5040608@intel.com> (raw)
In-Reply-To: <1435580756-20154-10-git-send-email-ville.syrjala@linux.intel.com>


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Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>



On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The BIOS maybe leave the DSI PLL enabled even if the port is disabled.
> The PLL doesn't seem to like being reconfigured while it's enabled so
> make sure it's disabled before doing that.
>
> The better fix would be to expose all PLLs independently of their ports
> so that we could disable any unused ones during the sanitize phase. But
> this seems like an OK short term solution.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dsi.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 92bb252..07c4bb3 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -907,6 +907,7 @@ static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
>   
>   	intel_dsi_prepare(encoder);
>   
> +	vlv_disable_dsi_pll(encoder);
>   	vlv_enable_dsi_pll(encoder);
>   }
>   

-- 
regards,
Sivakumar


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      reply	other threads:[~2015-07-13  6:17 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-29 12:25 [PATCH 0/9] drm/i915: VLV/CHV DPLL workarounds and cleanups ville.syrjala
2015-06-29 12:25 ` [PATCH 1/9] drm/i915: Keep GMCH DPLL VGA mode always disabled ville.syrjala
2015-06-29 14:16   ` Sivakumar Thulasimani
2015-06-29 14:31     ` Ville Syrjälä
2015-06-29 12:25 ` [PATCH 2/9] drm/i915: Apply OCD to VLV/CHV DPLL defines ville.syrjala
2015-06-29 14:21   ` Sivakumar Thulasimani
2015-06-29 12:25 ` [PATCH 3/9] drm/i915: Simplify CHV pipe A power well code ville.syrjala
2015-07-10 11:13   ` Sivakumar Thulasimani
2015-06-29 12:25 ` [PATCH 4/9] drm/i915: Refactor VLV display power well init/deinit ville.syrjala
2015-07-10 11:22   ` Sivakumar Thulasimani
2015-06-29 12:25 ` [PATCH 5/9] drm/i915: Clear out DPLL state from pipe config in DSI get config ville.syrjala
2015-06-29 16:42   ` Daniel Vetter
2015-06-29 16:56     ` Ville Syrjälä
2015-06-29 17:08       ` Ville Syrjälä
2015-06-30 10:13         ` Daniel Vetter
2015-06-30 11:50           ` Ville Syrjälä
2015-07-01 12:42             ` Daniel Vetter
2015-07-10 12:07               ` Sivakumar Thulasimani
2015-07-13  8:51                 ` Daniel Vetter
2015-07-13 10:19                   ` Sivakumar Thulasimani
2015-07-13 14:39                     ` Daniel Vetter
2015-07-10 11:45   ` Sivakumar Thulasimani
2015-06-29 12:25 ` [PATCH 6/9] drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable ville.syrjala
2015-07-10 12:33   ` Sivakumar Thulasimani
2015-08-26 12:34     ` Daniel Vetter
2015-06-29 12:25 ` [PATCH 7/9] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar ville.syrjala
2015-06-29 12:25 ` [PATCH 8/9] drm/i915: Implement WaPixelRepeatModeFixForC0:chv ville.syrjala
2015-07-13  6:14   ` Sivakumar Thulasimani
2015-08-10 16:01     ` Ville Syrjälä
2015-06-29 12:25 ` [PATCH 9/9] drm/i915: Disable DSI PLL before reconfiguring it ville.syrjala
2015-07-13  6:17   ` Sivakumar Thulasimani [this message]

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