From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sivakumar Thulasimani Subject: Re: [PATCH 9/9] drm/i915: Disable DSI PLL before reconfiguring it Date: Mon, 13 Jul 2015 11:47:05 +0530 Message-ID: <55A357E1.5040608@intel.com> References: <1435580756-20154-1-git-send-email-ville.syrjala@linux.intel.com> <1435580756-20154-10-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0405839370==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id CA80D6E209 for ; Sun, 12 Jul 2015 23:17:26 -0700 (PDT) In-Reply-To: <1435580756-20154-10-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0405839370== Content-Type: multipart/alternative; boundary="------------060407070701000507070407" This is a multi-part message in MIME format. --------------060407070701000507070407 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Reviewed-by: Sivakumar Thulasimani On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > The BIOS maybe leave the DSI PLL enabled even if the port is disabled. > The PLL doesn't seem to like being reconfigured while it's enabled so > make sure it's disabled before doing that. > > The better fix would be to expose all PLLs independently of their ports > so that we could disable any unused ones during the sanitize phase. But > this seems like an OK short term solution. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/intel_dsi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/in= tel_dsi.c > index 92bb252..07c4bb3 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -907,6 +907,7 @@ static void intel_dsi_pre_pll_enable(struct intel_e= ncoder *encoder) > =20 > intel_dsi_prepare(encoder); > =20 > + vlv_disable_dsi_pll(encoder); > vlv_enable_dsi_pll(encoder); > } > =20 --=20 regards, Sivakumar --------------060407070701000507070407 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

Reviewed= -by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote:
From: Ville Syrj=C3=A4l=C3=A4 <ville.syrj=
ala@linux.intel.com>

The BIOS maybe leave the DSI PLL enabled even if the port is disabled.
The PLL doesn't seem to like being reconfigured while it's enabled so
make sure it's disabled before doing that.

The better fix would be to expose all PLLs independently of their ports
so that we could disable any unused ones during the sanitize phase. But
this seems like an OK short term solution.

Signed-off-by: Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.in=
tel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/inte=
l_dsi.c
index 92bb252..07c4bb3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -907,6 +907,7 @@ static void intel_dsi_pre_pll_enable(struct intel_enc=
oder *encoder)
=20
 	intel_dsi_prepare(encoder);
=20
+	vlv_disable_dsi_pll(encoder);
 	vlv_enable_dsi_pll(encoder);
 }
=20


--=20
regards,
Sivakumar
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