intel-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: Michel Thierry <michel.thierry@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org, akash.goel@intel.com
Subject: Re: [PATCH v6 17/19] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset
Date: Wed, 5 Aug 2015 17:14:33 +0100	[thread overview]
Message-ID: <55C23669.5000309@intel.com> (raw)
In-Reply-To: <20150805155843.GC17734@phenom.ffwll.local>

On 8/5/2015 4:58 PM, Daniel Vetter wrote:
> On Wed, Jul 29, 2015 at 05:24:01PM +0100, Michel Thierry wrote:
>> There are some allocations that must be only referenced by 32-bit
>> offsets. To limit the chances of having the first 4GB already full,
>> objects not requiring this workaround use DRM_MM_SEARCH_BELOW/
>> DRM_MM_CREATE_TOP flags
>>
>> In specific, any resource used with flat/heapless (0x00000000-0xfffff000)
>> General State Heap (GSH) or Instruction State Heap (ISH) must be in a
>> 32-bit range, because the General State Offset and Instruction State
>> Offset are limited to 32-bits.
>>
>> Objects must have EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag to indicate if
>> they can be allocated above the 32-bit address range. To limit the
>> chances of having the first 4GB already full, objects will use
>> DRM_MM_SEARCH_BELOW + DRM_MM_CREATE_TOP flags when possible.
>>
>> v2: Changed flag logic from neeeds_32b, to supports_48b.
>> v3: Moved 48-bit support flag back to exec_object. (Chris, Daniel)
>> v4: Split pin flags into PIN_ZONE_4G and PIN_HIGH; update PIN_OFFSET_MASK
>> to use last PIN_ defined instead of hard-coded value; use correct limit
>> check in eb_vma_misplaced. (Chris)
>> v5: Don't touch PIN_OFFSET_MASK and update workaround comment (Chris)
>> v6: Apply pin-high for ggtt too (Chris)
>> v7: Handle simultaneous pin-high and pin-mappable end correctly (Akash)
>>      Fix check for entries currently using +4GB addresses, use min_t and
>>      other polish in object_bind_to_vm (Chris)
>>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Akash Goel <akash.goel@intel.com>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v4)
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>
> For the record, where can I find the mesa patches for this? I think for
> simple things like this a References: line point to the relevant UMD
> patches in mailing-list archives would be great.
> -Daniel
>

Here they are,

References: 
http://lists.freedesktop.org/archives/dri-devel/2015-July/085501.html 
and http://lists.freedesktop.org/archives/mesa-dev/2015-July/088003.html

The name for the macro will be OUT_RELOC64_INSIDE_4G, as suggested by Chris.

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2015-08-05 16:14 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-29 16:23 [PATCH v6 00/19] 48-bit PPGTT Michel Thierry
2015-07-29 16:23 ` [PATCH v6 01/19] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-07-30  3:06   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 02/19] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-07-30  3:18   ` Goel, Akash
2015-08-05 15:31   ` Daniel Vetter
2015-08-05 15:49     ` Michel Thierry
2015-08-05 15:51       ` Michel Thierry
2015-08-06 12:28       ` Daniel Vetter
2015-07-29 16:23 ` [PATCH v6 03/19] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-07-30 10:02   ` [PATCH v7 " Michel Thierry
2015-07-31  4:11     ` Goel, Akash
2015-08-05 15:33       ` Daniel Vetter
2015-07-29 16:23 ` [PATCH v6 04/19] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-07-30  4:46   ` Goel, Akash
2015-07-30  9:31     ` Michel Thierry
2015-07-30 10:02   ` [PATCH v7 " Michel Thierry
2015-07-31  4:00     ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 05/19] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-07-30  3:48   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 06/19] drm/i915/gen8: Add PML4 structure Michel Thierry
2015-07-30  4:01   ` Goel, Akash
2015-07-30  9:31     ` Michel Thierry
2015-07-30 10:04   ` [PATCH v7 " Michel Thierry
2015-07-31  4:35     ` Goel, Akash
2015-07-31 12:12     ` [PATCH v8 " Michel Thierry
2015-07-31 17:35       ` Goel, Akash
2015-08-03  8:34         ` Michel Thierry
2015-08-03  8:52       ` [PATCH v9 " Michel Thierry
2015-08-03  9:20         ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 07/19] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-07-30 10:05   ` [PATCH v7 " Michel Thierry
2015-07-31  4:20     ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 08/19] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-07-30  4:14   ` Goel, Akash
2015-07-30  9:36     ` Michel Thierry
2015-07-30 10:06   ` [PATCH v7 " Michel Thierry
2015-07-31  4:23     ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 09/19] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-07-30  4:19   ` Goel, Akash
2015-08-03  8:52   ` [PATCH v9 " Michel Thierry
2015-07-29 16:23 ` [PATCH v6 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-07-30  4:50   ` Goel, Akash
2015-08-03  8:53   ` [PATCH v9 " Michel Thierry
2015-08-03  9:23     ` Goel, Akash
2015-08-05 15:46     ` Daniel Vetter
2015-08-05 16:13       ` Michel Thierry
2015-07-29 16:23 ` [PATCH v6 11/19] drm/i915/gen8: Initialize PDPs and PML4 Michel Thierry
2015-07-30  4:56   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 12/19] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-07-30  5:09   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 13/19] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-07-30  5:20   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 14/19] drm/i915: object size needs to be u64 Michel Thierry
2015-07-30  5:22   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 15/19] drm/i915: batch_obj vm offset must " Michel Thierry
2015-07-30  5:23   ` Goel, Akash
2015-08-05 16:01   ` Daniel Vetter
2015-08-05 16:14     ` Michel Thierry
2015-08-06 12:30       ` Daniel Vetter
2015-07-29 16:24 ` [PATCH v6 16/19] drm/i915/userptr: Kill user_size limit check Michel Thierry
2015-07-30  5:25   ` Goel, Akash
2015-07-29 16:24 ` [PATCH v6 17/19] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-07-30  5:39   ` Goel, Akash
2015-08-05 15:58   ` Daniel Vetter
2015-08-05 16:14     ` Michel Thierry [this message]
2015-08-06 12:47       ` Daniel Vetter
2015-08-06 16:27         ` Michel Thierry
2015-08-07  7:55           ` Daniel Vetter
2015-07-29 16:24 ` [PATCH v6 18/19] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-07-30  5:49   ` Goel, Akash
2015-07-30 10:09   ` [PATCH v7 " Michel Thierry
2015-07-31 12:13     ` [PATCH v8 " Michel Thierry
2015-07-31 12:19       ` Chris Wilson
2015-07-31 12:35       ` Michel Thierry
2015-07-31 17:21         ` Goel, Akash
2015-07-29 16:24 ` [PATCH v6 19/19] drm/i915: Save some page table setup on repeated binds Michel Thierry
2015-07-30 11:26 ` [PATCH v6 00/19] 48-bit PPGTT Chris Wilson
2015-07-30 11:52   ` Michel Thierry
2015-07-30 12:13     ` Chris Wilson
2015-07-30 19:02     ` Chris Wilson
2015-08-03  9:51 ` Michel Thierry

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=55C23669.5000309@intel.com \
    --to=michel.thierry@intel.com \
    --cc=akash.goel@intel.com \
    --cc=daniel@ffwll.ch \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).