[PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp

[PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

While working on CHV DPIO powergating I relized DP .compute_config() was
clobbering lane_count etc. stored in intel_dp. This could cause problems
if we do the .compute_config() but later fail the modeset for some reason.
Any subsequent link re-training might then fail if intel_dp->lane_count
etc. got changed.

The reason I ran into this during the DPIO powergating work was that I may
need to know which lanes he active when shutting down the link. However
.compute_config() already clobbered that information by the time I need it.
By moving it to the pipe config we avoid that problem as well.

I also cleaned up the limited color range handling a bit while I was
in the neighborhood.

Ville Syrjälä (7):
  drm/i915: Clean up DP/HDMI limited color range handling
  drm/i915: Don't use link_bw for PLL setup
  drm/i915: Don't pass clock to DDI PLL select functions
  drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP
    .get_config()
  drm/i915: Move intel_dp->lane_count into pipe_config
  drm/i915: Don't use link_bw to select between TP1 and TP3
  drm/i915: Kill intel_dp->{link_bw,rate_select}

 drivers/gpu/drm/i915/i915_reg.h      |   3 +
 drivers/gpu/drm/i915/intel_ddi.c     |  41 ++++----
 drivers/gpu/drm/i915/intel_display.c |   7 +-
 drivers/gpu/drm/i915/intel_dp.c      | 177 ++++++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_dp_mst.c  |  19 ++--
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 drivers/gpu/drm/i915/intel_hdmi.c    |  26 +++--
 7 files changed, 155 insertions(+), 127 deletions(-)

-- 
2.3.6

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[PATCH 1/7] drm/i915: Clean up DP/HDMI limited color range handling

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we treat intel_{dp,hdmi}->color_range as partly user
controller value (via the property) but we also change it during
.compute_config() when using the "Automatic" mode. That is a bit
confusing, so let's just change things so that we store the user
property values in intel_dp, and only change what's stored in
pipe_config during .compute_config().

There should be no functional change.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 25 ++++++++++++-------------
 drivers/gpu/drm/i915/intel_drv.h  |  4 ++--
 drivers/gpu/drm/i915/intel_hdmi.c | 26 ++++++++++++--------------
 3 files changed, 26 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fcc64e5..decefa1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1455,15 +1455,13 @@ found:
 		 * CEA-861-E - 5.1 Default Encoding Parameters
 		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 		 */
-		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
-			intel_dp->color_range = DP_COLOR_RANGE_16_235;
-		else
-			intel_dp->color_range = 0;
+		pipe_config->limited_color_range =
+			bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
+	} else {
+		pipe_config->limited_color_range =
+			intel_dp->limited_color_range;
 	}
 
-	if (intel_dp->color_range)
-		pipe_config->limited_color_range = true;
-
 	intel_dp->lane_count = lane_count;
 
 	if (intel_dp->num_sink_rates) {
@@ -1605,8 +1603,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 			trans_dp &= ~TRANS_DP_ENH_FRAMING;
 		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
 	} else {
-		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
-			intel_dp->DP |= intel_dp->color_range;
+		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
+		    crtc->config->limited_color_range)
+			intel_dp->DP |= DP_COLOR_RANGE_16_235;
 
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 			intel_dp->DP |= DP_SYNC_HS_HIGH;
@@ -4663,7 +4662,7 @@ intel_dp_set_property(struct drm_connector *connector,
 
 	if (property == dev_priv->broadcast_rgb_property) {
 		bool old_auto = intel_dp->color_range_auto;
-		uint32_t old_range = intel_dp->color_range;
+		bool old_range = intel_dp->limited_color_range;
 
 		switch (val) {
 		case INTEL_BROADCAST_RGB_AUTO:
@@ -4671,18 +4670,18 @@ intel_dp_set_property(struct drm_connector *connector,
 			break;
 		case INTEL_BROADCAST_RGB_FULL:
 			intel_dp->color_range_auto = false;
-			intel_dp->color_range = 0;
+			intel_dp->limited_color_range = false;
 			break;
 		case INTEL_BROADCAST_RGB_LIMITED:
 			intel_dp->color_range_auto = false;
-			intel_dp->color_range = DP_COLOR_RANGE_16_235;
+			intel_dp->limited_color_range = true;
 			break;
 		default:
 			return -EINVAL;
 		}
 
 		if (old_auto == intel_dp->color_range_auto &&
-		    old_range == intel_dp->color_range)
+		    old_range == intel_dp->limited_color_range)
 			return 0;
 
 		goto done;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3f0a890..983a7a7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -669,7 +669,7 @@ struct cxsr_latency {
 struct intel_hdmi {
 	u32 hdmi_reg;
 	int ddc_bus;
-	uint32_t color_range;
+	bool limited_color_range;
 	bool color_range_auto;
 	bool has_hdmi_sink;
 	bool has_audio;
@@ -714,7 +714,7 @@ struct intel_dp {
 	uint32_t DP;
 	bool has_audio;
 	enum hdmi_force_audio force_audio;
-	uint32_t color_range;
+	bool limited_color_range;
 	bool color_range_auto;
 	uint8_t link_bw;
 	uint8_t rate_select;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c7e912b..ba845f7 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -848,8 +848,8 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
 	u32 hdmi_val;
 
 	hdmi_val = SDVO_ENCODING_HDMI;
-	if (!HAS_PCH_SPLIT(dev))
-		hdmi_val |= intel_hdmi->color_range;
+	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
+		hdmi_val |= HDMI_COLOR_RANGE_16_235;
 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -1257,11 +1257,12 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 
 	if (intel_hdmi->color_range_auto) {
 		/* See CEA-861-E - 5.1 Default Encoding Parameters */
-		if (pipe_config->has_hdmi_sink &&
-		    drm_match_cea_mode(adjusted_mode) > 1)
-			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
-		else
-			intel_hdmi->color_range = 0;
+		pipe_config->limited_color_range =
+			pipe_config->has_hdmi_sink &&
+			drm_match_cea_mode(adjusted_mode) > 1;
+	} else {
+		pipe_config->limited_color_range =
+			intel_hdmi->limited_color_range;
 	}
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
@@ -1270,9 +1271,6 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 		clock_12bpc *= 2;
 	}
 
-	if (intel_hdmi->color_range)
-		pipe_config->limited_color_range = true;
-
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 		pipe_config->has_pch_encoder = true;
 
@@ -1467,7 +1465,7 @@ intel_hdmi_set_property(struct drm_connector *connector,
 
 	if (property == dev_priv->broadcast_rgb_property) {
 		bool old_auto = intel_hdmi->color_range_auto;
-		uint32_t old_range = intel_hdmi->color_range;
+		bool old_range = intel_hdmi->limited_color_range;
 
 		switch (val) {
 		case INTEL_BROADCAST_RGB_AUTO:
@@ -1475,18 +1473,18 @@ intel_hdmi_set_property(struct drm_connector *connector,
 			break;
 		case INTEL_BROADCAST_RGB_FULL:
 			intel_hdmi->color_range_auto = false;
-			intel_hdmi->color_range = 0;
+			intel_hdmi->limited_color_range = false;
 			break;
 		case INTEL_BROADCAST_RGB_LIMITED:
 			intel_hdmi->color_range_auto = false;
-			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
+			intel_hdmi->limited_color_range = true;
 			break;
 		default:
 			return -EINVAL;
 		}
 
 		if (old_auto == intel_hdmi->color_range_auto &&
-		    old_range == intel_hdmi->color_range)
+		    old_range == intel_hdmi->limited_color_range)
 			return 0;
 
 		goto done;
-- 
2.3.6

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Re: [PATCH 1/7] drm/i915: Clean up DP/HDMI limited color range handling

[Sivakumar Thulasimani]

sdvo is still using color_range name in it's functions. would be good to
rename that as well along with dp & hdmi done here.

otherwise changes are fine
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On Monday 06 July 2015 05:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we treat intel_{dp,hdmi}->color_range as partly user
> controller value (via the property) but we also change it during
> .compute_config() when using the "Automatic" mode. That is a bit
> confusing, so let's just change things so that we store the user
> property values in intel_dp, and only change what's stored in
> pipe_config during .compute_config().
>
> There should be no functional change.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c   | 25 ++++++++++++-------------
>   drivers/gpu/drm/i915/intel_drv.h  |  4 ++--
>   drivers/gpu/drm/i915/intel_hdmi.c | 26 ++++++++++++--------------
>   3 files changed, 26 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fcc64e5..decefa1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1455,15 +1455,13 @@ found:
>   		 * CEA-861-E - 5.1 Default Encoding Parameters
>   		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
>   		 */
> -		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
> -			intel_dp->color_range = DP_COLOR_RANGE_16_235;
> -		else
> -			intel_dp->color_range = 0;
> +		pipe_config->limited_color_range =
> +			bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
> +	} else {
> +		pipe_config->limited_color_range =
> +			intel_dp->limited_color_range;
>   	}
>   
> -	if (intel_dp->color_range)
> -		pipe_config->limited_color_range = true;
> -
>   	intel_dp->lane_count = lane_count;
>   
>   	if (intel_dp->num_sink_rates) {
> @@ -1605,8 +1603,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>   			trans_dp &= ~TRANS_DP_ENH_FRAMING;
>   		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
>   	} else {
> -		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
> -			intel_dp->DP |= intel_dp->color_range;
> +		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> +		    crtc->config->limited_color_range)
> +			intel_dp->DP |= DP_COLOR_RANGE_16_235;
>   
>   		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>   			intel_dp->DP |= DP_SYNC_HS_HIGH;
> @@ -4663,7 +4662,7 @@ intel_dp_set_property(struct drm_connector *connector,
>   
>   	if (property == dev_priv->broadcast_rgb_property) {
>   		bool old_auto = intel_dp->color_range_auto;
> -		uint32_t old_range = intel_dp->color_range;
> +		bool old_range = intel_dp->limited_color_range;
>   
>   		switch (val) {
>   		case INTEL_BROADCAST_RGB_AUTO:
> @@ -4671,18 +4670,18 @@ intel_dp_set_property(struct drm_connector *connector,
>   			break;
>   		case INTEL_BROADCAST_RGB_FULL:
>   			intel_dp->color_range_auto = false;
> -			intel_dp->color_range = 0;
> +			intel_dp->limited_color_range = false;
>   			break;
>   		case INTEL_BROADCAST_RGB_LIMITED:
>   			intel_dp->color_range_auto = false;
> -			intel_dp->color_range = DP_COLOR_RANGE_16_235;
> +			intel_dp->limited_color_range = true;
>   			break;
>   		default:
>   			return -EINVAL;
>   		}
>   
>   		if (old_auto == intel_dp->color_range_auto &&
> -		    old_range == intel_dp->color_range)
> +		    old_range == intel_dp->limited_color_range)
>   			return 0;
>   
>   		goto done;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3f0a890..983a7a7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -669,7 +669,7 @@ struct cxsr_latency {
>   struct intel_hdmi {
>   	u32 hdmi_reg;
>   	int ddc_bus;
> -	uint32_t color_range;
> +	bool limited_color_range;
>   	bool color_range_auto;
>   	bool has_hdmi_sink;
>   	bool has_audio;
> @@ -714,7 +714,7 @@ struct intel_dp {
>   	uint32_t DP;
>   	bool has_audio;
>   	enum hdmi_force_audio force_audio;
> -	uint32_t color_range;
> +	bool limited_color_range;
>   	bool color_range_auto;
>   	uint8_t link_bw;
>   	uint8_t rate_select;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index c7e912b..ba845f7 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -848,8 +848,8 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
>   	u32 hdmi_val;
>   
>   	hdmi_val = SDVO_ENCODING_HDMI;
> -	if (!HAS_PCH_SPLIT(dev))
> -		hdmi_val |= intel_hdmi->color_range;
> +	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
> +		hdmi_val |= HDMI_COLOR_RANGE_16_235;
>   	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
>   		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
>   	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> @@ -1257,11 +1257,12 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
>   
>   	if (intel_hdmi->color_range_auto) {
>   		/* See CEA-861-E - 5.1 Default Encoding Parameters */
> -		if (pipe_config->has_hdmi_sink &&
> -		    drm_match_cea_mode(adjusted_mode) > 1)
> -			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
> -		else
> -			intel_hdmi->color_range = 0;
> +		pipe_config->limited_color_range =
> +			pipe_config->has_hdmi_sink &&
> +			drm_match_cea_mode(adjusted_mode) > 1;
> +	} else {
> +		pipe_config->limited_color_range =
> +			intel_hdmi->limited_color_range;
>   	}
>   
>   	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
> @@ -1270,9 +1271,6 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
>   		clock_12bpc *= 2;
>   	}
>   
> -	if (intel_hdmi->color_range)
> -		pipe_config->limited_color_range = true;
> -
>   	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
>   		pipe_config->has_pch_encoder = true;
>   
> @@ -1467,7 +1465,7 @@ intel_hdmi_set_property(struct drm_connector *connector,
>   
>   	if (property == dev_priv->broadcast_rgb_property) {
>   		bool old_auto = intel_hdmi->color_range_auto;
> -		uint32_t old_range = intel_hdmi->color_range;
> +		bool old_range = intel_hdmi->limited_color_range;
>   
>   		switch (val) {
>   		case INTEL_BROADCAST_RGB_AUTO:
> @@ -1475,18 +1473,18 @@ intel_hdmi_set_property(struct drm_connector *connector,
>   			break;
>   		case INTEL_BROADCAST_RGB_FULL:
>   			intel_hdmi->color_range_auto = false;
> -			intel_hdmi->color_range = 0;
> +			intel_hdmi->limited_color_range = false;
>   			break;
>   		case INTEL_BROADCAST_RGB_LIMITED:
>   			intel_hdmi->color_range_auto = false;
> -			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
> +			intel_hdmi->limited_color_range = true;
>   			break;
>   		default:
>   			return -EINVAL;
>   		}
>   
>   		if (old_auto == intel_hdmi->color_range_auto &&
> -		    old_range == intel_hdmi->color_range)
> +		    old_range == intel_hdmi->limited_color_range)
>   			return 0;
>   
>   		goto done;

-- 
regards,
Sivakumar Thulasimani

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Re: [PATCH 1/7] drm/i915: Clean up DP/HDMI limited color range handling

[Ville Syrjälä]

On Thu, Aug 13, 2015 at 11:46:56AM +0530, Sivakumar Thulasimani wrote:
> sdvo is still using color_range name in it's functions. would be good to
> rename that as well along with dp & hdmi done here.

Doh. I forgot about sdvo completely. I'll take a look to make sure it
conforms to the same style. Thanks for spotting it.

> 
> otherwise changes are fine
> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> 
> On Monday 06 July 2015 05:40 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Currently we treat intel_{dp,hdmi}->color_range as partly user
> > controller value (via the property) but we also change it during
> > .compute_config() when using the "Automatic" mode. That is a bit
> > confusing, so let's just change things so that we store the user
> > property values in intel_dp, and only change what's stored in
> > pipe_config during .compute_config().
> >
> > There should be no functional change.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_dp.c   | 25 ++++++++++++-------------
> >   drivers/gpu/drm/i915/intel_drv.h  |  4 ++--
> >   drivers/gpu/drm/i915/intel_hdmi.c | 26 ++++++++++++--------------
> >   3 files changed, 26 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index fcc64e5..decefa1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1455,15 +1455,13 @@ found:
> >   		 * CEA-861-E - 5.1 Default Encoding Parameters
> >   		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
> >   		 */
> > -		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
> > -			intel_dp->color_range = DP_COLOR_RANGE_16_235;
> > -		else
> > -			intel_dp->color_range = 0;
> > +		pipe_config->limited_color_range =
> > +			bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
> > +	} else {
> > +		pipe_config->limited_color_range =
> > +			intel_dp->limited_color_range;
> >   	}
> >   
> > -	if (intel_dp->color_range)
> > -		pipe_config->limited_color_range = true;
> > -
> >   	intel_dp->lane_count = lane_count;
> >   
> >   	if (intel_dp->num_sink_rates) {
> > @@ -1605,8 +1603,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
> >   			trans_dp &= ~TRANS_DP_ENH_FRAMING;
> >   		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
> >   	} else {
> > -		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
> > -			intel_dp->DP |= intel_dp->color_range;
> > +		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> > +		    crtc->config->limited_color_range)
> > +			intel_dp->DP |= DP_COLOR_RANGE_16_235;
> >   
> >   		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> >   			intel_dp->DP |= DP_SYNC_HS_HIGH;
> > @@ -4663,7 +4662,7 @@ intel_dp_set_property(struct drm_connector *connector,
> >   
> >   	if (property == dev_priv->broadcast_rgb_property) {
> >   		bool old_auto = intel_dp->color_range_auto;
> > -		uint32_t old_range = intel_dp->color_range;
> > +		bool old_range = intel_dp->limited_color_range;
> >   
> >   		switch (val) {
> >   		case INTEL_BROADCAST_RGB_AUTO:
> > @@ -4671,18 +4670,18 @@ intel_dp_set_property(struct drm_connector *connector,
> >   			break;
> >   		case INTEL_BROADCAST_RGB_FULL:
> >   			intel_dp->color_range_auto = false;
> > -			intel_dp->color_range = 0;
> > +			intel_dp->limited_color_range = false;
> >   			break;
> >   		case INTEL_BROADCAST_RGB_LIMITED:
> >   			intel_dp->color_range_auto = false;
> > -			intel_dp->color_range = DP_COLOR_RANGE_16_235;
> > +			intel_dp->limited_color_range = true;
> >   			break;
> >   		default:
> >   			return -EINVAL;
> >   		}
> >   
> >   		if (old_auto == intel_dp->color_range_auto &&
> > -		    old_range == intel_dp->color_range)
> > +		    old_range == intel_dp->limited_color_range)
> >   			return 0;
> >   
> >   		goto done;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 3f0a890..983a7a7 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -669,7 +669,7 @@ struct cxsr_latency {
> >   struct intel_hdmi {
> >   	u32 hdmi_reg;
> >   	int ddc_bus;
> > -	uint32_t color_range;
> > +	bool limited_color_range;
> >   	bool color_range_auto;
> >   	bool has_hdmi_sink;
> >   	bool has_audio;
> > @@ -714,7 +714,7 @@ struct intel_dp {
> >   	uint32_t DP;
> >   	bool has_audio;
> >   	enum hdmi_force_audio force_audio;
> > -	uint32_t color_range;
> > +	bool limited_color_range;
> >   	bool color_range_auto;
> >   	uint8_t link_bw;
> >   	uint8_t rate_select;
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index c7e912b..ba845f7 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -848,8 +848,8 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
> >   	u32 hdmi_val;
> >   
> >   	hdmi_val = SDVO_ENCODING_HDMI;
> > -	if (!HAS_PCH_SPLIT(dev))
> > -		hdmi_val |= intel_hdmi->color_range;
> > +	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
> > +		hdmi_val |= HDMI_COLOR_RANGE_16_235;
> >   	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> >   		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
> >   	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> > @@ -1257,11 +1257,12 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> >   
> >   	if (intel_hdmi->color_range_auto) {
> >   		/* See CEA-861-E - 5.1 Default Encoding Parameters */
> > -		if (pipe_config->has_hdmi_sink &&
> > -		    drm_match_cea_mode(adjusted_mode) > 1)
> > -			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
> > -		else
> > -			intel_hdmi->color_range = 0;
> > +		pipe_config->limited_color_range =
> > +			pipe_config->has_hdmi_sink &&
> > +			drm_match_cea_mode(adjusted_mode) > 1;
> > +	} else {
> > +		pipe_config->limited_color_range =
> > +			intel_hdmi->limited_color_range;
> >   	}
> >   
> >   	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
> > @@ -1270,9 +1271,6 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> >   		clock_12bpc *= 2;
> >   	}
> >   
> > -	if (intel_hdmi->color_range)
> > -		pipe_config->limited_color_range = true;
> > -
> >   	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
> >   		pipe_config->has_pch_encoder = true;
> >   
> > @@ -1467,7 +1465,7 @@ intel_hdmi_set_property(struct drm_connector *connector,
> >   
> >   	if (property == dev_priv->broadcast_rgb_property) {
> >   		bool old_auto = intel_hdmi->color_range_auto;
> > -		uint32_t old_range = intel_hdmi->color_range;
> > +		bool old_range = intel_hdmi->limited_color_range;
> >   
> >   		switch (val) {
> >   		case INTEL_BROADCAST_RGB_AUTO:
> > @@ -1475,18 +1473,18 @@ intel_hdmi_set_property(struct drm_connector *connector,
> >   			break;
> >   		case INTEL_BROADCAST_RGB_FULL:
> >   			intel_hdmi->color_range_auto = false;
> > -			intel_hdmi->color_range = 0;
> > +			intel_hdmi->limited_color_range = false;
> >   			break;
> >   		case INTEL_BROADCAST_RGB_LIMITED:
> >   			intel_hdmi->color_range_auto = false;
> > -			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
> > +			intel_hdmi->limited_color_range = true;
> >   			break;
> >   		default:
> >   			return -EINVAL;
> >   		}
> >   
> >   		if (old_auto == intel_hdmi->color_range_auto &&
> > -		    old_range == intel_hdmi->color_range)
> > +		    old_range == intel_hdmi->limited_color_range)
> >   			return 0;
> >   
> >   		goto done;
> 
> -- 
> regards,
> Sivakumar Thulasimani

-- 
Ville Syrjälä
Intel OTC
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[PATCH 2/7] drm/i915: Don't use link_bw for PLL setup

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use port_clock instead of link_bw when picking the PLL parameters for
DP. link_bw may be zero with an eDP 1.4 sink that supports
DP_LINK_RATE_SET so we shouln't use it for anything other than feed it
to the sink appropriately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 11 ++++------
 drivers/gpu/drm/i915/intel_dp.c  | 44 ++++++++++++++++++++--------------------
 2 files changed, 26 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9a40bfb..0d3cc98 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1574,17 +1574,14 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
 			 wrpll_params.central_freq;
 	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
-		struct drm_encoder *encoder = &intel_encoder->base;
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
+		switch (crtc_state->port_clock / 2) {
+		case 81000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
 			break;
-		case DP_LINK_BW_2_7:
+		case 135000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
 			break;
-		case DP_LINK_BW_5_4:
+		case 270000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
 			break;
 		}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index decefa1..3dd4342 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -48,28 +48,28 @@
 #define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
 
 struct dp_link_dpll {
-	int link_bw;
+	int clock;
 	struct dpll dpll;
 };
 
 static const struct dp_link_dpll gen4_dpll[] = {
-	{ DP_LINK_BW_1_62,
+	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
-	{ DP_LINK_BW_2_7,
+	{ 270000,
 		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
 };
 
 static const struct dp_link_dpll pch_dpll[] = {
-	{ DP_LINK_BW_1_62,
+	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
-	{ DP_LINK_BW_2_7,
+	{ 270000,
 		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 };
 
 static const struct dp_link_dpll vlv_dpll[] = {
-	{ DP_LINK_BW_1_62,
+	{ 162000,
 		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
-	{ DP_LINK_BW_2_7,
+	{ 270000,
 		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 };
 
@@ -83,11 +83,11 @@ static const struct dp_link_dpll chv_dpll[] = {
 	 * m2 is stored in fixed point format using formula below
 	 * (m2_int << 22) | m2_fraction
 	 */
-	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
+	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
 		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
-	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
+	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
 		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
-	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
+	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
@@ -1099,7 +1099,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
 }
 
 static void
-skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
+skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
 {
 	u32 ctrl1;
 
@@ -1111,7 +1111,7 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 	pipe_config->dpll_hw_state.cfgcr2 = 0;
 
 	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
-	switch (link_clock / 2) {
+	switch (pipe_config->port_clock / 2) {
 	case 81000:
 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 					      SKL_DPLL0);
@@ -1145,19 +1145,19 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 }
 
 static void
-hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
+hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
 {
 	memset(&pipe_config->dpll_hw_state, 0,
 	       sizeof(pipe_config->dpll_hw_state));
 
-	switch (link_bw) {
-	case DP_LINK_BW_1_62:
+	switch (pipe_config->port_clock / 2) {
+	case 81000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 		break;
-	case DP_LINK_BW_2_7:
+	case 135000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 		break;
-	case DP_LINK_BW_5_4:
+	case 270000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 		break;
 	}
@@ -1204,7 +1204,7 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 
 static void
 intel_dp_set_clock(struct intel_encoder *encoder,
-		   struct intel_crtc_state *pipe_config, int link_bw)
+		   struct intel_crtc_state *pipe_config)
 {
 	struct drm_device *dev = encoder->base.dev;
 	const struct dp_link_dpll *divisor = NULL;
@@ -1226,7 +1226,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 
 	if (divisor && count) {
 		for (i = 0; i < count; i++) {
-			if (link_bw == divisor[i].link_bw) {
+			if (pipe_config->port_clock == divisor[i].clock) {
 				pipe_config->dpll = divisor[i].dpll;
 				pipe_config->clock_set = true;
 				break;
@@ -1498,13 +1498,13 @@ found:
 	}
 
 	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
-		skl_edp_set_pll_config(pipe_config, common_rates[clock]);
+		skl_edp_set_pll_config(pipe_config);
 	else if (IS_BROXTON(dev))
 		/* handled in ddi */;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
+		hsw_dp_set_ddi_pll_sel(pipe_config);
 	else
-		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
+		intel_dp_set_clock(encoder, pipe_config);
 
 	return true;
 }
-- 
2.3.6

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Re: [PATCH 2/7] drm/i915: Don't use link_bw for PLL setup

[Sivakumar Thulasimani]

[-- Attachment #1.1: Type: text/plain, Size: 6509 bytes --]


Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>


On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use port_clock instead of link_bw when picking the PLL parameters for
> DP. link_bw may be zero with an eDP 1.4 sink that supports
> DP_LINK_RATE_SET so we shouln't use it for anything other than feed it
shouldn't ?
> to the sink appropriately.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ddi.c | 11 ++++------
>   drivers/gpu/drm/i915/intel_dp.c  | 44 ++++++++++++++++++++--------------------
>   2 files changed, 26 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9a40bfb..0d3cc98 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1574,17 +1574,14 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>   			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
>   			 wrpll_params.central_freq;
>   	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
> -		struct drm_encoder *encoder = &intel_encoder->base;
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> +		switch (crtc_state->port_clock / 2) {
> +		case 81000:
>   			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
>   			break;
> -		case DP_LINK_BW_2_7:
> +		case 135000:
>   			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
>   			break;
> -		case DP_LINK_BW_5_4:
> +		case 270000:
>   			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
>   			break;
>   		}
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index decefa1..3dd4342 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -48,28 +48,28 @@
>   #define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
>   
>   struct dp_link_dpll {
> -	int link_bw;
> +	int clock;
>   	struct dpll dpll;
>   };
>   
>   static const struct dp_link_dpll gen4_dpll[] = {
> -	{ DP_LINK_BW_1_62,
> +	{ 162000,
>   		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
> -	{ DP_LINK_BW_2_7,
> +	{ 270000,
>   		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
>   };
>   
>   static const struct dp_link_dpll pch_dpll[] = {
> -	{ DP_LINK_BW_1_62,
> +	{ 162000,
>   		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
> -	{ DP_LINK_BW_2_7,
> +	{ 270000,
>   		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
>   };
>   
>   static const struct dp_link_dpll vlv_dpll[] = {
> -	{ DP_LINK_BW_1_62,
> +	{ 162000,
>   		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
> -	{ DP_LINK_BW_2_7,
> +	{ 270000,
>   		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
>   };
>   
> @@ -83,11 +83,11 @@ static const struct dp_link_dpll chv_dpll[] = {
>   	 * m2 is stored in fixed point format using formula below
>   	 * (m2_int << 22) | m2_fraction
>   	 */
> -	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
> +	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
>   		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
> -	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
> +	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
>   		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
> -	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
> +	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>   };
>   
> @@ -1099,7 +1099,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
>   }
>   
>   static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
> +skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>   {
>   	u32 ctrl1;
>   
> @@ -1111,7 +1111,7 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>   	pipe_config->dpll_hw_state.cfgcr2 = 0;
>   
>   	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
> -	switch (link_clock / 2) {
> +	switch (pipe_config->port_clock / 2) {
>   	case 81000:
>   		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
>   					      SKL_DPLL0);
> @@ -1145,19 +1145,19 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>   }
>   
>   static void
> -hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
> +hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
>   {
>   	memset(&pipe_config->dpll_hw_state, 0,
>   	       sizeof(pipe_config->dpll_hw_state));
>   
> -	switch (link_bw) {
> -	case DP_LINK_BW_1_62:
> +	switch (pipe_config->port_clock / 2) {
> +	case 81000:
>   		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
>   		break;
> -	case DP_LINK_BW_2_7:
> +	case 135000:
>   		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
>   		break;
> -	case DP_LINK_BW_5_4:
> +	case 270000:
>   		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
>   		break;
>   	}
> @@ -1204,7 +1204,7 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>   
>   static void
>   intel_dp_set_clock(struct intel_encoder *encoder,
> -		   struct intel_crtc_state *pipe_config, int link_bw)
> +		   struct intel_crtc_state *pipe_config)
>   {
>   	struct drm_device *dev = encoder->base.dev;
>   	const struct dp_link_dpll *divisor = NULL;
> @@ -1226,7 +1226,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>   
>   	if (divisor && count) {
>   		for (i = 0; i < count; i++) {
> -			if (link_bw == divisor[i].link_bw) {
> +			if (pipe_config->port_clock == divisor[i].clock) {
>   				pipe_config->dpll = divisor[i].dpll;
>   				pipe_config->clock_set = true;
>   				break;
> @@ -1498,13 +1498,13 @@ found:
>   	}
>   
>   	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
> -		skl_edp_set_pll_config(pipe_config, common_rates[clock]);
> +		skl_edp_set_pll_config(pipe_config);
>   	else if (IS_BROXTON(dev))
>   		/* handled in ddi */;
>   	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
> +		hsw_dp_set_ddi_pll_sel(pipe_config);
>   	else
> -		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
> +		intel_dp_set_clock(encoder, pipe_config);
>   
>   	return true;
>   }

-- 
regards,
Sivakumar


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[PATCH v2 2/7] drm/i915: Don't use link_bw for PLL setup

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use port_clock instead of link_bw when picking the PLL parameters for
DP. link_bw may be zero with an eDP 1.4 sink that supports
DP_LINK_RATE_SET so we shouldn't use it for anything other than feed it
to the sink appropriately.

v2: Fix typo in commit message (Sivakumar)

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 11 ++++------
 drivers/gpu/drm/i915/intel_dp.c  | 44 ++++++++++++++++++++--------------------
 2 files changed, 26 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 110d546..b183a3d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1574,17 +1574,14 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
 			 wrpll_params.central_freq;
 	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
-		struct drm_encoder *encoder = &intel_encoder->base;
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
+		switch (crtc_state->port_clock / 2) {
+		case 81000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
 			break;
-		case DP_LINK_BW_2_7:
+		case 135000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
 			break;
-		case DP_LINK_BW_5_4:
+		case 270000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
 			break;
 		}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fe5f4a2..3027c36 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -48,28 +48,28 @@
 #define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
 
 struct dp_link_dpll {
-	int link_bw;
+	int clock;
 	struct dpll dpll;
 };
 
 static const struct dp_link_dpll gen4_dpll[] = {
-	{ DP_LINK_BW_1_62,
+	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
-	{ DP_LINK_BW_2_7,
+	{ 270000,
 		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
 };
 
 static const struct dp_link_dpll pch_dpll[] = {
-	{ DP_LINK_BW_1_62,
+	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
-	{ DP_LINK_BW_2_7,
+	{ 270000,
 		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 };
 
 static const struct dp_link_dpll vlv_dpll[] = {
-	{ DP_LINK_BW_1_62,
+	{ 162000,
 		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
-	{ DP_LINK_BW_2_7,
+	{ 270000,
 		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 };
 
@@ -83,11 +83,11 @@ static const struct dp_link_dpll chv_dpll[] = {
 	 * m2 is stored in fixed point format using formula below
 	 * (m2_int << 22) | m2_fraction
 	 */
-	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
+	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
 		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
-	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
+	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
 		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
-	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
+	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
@@ -1133,7 +1133,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
 }
 
 static void
-skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
+skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
 {
 	u32 ctrl1;
 
@@ -1145,7 +1145,7 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 	pipe_config->dpll_hw_state.cfgcr2 = 0;
 
 	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
-	switch (link_clock / 2) {
+	switch (pipe_config->port_clock / 2) {
 	case 81000:
 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 					      SKL_DPLL0);
@@ -1179,19 +1179,19 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 }
 
 static void
-hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
+hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
 {
 	memset(&pipe_config->dpll_hw_state, 0,
 	       sizeof(pipe_config->dpll_hw_state));
 
-	switch (link_bw) {
-	case DP_LINK_BW_1_62:
+	switch (pipe_config->port_clock / 2) {
+	case 81000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 		break;
-	case DP_LINK_BW_2_7:
+	case 135000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 		break;
-	case DP_LINK_BW_5_4:
+	case 270000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 		break;
 	}
@@ -1238,7 +1238,7 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 
 static void
 intel_dp_set_clock(struct intel_encoder *encoder,
-		   struct intel_crtc_state *pipe_config, int link_bw)
+		   struct intel_crtc_state *pipe_config)
 {
 	struct drm_device *dev = encoder->base.dev;
 	const struct dp_link_dpll *divisor = NULL;
@@ -1260,7 +1260,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 
 	if (divisor && count) {
 		for (i = 0; i < count; i++) {
-			if (link_bw == divisor[i].link_bw) {
+			if (pipe_config->port_clock == divisor[i].clock) {
 				pipe_config->dpll = divisor[i].dpll;
 				pipe_config->clock_set = true;
 				break;
@@ -1535,13 +1535,13 @@ found:
 	}
 
 	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
-		skl_edp_set_pll_config(pipe_config, common_rates[clock]);
+		skl_edp_set_pll_config(pipe_config);
 	else if (IS_BROXTON(dev))
 		/* handled in ddi */;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
+		hsw_dp_set_ddi_pll_sel(pipe_config);
 	else
-		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
+		intel_dp_set_clock(encoder, pipe_config);
 
 	return true;
 }
-- 
2.4.6

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[PATCH 3/7] drm/i915: Don't pass clock to DDI PLL select functions

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All the *_ddi_pll_select() functions get passed the port_clock and pipe
config as parameters. We only need to pass the pipe config, and the
functions can dig up the port_clock themselves.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0d3cc98..96fb472 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1262,9 +1262,10 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 static bool
 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 		   struct intel_crtc_state *crtc_state,
-		   struct intel_encoder *intel_encoder,
-		   int clock)
+		   struct intel_encoder *intel_encoder)
 {
+	int clock = crtc_state->port_clock;
+
 	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 		struct intel_shared_dpll *pll;
 		uint32_t val;
@@ -1543,11 +1544,11 @@ skip_remaining_dividers:
 static bool
 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 		   struct intel_crtc_state *crtc_state,
-		   struct intel_encoder *intel_encoder,
-		   int clock)
+		   struct intel_encoder *intel_encoder)
 {
 	struct intel_shared_dpll *pll;
 	uint32_t ctrl1, cfgcr1, cfgcr2;
+	int clock = crtc_state->port_clock;
 
 	/*
 	 * See comment in intel_dpll_hw_state to understand why we always use 0
@@ -1635,14 +1636,14 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = {
 static bool
 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 		   struct intel_crtc_state *crtc_state,
-		   struct intel_encoder *intel_encoder,
-		   int clock)
+		   struct intel_encoder *intel_encoder)
 {
 	struct intel_shared_dpll *pll;
 	struct bxt_clk_div clk_div = {0};
 	int vco = 0;
 	uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
 	uint32_t lanestagger;
+	int clock = crtc_state->port_clock;
 
 	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 		intel_clock_t best_clock;
@@ -1770,17 +1771,16 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct intel_encoder *intel_encoder =
 		intel_ddi_get_crtc_new_encoder(crtc_state);
-	int clock = crtc_state->port_clock;
 
 	if (IS_SKYLAKE(dev))
 		return skl_ddi_pll_select(intel_crtc, crtc_state,
-					  intel_encoder, clock);
+					  intel_encoder);
 	else if (IS_BROXTON(dev))
 		return bxt_ddi_pll_select(intel_crtc, crtc_state,
-					  intel_encoder, clock);
+					  intel_encoder);
 	else
 		return hsw_ddi_pll_select(intel_crtc, crtc_state,
-					  intel_encoder, clock);
+					  intel_encoder);
 }
 
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
-- 
2.3.6

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Re: [PATCH 3/7] drm/i915: Don't pass clock to DDI PLL select functions

[Sivakumar Thulasimani]

[-- Attachment #1.1: Type: text/plain, Size: 3197 bytes --]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>


On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All the *_ddi_pll_select() functions get passed the port_clock and pipe
> config as parameters. We only need to pass the pipe config, and the
> functions can dig up the port_clock themselves.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++----------
>   1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0d3cc98..96fb472 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1262,9 +1262,10 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
>   static bool
>   hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		   struct intel_crtc_state *crtc_state,
> -		   struct intel_encoder *intel_encoder,
> -		   int clock)
> +		   struct intel_encoder *intel_encoder)
>   {
> +	int clock = crtc_state->port_clock;
> +
>   	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
>   		struct intel_shared_dpll *pll;
>   		uint32_t val;
> @@ -1543,11 +1544,11 @@ skip_remaining_dividers:
>   static bool
>   skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		   struct intel_crtc_state *crtc_state,
> -		   struct intel_encoder *intel_encoder,
> -		   int clock)
> +		   struct intel_encoder *intel_encoder)
>   {
>   	struct intel_shared_dpll *pll;
>   	uint32_t ctrl1, cfgcr1, cfgcr2;
> +	int clock = crtc_state->port_clock;
>   
>   	/*
>   	 * See comment in intel_dpll_hw_state to understand why we always use 0
> @@ -1635,14 +1636,14 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = {
>   static bool
>   bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		   struct intel_crtc_state *crtc_state,
> -		   struct intel_encoder *intel_encoder,
> -		   int clock)
> +		   struct intel_encoder *intel_encoder)
>   {
>   	struct intel_shared_dpll *pll;
>   	struct bxt_clk_div clk_div = {0};
>   	int vco = 0;
>   	uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
>   	uint32_t lanestagger;
> +	int clock = crtc_state->port_clock;
>   
>   	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
>   		intel_clock_t best_clock;
> @@ -1770,17 +1771,16 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
>   	struct drm_device *dev = intel_crtc->base.dev;
>   	struct intel_encoder *intel_encoder =
>   		intel_ddi_get_crtc_new_encoder(crtc_state);
> -	int clock = crtc_state->port_clock;
>   
>   	if (IS_SKYLAKE(dev))
>   		return skl_ddi_pll_select(intel_crtc, crtc_state,
> -					  intel_encoder, clock);
> +					  intel_encoder);
>   	else if (IS_BROXTON(dev))
>   		return bxt_ddi_pll_select(intel_crtc, crtc_state,
> -					  intel_encoder, clock);
> +					  intel_encoder);
>   	else
>   		return hsw_ddi_pll_select(intel_crtc, crtc_state,
> -					  intel_encoder, clock);
> +					  intel_encoder);
>   }
>   
>   void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)

-- 
regards,
Sivakumar


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[PATCH 4/7] drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP .get_config()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use a separate variable for the TRANS_DP_CTL value instead of reusing
'tmp' that otherwise contains the DP port register value.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3dd4342..b6ba02e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2245,13 +2245,14 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
 
 	if (HAS_PCH_CPT(dev) && port != PORT_A) {
-		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
-		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
+		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
+
+		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
 			flags |= DRM_MODE_FLAG_PHSYNC;
 		else
 			flags |= DRM_MODE_FLAG_NHSYNC;
 
-		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
+		if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
 			flags |= DRM_MODE_FLAG_PVSYNC;
 		else
 			flags |= DRM_MODE_FLAG_NVSYNC;
-- 
2.3.6

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Re: [PATCH 4/7] drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP .get_config()

[Sivakumar Thulasimani]

[-- Attachment #1.1: Type: text/plain, Size: 1444 bytes --]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>



On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use a separate variable for the TRANS_DP_CTL value instead of reusing
> 'tmp' that otherwise contains the DP port register value.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3dd4342..b6ba02e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2245,13 +2245,14 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>   	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
>   
>   	if (HAS_PCH_CPT(dev) && port != PORT_A) {
> -		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
> -		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
> +		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
> +
> +		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
>   			flags |= DRM_MODE_FLAG_PHSYNC;
>   		else
>   			flags |= DRM_MODE_FLAG_NHSYNC;
>   
> -		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
> +		if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
>   			flags |= DRM_MODE_FLAG_PVSYNC;
>   		else
>   			flags |= DRM_MODE_FLAG_NVSYNC;

-- 
regards,
Sivakumar


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[PATCH 5/7] drm/i915: Move intel_dp->lane_count into pipe_config

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we clobber intel_dp->lane_count in compute config, which means
after a rejected modeset we may no longer be able to retrain the current
link. Move lane_count into pipe_config to avoid that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  3 ++
 drivers/gpu/drm/i915/intel_ddi.c     | 10 +++---
 drivers/gpu/drm/i915/intel_display.c |  7 +++--
 drivers/gpu/drm/i915/intel_dp.c      | 60 ++++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_dp_mst.c  |  6 +++-
 drivers/gpu/drm/i915/intel_drv.h     |  3 +-
 6 files changed, 61 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d5c794a..f5dc75c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4096,6 +4096,7 @@ enum skl_disp_power_wells {
 /* How many wires to use. I guess 3 was too hard */
 #define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
 #define   DP_PORT_WIDTH_MASK		(7 << 19)
+#define   DP_PORT_WIDTH_SHIFT		19
 
 /* Mystic DPCD version 1.1 special mode */
 #define   DP_ENHANCED_FRAMING		(1 << 18)
@@ -7128,6 +7129,8 @@ enum skl_disp_power_wells {
 #define  DDI_BUF_IS_IDLE			(1<<7)
 #define  DDI_A_4_LANES				(1<<4)
 #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
+#define  DDI_PORT_WIDTH_MASK			(7 << 1)
+#define  DDI_PORT_WIDTH_SHIFT			1
 #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
 
 /* DDI Buffer Translations */
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 96fb472..8df596d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -723,11 +723,11 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_digital_port *intel_dig_port =
 		enc_to_dig_port(&encoder->base);
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 
 	intel_dp->DP = intel_dig_port->saved_port_bits |
 		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
-	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
-
+	intel_dp->DP |= DDI_PORT_WIDTH(crtc->config->lane_count);
 }
 
 static struct intel_encoder *
@@ -1913,7 +1913,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 		} else
 			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 
-		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
+		temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
 	} else if (type == INTEL_OUTPUT_DP_MST) {
 		struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
 
@@ -1922,7 +1922,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 		} else
 			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 
-		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
+		temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
 	} else {
 		WARN(1, "Invalid encoder type %d for pipe %c\n",
 		     intel_encoder->type, pipe_name(pipe));
@@ -3072,6 +3072,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	case TRANS_DDI_MODE_SELECT_DP_SST:
 	case TRANS_DDI_MODE_SELECT_DP_MST:
 		pipe_config->has_dp_encoder = true;
+		pipe_config->lane_count =
+			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
 		intel_dp_get_m_n(intel_crtc, pipe_config);
 		break;
 	default:
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 136b533..fe7e6d6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11981,14 +11981,16 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
 		      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
 		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
 		      pipe_config->fdi_m_n.tu);
-	DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
 		      pipe_config->has_dp_encoder,
+		      pipe_config->lane_count,
 		      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
 		      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
 		      pipe_config->dp_m_n.tu);
 
-	DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
+	DRM_DEBUG_KMS("dp: %i, lanes %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
 		      pipe_config->has_dp_encoder,
+		      pipe_config->lane_count,
 		      pipe_config->dp_m2_n2.gmch_m,
 		      pipe_config->dp_m2_n2.gmch_n,
 		      pipe_config->dp_m2_n2.link_m,
@@ -12456,6 +12458,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_I(fdi_m_n.tu);
 
 	PIPE_CONF_CHECK_I(has_dp_encoder);
+	PIPE_CONF_CHECK_I(lane_count);
 
 	if (INTEL_INFO(dev)->gen < 8) {
 		PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b6ba02e..da036e8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1462,7 +1462,7 @@ found:
 			intel_dp->limited_color_range;
 	}
 
-	intel_dp->lane_count = lane_count;
+	pipe_config->lane_count = lane_count;
 
 	if (intel_dp->num_sink_rates) {
 		intel_dp->link_bw = 0;
@@ -1478,7 +1478,7 @@ found:
 	pipe_config->port_clock = common_rates[clock];
 
 	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
-		      intel_dp->link_bw, intel_dp->lane_count,
+		      intel_dp->link_bw, pipe_config->lane_count,
 		      pipe_config->port_clock, bpp);
 	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 		      mode_rate, link_avail);
@@ -1573,7 +1573,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 
 	/* Handle DP bits in common between all three register formats */
 	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
-	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
+	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
 
 	if (crtc->config->has_audio)
 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
@@ -2276,6 +2276,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 
 	pipe_config->has_dp_encoder = true;
 
+	pipe_config->lane_count =
+		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
+
 	intel_dp_get_m_n(crtc, pipe_config);
 
 	if (port == PORT_A) {
@@ -3301,13 +3304,15 @@ static void
 intel_get_adjust_train(struct intel_dp *intel_dp,
 		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	uint8_t v = 0;
 	uint8_t p = 0;
 	int lane;
 	uint8_t voltage_max;
 	uint8_t preemph_max;
 
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+	for (lane = 0; lane < crtc->config->lane_count; lane++) {
 		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 
@@ -3476,8 +3481,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 			uint8_t dp_train_pat)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = intel_dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv =
+		to_i915(intel_dig_port->base.base.dev);
+	struct intel_crtc *crtc =
+		to_intel_crtc(intel_dig_port->base.base.crtc);
 	uint8_t buf[sizeof(intel_dp->train_set) + 1];
 	int ret, len;
 
@@ -3493,8 +3500,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 		len = 1;
 	} else {
 		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
-		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
-		len = intel_dp->lane_count + 1;
+		memcpy(buf + 1, intel_dp->train_set, crtc->config->lane_count);
+		len = crtc->config->lane_count + 1;
 	}
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
@@ -3518,8 +3525,10 @@ intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
 			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = intel_dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv =
+		to_i915(intel_dig_port->base.base.dev);
+	struct intel_crtc *crtc =
+		to_intel_crtc(intel_dig_port->base.base.crtc);
 	int ret;
 
 	intel_get_adjust_train(intel_dp, link_status);
@@ -3529,9 +3538,9 @@ intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
 	POSTING_READ(intel_dp->output_reg);
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
-				intel_dp->train_set, intel_dp->lane_count);
+				intel_dp->train_set, crtc->config->lane_count);
 
-	return ret == intel_dp->lane_count;
+	return ret == crtc->config->lane_count;
 }
 
 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
@@ -3570,6 +3579,8 @@ void
 intel_dp_start_link_train(struct intel_dp *intel_dp)
 {
 	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	struct drm_device *dev = encoder->dev;
 	int i;
 	uint8_t voltage;
@@ -3582,7 +3593,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 
 	/* Write the link configuration data */
 	link_config[0] = intel_dp->link_bw;
-	link_config[1] = intel_dp->lane_count;
+	link_config[1] = crtc->config->lane_count;
 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
@@ -3616,7 +3627,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 			break;
 		}
 
-		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+		if (drm_dp_clock_recovery_ok(link_status, crtc->config->lane_count)) {
 			DRM_DEBUG_KMS("clock recovery OK\n");
 			break;
 		}
@@ -3639,10 +3650,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 		}
 
 		/* Check to see if we've tried the max voltage */
-		for (i = 0; i < intel_dp->lane_count; i++)
+		for (i = 0; i < crtc->config->lane_count; i++)
 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 				break;
-		if (i == intel_dp->lane_count) {
+		if (i == crtc->config->lane_count) {
 			++loop_tries;
 			if (loop_tries == 5) {
 				DRM_ERROR("too many full retries, give up\n");
@@ -3679,6 +3690,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 void
 intel_dp_complete_link_train(struct intel_dp *intel_dp)
 {
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	bool channel_eq = false;
 	int tries, cr_tries;
 	uint32_t DP = intel_dp->DP;
@@ -3714,7 +3727,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 		}
 
 		/* Make sure clock is still ok */
-		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+		if (!drm_dp_clock_recovery_ok(link_status,
+					      crtc->config->lane_count)) {
 			intel_dp->train_set_valid = false;
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
@@ -3724,7 +3738,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			continue;
 		}
 
-		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
+		if (drm_dp_channel_eq_ok(link_status,
+					 crtc->config->lane_count)) {
 			channel_eq = true;
 			break;
 		}
@@ -4168,6 +4183,8 @@ update_status:
 static int
 intel_dp_check_mst_status(struct intel_dp *intel_dp)
 {
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	bool bret;
 
 	if (intel_dp->is_mst) {
@@ -4180,7 +4197,8 @@ go_again:
 		if (bret == true) {
 
 			/* check link status - esi[10] = 0x200c */
-			if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
+			if (intel_dp->active_mst_links &&
+			    !drm_dp_channel_eq_ok(&esi[10], crtc->config->lane_count)) {
 				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
 				intel_dp_start_link_train(intel_dp);
 				intel_dp_complete_link_train(intel_dp);
@@ -4235,6 +4253,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	u8 sink_irq_vector;
 	u8 link_status[DP_LINK_STATUS_SIZE];
 
@@ -4273,7 +4293,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
 			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
 	}
 
-	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
+	if (!drm_dp_channel_eq_ok(link_status, crtc->config->lane_count)) {
 		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
 			      intel_encoder->base.name);
 		intel_dp_start_link_train(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 6e4cc53..eeda730 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -65,7 +65,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 		intel_dp->rate_select = 0;
 	}
 
-	intel_dp->lane_count = lane_count;
+	pipe_config->lane_count = lane_count;
 
 	pipe_config->pipe_bpp = 24;
 	pipe_config->port_clock = rate;
@@ -276,6 +276,10 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
 		break;
 	}
 	pipe_config->base.adjusted_mode.flags |= flags;
+
+	pipe_config->lane_count =
+		((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+
 	intel_dp_get_m_n(crtc, pipe_config);
 
 	intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 983a7a7..703b394 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -430,6 +430,8 @@ struct intel_crtc_state {
 	/* Used by SDVO (and if we ever fix it, HDMI). */
 	unsigned pixel_multiplier;
 
+	uint8_t lane_count;
+
 	/* Panel fitter controls for gen2-gen4 + VLV */
 	struct {
 		u32 control;
@@ -718,7 +720,6 @@ struct intel_dp {
 	bool color_range_auto;
 	uint8_t link_bw;
 	uint8_t rate_select;
-	uint8_t lane_count;
 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
-- 
2.3.6

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 5/7] drm/i915: Move intel_dp->lane_count into pipe_config

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we clobber intel_dp->lane_count in compute config, which means
after a rejected modeset we may no longer be able to retrain the current
link. Move lane_count into pipe_config to avoid that.

v2: Add missing ':' to the pipe config debug dump

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  3 ++
 drivers/gpu/drm/i915/intel_ddi.c     | 10 +++---
 drivers/gpu/drm/i915/intel_display.c |  7 +++--
 drivers/gpu/drm/i915/intel_dp.c      | 60 ++++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_dp_mst.c  |  6 +++-
 drivers/gpu/drm/i915/intel_drv.h     |  3 +-
 6 files changed, 61 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d5c794a..f5dc75c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4096,6 +4096,7 @@ enum skl_disp_power_wells {
 /* How many wires to use. I guess 3 was too hard */
 #define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
 #define   DP_PORT_WIDTH_MASK		(7 << 19)
+#define   DP_PORT_WIDTH_SHIFT		19
 
 /* Mystic DPCD version 1.1 special mode */
 #define   DP_ENHANCED_FRAMING		(1 << 18)
@@ -7128,6 +7129,8 @@ enum skl_disp_power_wells {
 #define  DDI_BUF_IS_IDLE			(1<<7)
 #define  DDI_A_4_LANES				(1<<4)
 #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
+#define  DDI_PORT_WIDTH_MASK			(7 << 1)
+#define  DDI_PORT_WIDTH_SHIFT			1
 #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
 
 /* DDI Buffer Translations */
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 96fb472..8df596d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -723,11 +723,11 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_digital_port *intel_dig_port =
 		enc_to_dig_port(&encoder->base);
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 
 	intel_dp->DP = intel_dig_port->saved_port_bits |
 		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
-	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
-
+	intel_dp->DP |= DDI_PORT_WIDTH(crtc->config->lane_count);
 }
 
 static struct intel_encoder *
@@ -1913,7 +1913,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 		} else
 			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 
-		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
+		temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
 	} else if (type == INTEL_OUTPUT_DP_MST) {
 		struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
 
@@ -1922,7 +1922,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 		} else
 			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 
-		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
+		temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
 	} else {
 		WARN(1, "Invalid encoder type %d for pipe %c\n",
 		     intel_encoder->type, pipe_name(pipe));
@@ -3072,6 +3072,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	case TRANS_DDI_MODE_SELECT_DP_SST:
 	case TRANS_DDI_MODE_SELECT_DP_MST:
 		pipe_config->has_dp_encoder = true;
+		pipe_config->lane_count =
+			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
 		intel_dp_get_m_n(intel_crtc, pipe_config);
 		break;
 	default:
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 136b533..d56973f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11981,14 +11981,16 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
 		      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
 		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
 		      pipe_config->fdi_m_n.tu);
-	DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
 		      pipe_config->has_dp_encoder,
+		      pipe_config->lane_count,
 		      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
 		      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
 		      pipe_config->dp_m_n.tu);
 
-	DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
+	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
 		      pipe_config->has_dp_encoder,
+		      pipe_config->lane_count,
 		      pipe_config->dp_m2_n2.gmch_m,
 		      pipe_config->dp_m2_n2.gmch_n,
 		      pipe_config->dp_m2_n2.link_m,
@@ -12456,6 +12458,7 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_I(fdi_m_n.tu);
 
 	PIPE_CONF_CHECK_I(has_dp_encoder);
+	PIPE_CONF_CHECK_I(lane_count);
 
 	if (INTEL_INFO(dev)->gen < 8) {
 		PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b6ba02e..da036e8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1462,7 +1462,7 @@ found:
 			intel_dp->limited_color_range;
 	}
 
-	intel_dp->lane_count = lane_count;
+	pipe_config->lane_count = lane_count;
 
 	if (intel_dp->num_sink_rates) {
 		intel_dp->link_bw = 0;
@@ -1478,7 +1478,7 @@ found:
 	pipe_config->port_clock = common_rates[clock];
 
 	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
-		      intel_dp->link_bw, intel_dp->lane_count,
+		      intel_dp->link_bw, pipe_config->lane_count,
 		      pipe_config->port_clock, bpp);
 	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 		      mode_rate, link_avail);
@@ -1573,7 +1573,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 
 	/* Handle DP bits in common between all three register formats */
 	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
-	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
+	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
 
 	if (crtc->config->has_audio)
 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
@@ -2276,6 +2276,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 
 	pipe_config->has_dp_encoder = true;
 
+	pipe_config->lane_count =
+		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
+
 	intel_dp_get_m_n(crtc, pipe_config);
 
 	if (port == PORT_A) {
@@ -3301,13 +3304,15 @@ static void
 intel_get_adjust_train(struct intel_dp *intel_dp,
 		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	uint8_t v = 0;
 	uint8_t p = 0;
 	int lane;
 	uint8_t voltage_max;
 	uint8_t preemph_max;
 
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+	for (lane = 0; lane < crtc->config->lane_count; lane++) {
 		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 
@@ -3476,8 +3481,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 			uint8_t dp_train_pat)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = intel_dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv =
+		to_i915(intel_dig_port->base.base.dev);
+	struct intel_crtc *crtc =
+		to_intel_crtc(intel_dig_port->base.base.crtc);
 	uint8_t buf[sizeof(intel_dp->train_set) + 1];
 	int ret, len;
 
@@ -3493,8 +3500,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 		len = 1;
 	} else {
 		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
-		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
-		len = intel_dp->lane_count + 1;
+		memcpy(buf + 1, intel_dp->train_set, crtc->config->lane_count);
+		len = crtc->config->lane_count + 1;
 	}
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
@@ -3518,8 +3525,10 @@ intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
 			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = intel_dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_private *dev_priv =
+		to_i915(intel_dig_port->base.base.dev);
+	struct intel_crtc *crtc =
+		to_intel_crtc(intel_dig_port->base.base.crtc);
 	int ret;
 
 	intel_get_adjust_train(intel_dp, link_status);
@@ -3529,9 +3538,9 @@ intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
 	POSTING_READ(intel_dp->output_reg);
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
-				intel_dp->train_set, intel_dp->lane_count);
+				intel_dp->train_set, crtc->config->lane_count);
 
-	return ret == intel_dp->lane_count;
+	return ret == crtc->config->lane_count;
 }
 
 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
@@ -3570,6 +3579,8 @@ void
 intel_dp_start_link_train(struct intel_dp *intel_dp)
 {
 	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	struct drm_device *dev = encoder->dev;
 	int i;
 	uint8_t voltage;
@@ -3582,7 +3593,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 
 	/* Write the link configuration data */
 	link_config[0] = intel_dp->link_bw;
-	link_config[1] = intel_dp->lane_count;
+	link_config[1] = crtc->config->lane_count;
 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
@@ -3616,7 +3627,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 			break;
 		}
 
-		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+		if (drm_dp_clock_recovery_ok(link_status, crtc->config->lane_count)) {
 			DRM_DEBUG_KMS("clock recovery OK\n");
 			break;
 		}
@@ -3639,10 +3650,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 		}
 
 		/* Check to see if we've tried the max voltage */
-		for (i = 0; i < intel_dp->lane_count; i++)
+		for (i = 0; i < crtc->config->lane_count; i++)
 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 				break;
-		if (i == intel_dp->lane_count) {
+		if (i == crtc->config->lane_count) {
 			++loop_tries;
 			if (loop_tries == 5) {
 				DRM_ERROR("too many full retries, give up\n");
@@ -3679,6 +3690,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 void
 intel_dp_complete_link_train(struct intel_dp *intel_dp)
 {
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	bool channel_eq = false;
 	int tries, cr_tries;
 	uint32_t DP = intel_dp->DP;
@@ -3714,7 +3727,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 		}
 
 		/* Make sure clock is still ok */
-		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+		if (!drm_dp_clock_recovery_ok(link_status,
+					      crtc->config->lane_count)) {
 			intel_dp->train_set_valid = false;
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
@@ -3724,7 +3738,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			continue;
 		}
 
-		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
+		if (drm_dp_channel_eq_ok(link_status,
+					 crtc->config->lane_count)) {
 			channel_eq = true;
 			break;
 		}
@@ -4168,6 +4183,8 @@ update_status:
 static int
 intel_dp_check_mst_status(struct intel_dp *intel_dp)
 {
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	bool bret;
 
 	if (intel_dp->is_mst) {
@@ -4180,7 +4197,8 @@ go_again:
 		if (bret == true) {
 
 			/* check link status - esi[10] = 0x200c */
-			if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
+			if (intel_dp->active_mst_links &&
+			    !drm_dp_channel_eq_ok(&esi[10], crtc->config->lane_count)) {
 				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
 				intel_dp_start_link_train(intel_dp);
 				intel_dp_complete_link_train(intel_dp);
@@ -4235,6 +4253,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
+	struct intel_crtc *crtc =
+		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
 	u8 sink_irq_vector;
 	u8 link_status[DP_LINK_STATUS_SIZE];
 
@@ -4273,7 +4293,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
 			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
 	}
 
-	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
+	if (!drm_dp_channel_eq_ok(link_status, crtc->config->lane_count)) {
 		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
 			      intel_encoder->base.name);
 		intel_dp_start_link_train(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 6e4cc53..eeda730 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -65,7 +65,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 		intel_dp->rate_select = 0;
 	}
 
-	intel_dp->lane_count = lane_count;
+	pipe_config->lane_count = lane_count;
 
 	pipe_config->pipe_bpp = 24;
 	pipe_config->port_clock = rate;
@@ -276,6 +276,10 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
 		break;
 	}
 	pipe_config->base.adjusted_mode.flags |= flags;
+
+	pipe_config->lane_count =
+		((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+
 	intel_dp_get_m_n(crtc, pipe_config);
 
 	intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 983a7a7..703b394 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -430,6 +430,8 @@ struct intel_crtc_state {
 	/* Used by SDVO (and if we ever fix it, HDMI). */
 	unsigned pixel_multiplier;
 
+	uint8_t lane_count;
+
 	/* Panel fitter controls for gen2-gen4 + VLV */
 	struct {
 		u32 control;
@@ -718,7 +720,6 @@ struct intel_dp {
 	bool color_range_auto;
 	uint8_t link_bw;
 	uint8_t rate_select;
-	uint8_t lane_count;
 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
-- 
2.3.6

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 5/7] drm/i915: Move intel_dp->lane_count into pipe_config

[Sivakumar Thulasimani]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On Monday 06 July 2015 07:09 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we clobber intel_dp->lane_count in compute config, which means
> after a rejected modeset we may no longer be able to retrain the current
> link. Move lane_count into pipe_config to avoid that.
>
> v2: Add missing ':' to the pipe config debug dump
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      |  3 ++
>   drivers/gpu/drm/i915/intel_ddi.c     | 10 +++---
>   drivers/gpu/drm/i915/intel_display.c |  7 +++--
>   drivers/gpu/drm/i915/intel_dp.c      | 60 ++++++++++++++++++++++++------------
>   drivers/gpu/drm/i915/intel_dp_mst.c  |  6 +++-
>   drivers/gpu/drm/i915/intel_drv.h     |  3 +-
>   6 files changed, 61 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d5c794a..f5dc75c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4096,6 +4096,7 @@ enum skl_disp_power_wells {
>   /* How many wires to use. I guess 3 was too hard */
>   #define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
>   #define   DP_PORT_WIDTH_MASK		(7 << 19)
> +#define   DP_PORT_WIDTH_SHIFT		19
>   
>   /* Mystic DPCD version 1.1 special mode */
>   #define   DP_ENHANCED_FRAMING		(1 << 18)
> @@ -7128,6 +7129,8 @@ enum skl_disp_power_wells {
>   #define  DDI_BUF_IS_IDLE			(1<<7)
>   #define  DDI_A_4_LANES				(1<<4)
>   #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
> +#define  DDI_PORT_WIDTH_MASK			(7 << 1)
> +#define  DDI_PORT_WIDTH_SHIFT			1
>   #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
>   
>   /* DDI Buffer Translations */
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 96fb472..8df596d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -723,11 +723,11 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
>   	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>   	struct intel_digital_port *intel_dig_port =
>   		enc_to_dig_port(&encoder->base);
> +	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
>   
>   	intel_dp->DP = intel_dig_port->saved_port_bits |
>   		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
> -	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
> -
> +	intel_dp->DP |= DDI_PORT_WIDTH(crtc->config->lane_count);
>   }
>   
>   static struct intel_encoder *
> @@ -1913,7 +1913,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
>   		} else
>   			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
>   
> -		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
> +		temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
>   	} else if (type == INTEL_OUTPUT_DP_MST) {
>   		struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
>   
> @@ -1922,7 +1922,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
>   		} else
>   			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
>   
> -		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
> +		temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
>   	} else {
>   		WARN(1, "Invalid encoder type %d for pipe %c\n",
>   		     intel_encoder->type, pipe_name(pipe));
> @@ -3072,6 +3072,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>   	case TRANS_DDI_MODE_SELECT_DP_SST:
>   	case TRANS_DDI_MODE_SELECT_DP_MST:
>   		pipe_config->has_dp_encoder = true;
> +		pipe_config->lane_count =
> +			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
>   		intel_dp_get_m_n(intel_crtc, pipe_config);
>   		break;
>   	default:
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 136b533..d56973f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11981,14 +11981,16 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
>   		      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
>   		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
>   		      pipe_config->fdi_m_n.tu);
> -	DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
> +	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
>   		      pipe_config->has_dp_encoder,
> +		      pipe_config->lane_count,
>   		      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
>   		      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
>   		      pipe_config->dp_m_n.tu);
>   
> -	DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
> +	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
>   		      pipe_config->has_dp_encoder,
> +		      pipe_config->lane_count,
>   		      pipe_config->dp_m2_n2.gmch_m,
>   		      pipe_config->dp_m2_n2.gmch_n,
>   		      pipe_config->dp_m2_n2.link_m,
> @@ -12456,6 +12458,7 @@ intel_pipe_config_compare(struct drm_device *dev,
>   	PIPE_CONF_CHECK_I(fdi_m_n.tu);
>   
>   	PIPE_CONF_CHECK_I(has_dp_encoder);
> +	PIPE_CONF_CHECK_I(lane_count);
>   
>   	if (INTEL_INFO(dev)->gen < 8) {
>   		PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b6ba02e..da036e8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1462,7 +1462,7 @@ found:
>   			intel_dp->limited_color_range;
>   	}
>   
> -	intel_dp->lane_count = lane_count;
> +	pipe_config->lane_count = lane_count;
>   
>   	if (intel_dp->num_sink_rates) {
>   		intel_dp->link_bw = 0;
> @@ -1478,7 +1478,7 @@ found:
>   	pipe_config->port_clock = common_rates[clock];
>   
>   	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
> -		      intel_dp->link_bw, intel_dp->lane_count,
> +		      intel_dp->link_bw, pipe_config->lane_count,
>   		      pipe_config->port_clock, bpp);
>   	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
>   		      mode_rate, link_avail);
> @@ -1573,7 +1573,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>   
>   	/* Handle DP bits in common between all three register formats */
>   	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
> -	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
> +	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
>   
>   	if (crtc->config->has_audio)
>   		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
> @@ -2276,6 +2276,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>   
>   	pipe_config->has_dp_encoder = true;
>   
> +	pipe_config->lane_count =
> +		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
> +
>   	intel_dp_get_m_n(crtc, pipe_config);
>   
>   	if (port == PORT_A) {
> @@ -3301,13 +3304,15 @@ static void
>   intel_get_adjust_train(struct intel_dp *intel_dp,
>   		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
>   {
> +	struct intel_crtc *crtc =
> +		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
>   	uint8_t v = 0;
>   	uint8_t p = 0;
>   	int lane;
>   	uint8_t voltage_max;
>   	uint8_t preemph_max;
>   
> -	for (lane = 0; lane < intel_dp->lane_count; lane++) {
> +	for (lane = 0; lane < crtc->config->lane_count; lane++) {
>   		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
>   		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
>   
> @@ -3476,8 +3481,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>   			uint8_t dp_train_pat)
>   {
>   	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_device *dev = intel_dig_port->base.base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_i915_private *dev_priv =
> +		to_i915(intel_dig_port->base.base.dev);
> +	struct intel_crtc *crtc =
> +		to_intel_crtc(intel_dig_port->base.base.crtc);
>   	uint8_t buf[sizeof(intel_dp->train_set) + 1];
>   	int ret, len;
>   
> @@ -3493,8 +3500,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>   		len = 1;
>   	} else {
>   		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
> -		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
> -		len = intel_dp->lane_count + 1;
> +		memcpy(buf + 1, intel_dp->train_set, crtc->config->lane_count);
> +		len = crtc->config->lane_count + 1;
>   	}
>   
>   	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
> @@ -3518,8 +3525,10 @@ intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
>   			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
>   {
>   	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_device *dev = intel_dig_port->base.base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_i915_private *dev_priv =
> +		to_i915(intel_dig_port->base.base.dev);
> +	struct intel_crtc *crtc =
> +		to_intel_crtc(intel_dig_port->base.base.crtc);
>   	int ret;
>   
>   	intel_get_adjust_train(intel_dp, link_status);
> @@ -3529,9 +3538,9 @@ intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
>   	POSTING_READ(intel_dp->output_reg);
>   
>   	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
> -				intel_dp->train_set, intel_dp->lane_count);
> +				intel_dp->train_set, crtc->config->lane_count);
>   
> -	return ret == intel_dp->lane_count;
> +	return ret == crtc->config->lane_count;
>   }
>   
>   static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
> @@ -3570,6 +3579,8 @@ void
>   intel_dp_start_link_train(struct intel_dp *intel_dp)
>   {
>   	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> +	struct intel_crtc *crtc =
> +		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
>   	struct drm_device *dev = encoder->dev;
>   	int i;
>   	uint8_t voltage;
> @@ -3582,7 +3593,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>   
>   	/* Write the link configuration data */
>   	link_config[0] = intel_dp->link_bw;
> -	link_config[1] = intel_dp->lane_count;
> +	link_config[1] = crtc->config->lane_count;
>   	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>   		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>   	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> @@ -3616,7 +3627,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>   			break;
>   		}
>   
> -		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
> +		if (drm_dp_clock_recovery_ok(link_status, crtc->config->lane_count)) {
>   			DRM_DEBUG_KMS("clock recovery OK\n");
>   			break;
>   		}
> @@ -3639,10 +3650,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>   		}
>   
>   		/* Check to see if we've tried the max voltage */
> -		for (i = 0; i < intel_dp->lane_count; i++)
> +		for (i = 0; i < crtc->config->lane_count; i++)
>   			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
>   				break;
> -		if (i == intel_dp->lane_count) {
> +		if (i == crtc->config->lane_count) {
>   			++loop_tries;
>   			if (loop_tries == 5) {
>   				DRM_ERROR("too many full retries, give up\n");
> @@ -3679,6 +3690,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>   void
>   intel_dp_complete_link_train(struct intel_dp *intel_dp)
>   {
> +	struct intel_crtc *crtc =
> +		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
>   	bool channel_eq = false;
>   	int tries, cr_tries;
>   	uint32_t DP = intel_dp->DP;
> @@ -3714,7 +3727,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>   		}
>   
>   		/* Make sure clock is still ok */
> -		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
> +		if (!drm_dp_clock_recovery_ok(link_status,
> +					      crtc->config->lane_count)) {
>   			intel_dp->train_set_valid = false;
>   			intel_dp_start_link_train(intel_dp);
>   			intel_dp_set_link_train(intel_dp, &DP,
> @@ -3724,7 +3738,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>   			continue;
>   		}
>   
> -		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
> +		if (drm_dp_channel_eq_ok(link_status,
> +					 crtc->config->lane_count)) {
>   			channel_eq = true;
>   			break;
>   		}
> @@ -4168,6 +4183,8 @@ update_status:
>   static int
>   intel_dp_check_mst_status(struct intel_dp *intel_dp)
>   {
> +	struct intel_crtc *crtc =
> +		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
>   	bool bret;
>   
>   	if (intel_dp->is_mst) {
> @@ -4180,7 +4197,8 @@ go_again:
>   		if (bret == true) {
>   
>   			/* check link status - esi[10] = 0x200c */
> -			if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
> +			if (intel_dp->active_mst_links &&
> +			    !drm_dp_channel_eq_ok(&esi[10], crtc->config->lane_count)) {
>   				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
>   				intel_dp_start_link_train(intel_dp);
>   				intel_dp_complete_link_train(intel_dp);
> @@ -4235,6 +4253,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
>   {
>   	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>   	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
> +	struct intel_crtc *crtc =
> +		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
>   	u8 sink_irq_vector;
>   	u8 link_status[DP_LINK_STATUS_SIZE];
>   
> @@ -4273,7 +4293,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
>   			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
>   	}
>   
> -	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
> +	if (!drm_dp_channel_eq_ok(link_status, crtc->config->lane_count)) {
>   		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
>   			      intel_encoder->base.name);
>   		intel_dp_start_link_train(intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 6e4cc53..eeda730 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -65,7 +65,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>   		intel_dp->rate_select = 0;
>   	}
>   
> -	intel_dp->lane_count = lane_count;
> +	pipe_config->lane_count = lane_count;
>   
>   	pipe_config->pipe_bpp = 24;
>   	pipe_config->port_clock = rate;
> @@ -276,6 +276,10 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
>   		break;
>   	}
>   	pipe_config->base.adjusted_mode.flags |= flags;
> +
> +	pipe_config->lane_count =
> +		((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
> +
>   	intel_dp_get_m_n(crtc, pipe_config);
>   
>   	intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 983a7a7..703b394 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -430,6 +430,8 @@ struct intel_crtc_state {
>   	/* Used by SDVO (and if we ever fix it, HDMI). */
>   	unsigned pixel_multiplier;
>   
> +	uint8_t lane_count;
> +
>   	/* Panel fitter controls for gen2-gen4 + VLV */
>   	struct {
>   		u32 control;
> @@ -718,7 +720,6 @@ struct intel_dp {
>   	bool color_range_auto;
>   	uint8_t link_bw;
>   	uint8_t rate_select;
> -	uint8_t lane_count;
>   	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
>   	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>   	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

-- 
regards,
Sivakumar Thulasimani

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[PATCH 6/7] drm/i915: Don't use link_bw to select between TP1 and TP3

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_dp->link_bw is going away, so consul the port_clock instead when
choosing between TP1 and TP3.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da036e8..46b734b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3697,8 +3697,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 	uint32_t DP = intel_dp->DP;
 	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
 
-	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
-	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
+	/* Training Pattern 3 for HBR2 or 1.2 devices that support it*/
+	if (crtc->config->port_clock == 540000 || intel_dp->use_tps3)
 		training_pattern = DP_TRAINING_PATTERN_3;
 
 	/* channel equalization */
-- 
2.3.6

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Re: [PATCH 6/7] drm/i915: Don't use link_bw to select between TP1 and TP3

[Sivakumar Thulasimani]

[-- Attachment #1.1: Type: text/plain, Size: 1246 bytes --]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>



On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_dp->link_bw is going away, so consul the port_clock instead when
> choosing between TP1 and TP3.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index da036e8..46b734b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3697,8 +3697,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>   	uint32_t DP = intel_dp->DP;
>   	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>   
> -	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> -	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> +	/* Training Pattern 3 for HBR2 or 1.2 devices that support it*/
> +	if (crtc->config->port_clock == 540000 || intel_dp->use_tps3)
>   		training_pattern = DP_TRAINING_PATTERN_3;
>   
>   	/* channel equalization */

-- 
regards,
Sivakumar


[-- Attachment #1.2: Type: text/html, Size: 2263 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

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[PATCH 7/7] drm/i915: Kill intel_dp->{link_bw, rate_select}

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We only need the link_bw/rate_select parameters when starting link
training, and they should be computed based on the currently active
config, so throw them out from intel_dp and just compute on demand.

Toss in an extra debug print to see rate_select in addition to link_bw,
as the latter may be 0 for eDP 1.4.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c     | 39 ++++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_dp_mst.c | 13 ++-----------
 drivers/gpu/drm/i915/intel_drv.h    |  2 --
 3 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 46b734b..e88cec2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1342,6 +1342,19 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 	return rate_to_index(rate, intel_dp->sink_rates);
 }
 
+static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
+				  uint8_t *link_bw, uint8_t *rate_select)
+{
+	if (intel_dp->num_sink_rates) {
+		*link_bw = 0;
+		*rate_select =
+			intel_dp_rate_select(intel_dp, port_clock);
+	} else {
+		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
+		*rate_select = 0;
+	}
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config)
@@ -1363,6 +1376,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	int link_avail, link_clock;
 	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
 	int common_len;
+	uint8_t link_bw, rate_select;
 
 	common_len = intel_dp_common_rates(intel_dp, common_rates);
 
@@ -1464,21 +1478,14 @@ found:
 
 	pipe_config->lane_count = lane_count;
 
-	if (intel_dp->num_sink_rates) {
-		intel_dp->link_bw = 0;
-		intel_dp->rate_select =
-			intel_dp_rate_select(intel_dp, common_rates[clock]);
-	} else {
-		intel_dp->link_bw =
-			drm_dp_link_rate_to_bw_code(common_rates[clock]);
-		intel_dp->rate_select = 0;
-	}
-
 	pipe_config->pipe_bpp = bpp;
 	pipe_config->port_clock = common_rates[clock];
 
-	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
-		      intel_dp->link_bw, pipe_config->lane_count,
+	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
+			      &link_bw, &rate_select);
+
+	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
+		      link_bw, rate_select, pipe_config->lane_count,
 		      pipe_config->port_clock, bpp);
 	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 		      mode_rate, link_avail);
@@ -3587,19 +3594,23 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
 	int voltage_tries, loop_tries;
 	uint32_t DP = intel_dp->DP;
 	uint8_t link_config[2];
+	uint8_t link_bw, rate_select;
 
 	if (HAS_DDI(dev))
 		intel_ddi_prepare_link_retrain(encoder);
 
+	intel_dp_compute_rate(intel_dp, crtc->config->port_clock,
+			      &link_bw, &rate_select);
+
 	/* Write the link configuration data */
-	link_config[0] = intel_dp->link_bw;
+	link_config[0] = link_bw;
 	link_config[1] = crtc->config->lane_count;
 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 	if (intel_dp->num_sink_rates)
 		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
-				&intel_dp->rate_select, 1);
+				  &rate_select, 1);
 
 	link_config[0] = 0;
 	link_config[1] = DP_SET_ANSI_8B10B;
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index eeda730..3dc08da 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -38,7 +38,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = &intel_dig_port->dp;
 	struct drm_atomic_state *state;
 	int bpp, i;
-	int lane_count, slots, rate;
+	int lane_count, slots;
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	struct drm_connector *drm_connector;
 	struct intel_connector *connector, *found = NULL;
@@ -55,20 +55,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	 */
 	lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 
-	rate = intel_dp_max_link_rate(intel_dp);
-
-	if (intel_dp->num_sink_rates) {
-		intel_dp->link_bw = 0;
-		intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
-	} else {
-		intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate);
-		intel_dp->rate_select = 0;
-	}
 
 	pipe_config->lane_count = lane_count;
 
 	pipe_config->pipe_bpp = 24;
-	pipe_config->port_clock = rate;
+	pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
 
 	state = pipe_config->base.state;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 703b394..709de50 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -718,8 +718,6 @@ struct intel_dp {
 	enum hdmi_force_audio force_audio;
 	bool limited_color_range;
 	bool color_range_auto;
-	uint8_t link_bw;
-	uint8_t rate_select;
 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
-- 
2.3.6

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Re: [PATCH 7/7] drm/i915: Kill intel_dp->{link_bw, rate_select}

[Sivakumar Thulasimani]

[-- Attachment #1.1: Type: text/plain, Size: 5936 bytes --]


Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>


On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We only need the link_bw/rate_select parameters when starting link
> training, and they should be computed based on the currently active
> config, so throw them out from intel_dp and just compute on demand.
>
> Toss in an extra debug print to see rate_select in addition to link_bw,
> as the latter may be 0 for eDP 1.4.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c     | 39 ++++++++++++++++++++++++-------------
>   drivers/gpu/drm/i915/intel_dp_mst.c | 13 ++-----------
>   drivers/gpu/drm/i915/intel_drv.h    |  2 --
>   3 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 46b734b..e88cec2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1342,6 +1342,19 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
>   	return rate_to_index(rate, intel_dp->sink_rates);
>   }
>   
> +static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> +				  uint8_t *link_bw, uint8_t *rate_select)
> +{
> +	if (intel_dp->num_sink_rates) {
> +		*link_bw = 0;
> +		*rate_select =
> +			intel_dp_rate_select(intel_dp, port_clock);
> +	} else {
> +		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
> +		*rate_select = 0;
> +	}
> +}
> +
>   bool
>   intel_dp_compute_config(struct intel_encoder *encoder,
>   			struct intel_crtc_state *pipe_config)
> @@ -1363,6 +1376,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   	int link_avail, link_clock;
>   	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
>   	int common_len;
> +	uint8_t link_bw, rate_select;
>   
>   	common_len = intel_dp_common_rates(intel_dp, common_rates);
>   
> @@ -1464,21 +1478,14 @@ found:
>   
>   	pipe_config->lane_count = lane_count;
>   
> -	if (intel_dp->num_sink_rates) {
> -		intel_dp->link_bw = 0;
> -		intel_dp->rate_select =
> -			intel_dp_rate_select(intel_dp, common_rates[clock]);
> -	} else {
> -		intel_dp->link_bw =
> -			drm_dp_link_rate_to_bw_code(common_rates[clock]);
> -		intel_dp->rate_select = 0;
> -	}
> -
>   	pipe_config->pipe_bpp = bpp;
>   	pipe_config->port_clock = common_rates[clock];
>   
> -	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
> -		      intel_dp->link_bw, pipe_config->lane_count,
> +	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
> +			      &link_bw, &rate_select);
> +
> +	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
> +		      link_bw, rate_select, pipe_config->lane_count,
>   		      pipe_config->port_clock, bpp);
>   	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
>   		      mode_rate, link_avail);
> @@ -3587,19 +3594,23 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>   	int voltage_tries, loop_tries;
>   	uint32_t DP = intel_dp->DP;
>   	uint8_t link_config[2];
> +	uint8_t link_bw, rate_select;
>   
>   	if (HAS_DDI(dev))
>   		intel_ddi_prepare_link_retrain(encoder);
>   
> +	intel_dp_compute_rate(intel_dp, crtc->config->port_clock,
> +			      &link_bw, &rate_select);
> +
>   	/* Write the link configuration data */
> -	link_config[0] = intel_dp->link_bw;
> +	link_config[0] = link_bw;
>   	link_config[1] = crtc->config->lane_count;
>   	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>   		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>   	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
>   	if (intel_dp->num_sink_rates)
>   		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> -				&intel_dp->rate_select, 1);
> +				  &rate_select, 1);
>   
>   	link_config[0] = 0;
>   	link_config[1] = DP_SET_ANSI_8B10B;
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index eeda730..3dc08da 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -38,7 +38,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>   	struct intel_dp *intel_dp = &intel_dig_port->dp;
>   	struct drm_atomic_state *state;
>   	int bpp, i;
> -	int lane_count, slots, rate;
> +	int lane_count, slots;
>   	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
>   	struct drm_connector *drm_connector;
>   	struct intel_connector *connector, *found = NULL;
> @@ -55,20 +55,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>   	 */
>   	lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
>   
> -	rate = intel_dp_max_link_rate(intel_dp);
> -
> -	if (intel_dp->num_sink_rates) {
> -		intel_dp->link_bw = 0;
> -		intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
> -	} else {
> -		intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate);
> -		intel_dp->rate_select = 0;
> -	}
>   
>   	pipe_config->lane_count = lane_count;
>   
>   	pipe_config->pipe_bpp = 24;
> -	pipe_config->port_clock = rate;
> +	pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
>   
>   	state = pipe_config->base.state;
>   
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 703b394..709de50 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -718,8 +718,6 @@ struct intel_dp {
>   	enum hdmi_force_audio force_audio;
>   	bool limited_color_range;
>   	bool color_range_auto;
> -	uint8_t link_bw;
> -	uint8_t rate_select;
>   	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
>   	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>   	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

-- 
regards,
Sivakumar


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Re: [PATCH 7/7] drm/i915: Kill intel_dp->{link_bw, rate_select}

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6727
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  303/303              303/303
SNB              +3                 309/316              312/316
IVB                                  343/343              343/343
BYT                 -1              285/285              284/285
HSW              +13                 367/381              380/381
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*SNB  igt@kms_mmio_vs_cs_flip@setcrtc_vs_cs_flip      DMESG_WARN(1)      PASS(1)
*SNB  igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip      DMESG_WARN(1)      PASS(1)
*SNB  igt@pm_rpm@cursor      DMESG_WARN(1)      PASS(1)
*SNB  igt@pm_rpm@cursor-dpms      DMESG_FAIL(1)      FAIL(1)
*BYT  igt@gem_partial_pwrite_pread@reads-uncached      PASS(1)      FAIL(1)
*HSW  igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_lpsp@non-edp      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@debugfs-read      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@gem-idle      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@gem-mmap-gtt      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@gem-pread      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@i2c      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@modeset-non-lpsp      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@modeset-non-lpsp-stress-no-wait      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@pci-d3-state      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@reg-read-ioctl      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@rte      DMESG_WARN(1)      PASS(1)
*HSW  igt@pm_rpm@sysfs-read      DMESG_WARN(1)      PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp

[Ville Syrjälä]

On Mon, Jul 06, 2015 at 03:09:59PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> While working on CHV DPIO powergating I relized DP .compute_config() was
> clobbering lane_count etc. stored in intel_dp. This could cause problems
> if we do the .compute_config() but later fail the modeset for some reason.
> Any subsequent link re-training might then fail if intel_dp->lane_count
> etc. got changed.
> 
> The reason I ran into this during the DPIO powergating work was that I may
> need to know which lanes he active when shutting down the link. However
> .compute_config() already clobbered that information by the time I need it.
> By moving it to the pipe config we avoid that problem as well.
> 
> I also cleaned up the limited color range handling a bit while I was
> in the neighborhood.
> 

>   drm/i915: Clean up DP/HDMI limited color range handling
>   drm/i915: Move intel_dp->lane_count into pipe_config

These two are still lacking a r-b. Would be nice to get these in so that
they don't end up blocking the CHV DPIO powergating stuff once that gets
reviewed.

Sivakumar, any chance you'd like to review those as well? Or do we have
anyone else interested?

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp

[Daniel Vetter]

On Wed, Aug 12, 2015 at 07:04:22PM +0300, Ville Syrjälä wrote:
> On Mon, Jul 06, 2015 at 03:09:59PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > While working on CHV DPIO powergating I relized DP .compute_config() was
> > clobbering lane_count etc. stored in intel_dp. This could cause problems
> > if we do the .compute_config() but later fail the modeset for some reason.
> > Any subsequent link re-training might then fail if intel_dp->lane_count
> > etc. got changed.
> > 
> > The reason I ran into this during the DPIO powergating work was that I may
> > need to know which lanes he active when shutting down the link. However
> > .compute_config() already clobbered that information by the time I need it.
> > By moving it to the pipe config we avoid that problem as well.
> > 
> > I also cleaned up the limited color range handling a bit while I was
> > in the neighborhood.
> > 
> 
> >   drm/i915: Clean up DP/HDMI limited color range handling
> >   drm/i915: Move intel_dp->lane_count into pipe_config
> 
> These two are still lacking a r-b. Would be nice to get these in so that
> they don't end up blocking the CHV DPIO powergating stuff once that gets
> reviewed.
> 
> Sivakumar, any chance you'd like to review those as well? Or do we have
> anyone else interested?

All merged to dinq, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp

[Maarten Lankhorst]

Hey,

Op 06-07-15 om 14:09 schreef ville.syrjala@linux.intel.com:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> While working on CHV DPIO powergating I relized DP .compute_config() was
> clobbering lane_count etc. stored in intel_dp. This could cause problems
> if we do the .compute_config() but later fail the modeset for some reason.
> Any subsequent link re-training might then fail if intel_dp->lane_count
> etc. got changed.
>
> The reason I ran into this during the DPIO powergating work was that I may
> need to know which lanes he active when shutting down the link. However
> .compute_config() already clobbered that information by the time I need it.
> By moving it to the pipe config we avoid that problem as well.
>
> I also cleaned up the limited color range handling a bit while I was
> in the neighborhood.
>
> Ville Syrjälä (7):
>   drm/i915: Clean up DP/HDMI limited color range handling
>   drm/i915: Don't use link_bw for PLL setup
^
>   drm/i915: Don't pass clock to DDI PLL select functions
>   drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP
>     .get_config()
>   drm/i915: Move intel_dp->lane_count into pipe_config
^Your patch series breaks MST entirely.

drm_encoder->crtc will be NULL and dereferencing crtc->config will fail on the primary encoder:

intel_mst_pre_enable_dp(mst_enc) -> intel_ddi_init_dp_buf_reg(mst_enc->primary). -> primary->crtc = NULL, OOPS.

Voltage training was failing too and I was getting a MCE until I reverted the crtc->config changes from this series..


>   drm/i915: Don't use link_bw to select between TP1 and TP3
>   drm/i915: Kill intel_dp->{link_bw,rate_select}
>
>  drivers/gpu/drm/i915/i915_reg.h      |   3 +
>  drivers/gpu/drm/i915/intel_ddi.c     |  41 ++++----
>  drivers/gpu/drm/i915/intel_display.c |   7 +-
>  drivers/gpu/drm/i915/intel_dp.c      | 177 ++++++++++++++++++++---------------
>  drivers/gpu/drm/i915/intel_dp_mst.c  |  19 ++--
>  drivers/gpu/drm/i915/intel_drv.h     |   9 +-
>  drivers/gpu/drm/i915/intel_hdmi.c    |  26 +++--
>  7 files changed, 155 insertions(+), 127 deletions(-)
>

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Re: [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp

[Ville Syrjälä]

On Mon, Aug 17, 2015 at 10:42:23AM +0200, Maarten Lankhorst wrote:
> Hey,
> 
> Op 06-07-15 om 14:09 schreef ville.syrjala@linux.intel.com:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > While working on CHV DPIO powergating I relized DP .compute_config() was
> > clobbering lane_count etc. stored in intel_dp. This could cause problems
> > if we do the .compute_config() but later fail the modeset for some reason.
> > Any subsequent link re-training might then fail if intel_dp->lane_count
> > etc. got changed.
> >
> > The reason I ran into this during the DPIO powergating work was that I may
> > need to know which lanes he active when shutting down the link. However
> > .compute_config() already clobbered that information by the time I need it.
> > By moving it to the pipe config we avoid that problem as well.
> >
> > I also cleaned up the limited color range handling a bit while I was
> > in the neighborhood.
> >
> > Ville Syrjälä (7):
> >   drm/i915: Clean up DP/HDMI limited color range handling
> >   drm/i915: Don't use link_bw for PLL setup
> ^
> >   drm/i915: Don't pass clock to DDI PLL select functions
> >   drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP
> >     .get_config()
> >   drm/i915: Move intel_dp->lane_count into pipe_config
> ^Your patch series breaks MST entirely.
> 
> drm_encoder->crtc will be NULL and dereferencing crtc->config will fail on the primary encoder:
> 
> intel_mst_pre_enable_dp(mst_enc) -> intel_ddi_init_dp_buf_reg(mst_enc->primary). -> primary->crtc = NULL, OOPS.
> 
> Voltage training was failing too and I was getting a MCE until I reverted the crtc->config changes from this series..

Hmm. Our modeset code vs. mst seems to a huge mess. To fix it properly
we should split the link compute/setup from the pipe config entirely.
As a short term solution I suppose I could pass the pipe config into
various dp link setup functions rather than assume that we can dig it
out from the encoder->crtc.

> 
> 
> >   drm/i915: Don't use link_bw to select between TP1 and TP3
> >   drm/i915: Kill intel_dp->{link_bw,rate_select}
> >
> >  drivers/gpu/drm/i915/i915_reg.h      |   3 +
> >  drivers/gpu/drm/i915/intel_ddi.c     |  41 ++++----
> >  drivers/gpu/drm/i915/intel_display.c |   7 +-
> >  drivers/gpu/drm/i915/intel_dp.c      | 177 ++++++++++++++++++++---------------
> >  drivers/gpu/drm/i915/intel_dp_mst.c  |  19 ++--
> >  drivers/gpu/drm/i915/intel_drv.h     |   9 +-
> >  drivers/gpu/drm/i915/intel_hdmi.c    |  26 +++--
> >  7 files changed, 155 insertions(+), 127 deletions(-)
> >

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp

[Daniel Vetter]

On Mon, Aug 17, 2015 at 03:03:10PM +0300, Ville Syrjälä wrote:
> On Mon, Aug 17, 2015 at 10:42:23AM +0200, Maarten Lankhorst wrote:
> > Hey,
> > 
> > Op 06-07-15 om 14:09 schreef ville.syrjala@linux.intel.com:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > While working on CHV DPIO powergating I relized DP .compute_config() was
> > > clobbering lane_count etc. stored in intel_dp. This could cause problems
> > > if we do the .compute_config() but later fail the modeset for some reason.
> > > Any subsequent link re-training might then fail if intel_dp->lane_count
> > > etc. got changed.
> > >
> > > The reason I ran into this during the DPIO powergating work was that I may
> > > need to know which lanes he active when shutting down the link. However
> > > .compute_config() already clobbered that information by the time I need it.
> > > By moving it to the pipe config we avoid that problem as well.
> > >
> > > I also cleaned up the limited color range handling a bit while I was
> > > in the neighborhood.
> > >
> > > Ville Syrjälä (7):
> > >   drm/i915: Clean up DP/HDMI limited color range handling
> > >   drm/i915: Don't use link_bw for PLL setup
> > ^
> > >   drm/i915: Don't pass clock to DDI PLL select functions
> > >   drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP
> > >     .get_config()
> > >   drm/i915: Move intel_dp->lane_count into pipe_config
> > ^Your patch series breaks MST entirely.
> > 
> > drm_encoder->crtc will be NULL and dereferencing crtc->config will fail on the primary encoder:
> > 
> > intel_mst_pre_enable_dp(mst_enc) -> intel_ddi_init_dp_buf_reg(mst_enc->primary). -> primary->crtc = NULL, OOPS.
> > 
> > Voltage training was failing too and I was getting a MCE until I reverted the crtc->config changes from this series..
> 
> Hmm. Our modeset code vs. mst seems to a huge mess. To fix it properly
> we should split the link compute/setup from the pipe config entirely.
> As a short term solution I suppose I could pass the pipe config into
> various dp link setup functions rather than assume that we can dig it
> out from the encoder->crtc.

Luckily seris is in 4.4 only. Should I just drop it, or is it easily
salvageable?
-Daniel

> 
> > 
> > 
> > >   drm/i915: Don't use link_bw to select between TP1 and TP3
> > >   drm/i915: Kill intel_dp->{link_bw,rate_select}
> > >
> > >  drivers/gpu/drm/i915/i915_reg.h      |   3 +
> > >  drivers/gpu/drm/i915/intel_ddi.c     |  41 ++++----
> > >  drivers/gpu/drm/i915/intel_display.c |   7 +-
> > >  drivers/gpu/drm/i915/intel_dp.c      | 177 ++++++++++++++++++++---------------
> > >  drivers/gpu/drm/i915/intel_dp_mst.c  |  19 ++--
> > >  drivers/gpu/drm/i915/intel_drv.h     |   9 +-
> > >  drivers/gpu/drm/i915/intel_hdmi.c    |  26 +++--
> > >  7 files changed, 155 insertions(+), 127 deletions(-)
> > >
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp

[Ville Syrjälä]

On Tue, Aug 25, 2015 at 02:57:45PM +0200, Daniel Vetter wrote:
> On Mon, Aug 17, 2015 at 03:03:10PM +0300, Ville Syrjälä wrote:
> > On Mon, Aug 17, 2015 at 10:42:23AM +0200, Maarten Lankhorst wrote:
> > > Hey,
> > > 
> > > Op 06-07-15 om 14:09 schreef ville.syrjala@linux.intel.com:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > While working on CHV DPIO powergating I relized DP .compute_config() was
> > > > clobbering lane_count etc. stored in intel_dp. This could cause problems
> > > > if we do the .compute_config() but later fail the modeset for some reason.
> > > > Any subsequent link re-training might then fail if intel_dp->lane_count
> > > > etc. got changed.
> > > >
> > > > The reason I ran into this during the DPIO powergating work was that I may
> > > > need to know which lanes he active when shutting down the link. However
> > > > .compute_config() already clobbered that information by the time I need it.
> > > > By moving it to the pipe config we avoid that problem as well.
> > > >
> > > > I also cleaned up the limited color range handling a bit while I was
> > > > in the neighborhood.
> > > >
> > > > Ville Syrjälä (7):
> > > >   drm/i915: Clean up DP/HDMI limited color range handling
> > > >   drm/i915: Don't use link_bw for PLL setup
> > > ^
> > > >   drm/i915: Don't pass clock to DDI PLL select functions
> > > >   drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP
> > > >     .get_config()
> > > >   drm/i915: Move intel_dp->lane_count into pipe_config
> > > ^Your patch series breaks MST entirely.
> > > 
> > > drm_encoder->crtc will be NULL and dereferencing crtc->config will fail on the primary encoder:
> > > 
> > > intel_mst_pre_enable_dp(mst_enc) -> intel_ddi_init_dp_buf_reg(mst_enc->primary). -> primary->crtc = NULL, OOPS.
> > > 
> > > Voltage training was failing too and I was getting a MCE until I reverted the crtc->config changes from this series..
> > 
> > Hmm. Our modeset code vs. mst seems to a huge mess. To fix it properly
> > we should split the link compute/setup from the pipe config entirely.
> > As a short term solution I suppose I could pass the pipe config into
> > various dp link setup functions rather than assume that we can dig it
> > out from the encoder->crtc.
> 
> Luckily seris is in 4.4 only. Should I just drop it, or is it easily
> salvageable?

Fix is on the list with Maarten's t-b.

> -Daniel
> 
> > 
> > > 
> > > 
> > > >   drm/i915: Don't use link_bw to select between TP1 and TP3
> > > >   drm/i915: Kill intel_dp->{link_bw,rate_select}
> > > >
> > > >  drivers/gpu/drm/i915/i915_reg.h      |   3 +
> > > >  drivers/gpu/drm/i915/intel_ddi.c     |  41 ++++----
> > > >  drivers/gpu/drm/i915/intel_display.c |   7 +-
> > > >  drivers/gpu/drm/i915/intel_dp.c      | 177 ++++++++++++++++++++---------------
> > > >  drivers/gpu/drm/i915/intel_dp_mst.c  |  19 ++--
> > > >  drivers/gpu/drm/i915/intel_drv.h     |   9 +-
> > > >  drivers/gpu/drm/i915/intel_hdmi.c    |  26 +++--
> > > >  7 files changed, 155 insertions(+), 127 deletions(-)
> > > >
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
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