[RFC 0/8] *** DSC Inital Design RFC ***

[RFC 0/8] *** DSC Inital Design RFC ***

[vikas.korjani]

From: vkorjani <vikas.korjani@intel.com>

s RFC is for feature Display Stream Compression (DSC) for BXT,
It is a VESA defined standard to compress and decompress image in display
streams in a link independent manner. Some of the basic requirements of
the standard are to support higher resolution on a given display link
with fewer lanes or lower rate.

DSC is architected to work in current Intel Display Engine design
without modification how current display pipeline works. DSC hardware
as per HAS is in b/n port and MIPI DSI controller. so most of the
changes are at port level.

At begining of frame display can start sending valid pixels to DSC
at normal rate, DSC start compressing this image according to
pps parameters programmed already to 8bpp, 10bpp, 12bpp.

/*This bitstream is temprory stored in output buffer and sent as byte
stream to DSI controller as soon as it is valid.
*/
Following are the set of patches as per  initial design in HLD, one
can refer DSC HLD if more details about the changes is required.

Tested these patches on fulsim simulation enviornment.


vkorjani (8):
  drm/915/bxt: Adding DSC VBT parameter and PPS structures
  drm/i915/bxt: Adding registers to support DSC
  drm/i915/bxt: Init PPS, Calculate DSI frequency and DPHY parameters
    for DSC
  drm/i915/bxt: MIPI DSI Register Programming for DSC
  drm/i915/bxt: Program MIPI_DPI_RESOLUTION for DSC
  drm/i915/bxt: Enable/Disable DSC and programme PPS.
  drm: Add support for pps and compression mode command packet
  drm/i915/bxt: Send PPS packet and compression mode command packet

 drivers/gpu/drm/drm_mipi_dsi.c             |   29 +++
 drivers/gpu/drm/i915/i915_drv.h            |    2 +
 drivers/gpu/drm/i915/i915_reg.h            |  126 +++++++++++++
 drivers/gpu/drm/i915/intel_bios.h          |   74 ++++++++
 drivers/gpu/drm/i915/intel_dsi.c           |  274 ++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_dsi.h           |    5 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   23 +++
 drivers/gpu/drm/i915/intel_dsi_pll.c       |   24 ++-
 include/drm/drm_mipi_dsi.h                 |    4 +-
 include/video/mipi_display.h               |    3 +
 10 files changed, 539 insertions(+), 25 deletions(-)

-- 
1.7.9.5

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[RFC 1/8] drm/915/bxt: Adding DSC VBT parameter and PPS structures

[vikas.korjani]

From: vkorjani <vikas.korjani@intel.com>

Adding pps structure as per VESA DSC v1.1 spec.
Adding "vbt_dsc_param" vbt structure to store DSC info
vbt_dsc_param and pps structures are made part of intel_vbt_data.

Signed-off-by: vkorjani <vikas.korjani@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |    2 +
 drivers/gpu/drm/i915/intel_bios.h |   73 +++++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e1a9b0f..78f293f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1492,6 +1492,8 @@ struct intel_vbt_data {
 	union child_device_config *child_dev;
 
 	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
+	struct vbt_dsc_param dsc_param;
+	struct vbt_dsc_capablity_param capab_param;
 };
 
 enum intel_ddb_partitioning {
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index af0b476..8bc7c87 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -778,6 +778,79 @@ int intel_parse_bios(struct drm_device *dev);
 #define MIPI_DSI_UNDEFINED_PANEL_ID	0
 #define MIPI_DSI_GENERIC_PANEL_ID	1
 
+struct vesa_dsc_rc_range_param {
+	u8 range_min_qp;
+	u8 range_max_qp;
+	u8 range_bpg_offset;
+};
+
+struct vesa_dsc_rc_param {
+	u16 model_size;
+	u8 rc_edge_factor;
+	u8 rc_quant_incr_limit0;
+	u8 rc_quant_incr_limit1;
+	u8 rc_tgt_offset_hi;
+	u8 rc_tgt_offset_lo;
+	u8 rc_buf_thresh[14];
+	struct vesa_dsc_rc_range_param rc_range[16];
+};
+
+struct vesa_dsc_pps_data {
+	u8 dsc_ver_major;
+	u8 dsc_ver_minor;
+	u8 pps_identifier;
+	u8 bit_per_comp;
+	u8 line_buf_depth;
+	u8 block_pred_enable;
+	u8 convert_rgb;
+	u8 enable_422;
+	u8 enable_vbr;
+	u16 bits_per_pixel;
+	u16 pic_width;
+	u16 pic_height;
+	u16 slice_width;
+	u16 slice_height;
+	u16 chunk_size;
+	u16 initial_xmit_delay;
+	u16 initial_dec_delay;
+	u8 initial_scale_value;
+	u16 scale_increment_interval;
+	u16 scale_decrement_interval;
+	u8 first_line_bpg_offset;
+	u16 nfl_bpg_offset;
+	u16 slice_bpg_offset;
+	u16 initial_offset;
+	u16 final_offset;
+	u8 flatness_min_qp;
+	u8 flatness_max_qp;
+	struct vesa_dsc_rc_param rc_param;
+};
+
+struct vbt_dsc_capablity_param {
+	u8 block_prediction_allowed;
+	u8 disp_bpc;
+	u8 line_buf_bit_depth;
+	u16 picture_height;
+	u16 picture_width;
+	u16 rate_buffer_size;
+	u16 slice_height;
+	u16 slice_width;
+	u8 supported_dsc_version;
+	u8 vbr_allowed;
+};
+struct vbt_dsc_param {
+	u8 dsc_support;
+	u8 valid_pps;
+	u8 block_prediction;
+	u8 panel_bpc;
+	u8 bit_depth;
+	u16 rate_buffer_size;
+	u16 slice_height;
+	u16 slice_width;
+	u8 dsc_version;
+	struct vesa_dsc_pps_data pps_data;
+};
+
 struct mipi_config {
 	u16 panel_id;
 
-- 
1.7.9.5

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[RFC 2/8] drm/i915/bxt: Adding registers to support DSC

[vikas.korjani]

From: vkorjani <vikas.korjani@intel.com>

This patch adds register definitions required to support
DSC feature.

Signed-off-by: vkorjani <vikas.korjani@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  126 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_bios.h |    1 +
 2 files changed, 127 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b1d7ff..b41da94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7666,12 +7666,15 @@ enum skl_disp_power_wells {
 #define  CMD_MODE_DATA_WIDTH_8_BIT			(3 << 13)
 #define  CMD_MODE_DATA_WIDTH_OPTION1			(4 << 13)
 #define  CMD_MODE_DATA_WIDTH_OPTION2			(5 << 13)
+#define  CMD_MODE_DATA_WIDTH_OPTION2_SKIP_LAST          (6 << 13)
+#define  CMD_MODE_DATA_WIDTH_OPTION2_SKIP_LAST2         (7 << 13)
 #define  VID_MODE_FORMAT_MASK				(0xf << 7)
 #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
 #define  VID_MODE_FORMAT_RGB565				(1 << 7)
 #define  VID_MODE_FORMAT_RGB666				(2 << 7)
 #define  VID_MODE_FORMAT_RGB666_LOOSE			(3 << 7)
 #define  VID_MODE_FORMAT_RGB888				(4 << 7)
+#define  VID_MODE_FORMAT_COMPRESSED                     (8 << 7)
 #define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
 #define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
 #define  VID_MODE_CHANNEL_NUMBER_SHIFT			3
@@ -7965,6 +7968,7 @@ enum skl_disp_power_wells {
 #define  BXT_PIPE_SELECT_C				(2 << 7)
 #define  BXT_PIPE_SELECT_B				(1 << 7)
 #define  BXT_PIPE_SELECT_A				(0 << 7)
+#define  BXT_DSC_ENABLE                                 (1 << 3)
 
 #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
 #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
@@ -8010,6 +8014,128 @@ enum skl_disp_power_wells {
 				_MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
 #define  READ_DATA_VALID(n)				(1 << (n))
 
+#define DSC_A_PICTURE_PARAMETER_SET_0    (dev_priv->mipi_mmio_base + 0xb200)
+#define DSC_A_PICTURE_PARAMETER_SET_1    (dev_priv->mipi_mmio_base + 0xb204)
+#define DSC_A_PICTURE_PARAMETER_SET_2    (dev_priv->mipi_mmio_base + 0xb208)
+#define DSC_A_PICTURE_PARAMETER_SET_3    (dev_priv->mipi_mmio_base + 0xb20c)
+#define DSC_A_PICTURE_PARAMETER_SET_4    (dev_priv->mipi_mmio_base + 0xb210)
+#define DSC_A_PICTURE_PARAMETER_SET_5    (dev_priv->mipi_mmio_base + 0xb214)
+#define DSC_A_PICTURE_PARAMETER_SET_6    (dev_priv->mipi_mmio_base + 0xb218)
+#define DSC_A_PICTURE_PARAMETER_SET_7    (dev_priv->mipi_mmio_base + 0xb21c)
+#define DSC_A_PICTURE_PARAMETER_SET_8    (dev_priv->mipi_mmio_base + 0xb220)
+#define DSC_A_PICTURE_PARAMETER_SET_9    (dev_priv->mipi_mmio_base + 0xb224)
+#define DSC_A_PICTURE_PARAMETER_SET_10   (dev_priv->mipi_mmio_base + 0xb228)
+#define DSC_A_PICTURE_PARAMETER_SET_11   (dev_priv->mipi_mmio_base + 0xb22c)
+#define DSC_A_PICTURE_PARAMETER_SET_12   (dev_priv->mipi_mmio_base + 0xb260)
+#define DSC_A_PICTURE_PARAMETER_SET_13   (dev_priv->mipi_mmio_base + 0xb264)
+#define DSC_A_PICTURE_PARAMETER_SET_14   (dev_priv->mipi_mmio_base + 0xb268)
+#define DSC_A_PICTURE_PARAMETER_SET_15   (dev_priv->mipi_mmio_base + 0xb26c)
+#define DSC_A_PICTURE_PARAMETER_SET_16   (dev_priv->mipi_mmio_base + 0xb270)
+#define DSC_A_RC_BUF_THRESH_0_3         (dev_priv->mipi_mmio_base + 0xb230)
+#define DSC_A_RC_BUF_THRESH_4_7         (dev_priv->mipi_mmio_base + 0xb234)
+#define DSC_A_RC_BUF_THRESH_8_11        (dev_priv->mipi_mmio_base + 0xb238)
+#define DSC_A_RC_BUF_THRESH_12_13       (dev_priv->mipi_mmio_base + 0xb23C)
+#define DSC_A_RC_RANGE_PARAMETERS_0     (dev_priv->mipi_mmio_base + 0xb240)
+#define DSC_A_RC_RANGE_PARAMETERS_1     (dev_priv->mipi_mmio_base + 0xb244)
+#define DSC_A_RC_RANGE_PARAMETERS_2     (dev_priv->mipi_mmio_base + 0xb248)
+#define DSC_A_RC_RANGE_PARAMETERS_3     (dev_priv->mipi_mmio_base + 0xb24C)
+#define DSC_A_RC_RANGE_PARAMETERS_4     (dev_priv->mipi_mmio_base + 0xb250)
+#define DSC_A_RC_RANGE_PARAMETERS_5     (dev_priv->mipi_mmio_base + 0xb254)
+#define DSC_A_RC_RANGE_PARAMETERS_6     (dev_priv->mipi_mmio_base + 0xb258)
+#define DSC_A_RC_RANGE_PARAMETERS_7     (dev_priv->mipi_mmio_base + 0xb25C)
+
+#define DSC_C_PICTURE_PARAMETER_SET_0    (dev_priv->mipi_mmio_base + 0xba00)
+#define DSC_C_PICTURE_PARAMETER_SET_1    (dev_priv->mipi_mmio_base + 0xba04)
+#define DSC_C_PICTURE_PARAMETER_SET_2    (dev_priv->mipi_mmio_base + 0xba08)
+#define DSC_C_PICTURE_PARAMETER_SET_3    (dev_priv->mipi_mmio_base + 0xba0c)
+#define DSC_C_PICTURE_PARAMETER_SET_4    (dev_priv->mipi_mmio_base + 0xba10)
+#define DSC_C_PICTURE_PARAMETER_SET_5    (dev_priv->mipi_mmio_base + 0xba14)
+#define DSC_C_PICTURE_PARAMETER_SET_6    (dev_priv->mipi_mmio_base + 0xba18)
+#define DSC_C_PICTURE_PARAMETER_SET_7    (dev_priv->mipi_mmio_base + 0xba1c)
+#define DSC_C_PICTURE_PARAMETER_SET_8    (dev_priv->mipi_mmio_base + 0xba20)
+#define DSC_C_PICTURE_PARAMETER_SET_9    (dev_priv->mipi_mmio_base + 0xba24)
+#define DSC_C_PICTURE_PARAMETER_SET_10   (dev_priv->mipi_mmio_base + 0xba28)
+#define DSC_C_PICTURE_PARAMETER_SET_11   (dev_priv->mipi_mmio_base + 0xba2c)
+#define DSC_C_PICTURE_PARAMETER_SET_12   (dev_priv->mipi_mmio_base + 0xba60)
+#define DSC_C_PICTURE_PARAMETER_SET_13   (dev_priv->mipi_mmio_base + 0xba64)
+#define DSC_C_PICTURE_PARAMETER_SET_14   (dev_priv->mipi_mmio_base + 0xba68)
+#define DSC_C_PICTURE_PARAMETER_SET_15   (dev_priv->mipi_mmio_base + 0xba6c)
+#define DSC_C_PICTURE_PARAMETER_SET_16   (dev_priv->mipi_mmio_base + 0xba70)
+#define DSC_C_RC_BUF_THRESH_0_3         (dev_priv->mipi_mmio_base + 0xba30)
+#define DSC_C_RC_BUF_THRESH_4_7         (dev_priv->mipi_mmio_base + 0xba34)
+#define DSC_C_RC_BUF_THRESH_8_11        (dev_priv->mipi_mmio_base + 0xba38)
+#define DSC_C_RC_BUF_THRESH_12_13       (dev_priv->mipi_mmio_base + 0xba3C)
+#define DSC_C_RC_RANGE_PARAMETERS_0     (dev_priv->mipi_mmio_base + 0xba40)
+#define DSC_C_RC_RANGE_PARAMETERS_1     (dev_priv->mipi_mmio_base + 0xba44)
+#define DSC_C_RC_RANGE_PARAMETERS_2     (dev_priv->mipi_mmio_base + 0xba48)
+#define DSC_C_RC_RANGE_PARAMETERS_3     (dev_priv->mipi_mmio_base + 0xba4C)
+#define DSC_C_RC_RANGE_PARAMETERS_4     (dev_priv->mipi_mmio_base + 0xba50)
+#define DSC_C_RC_RANGE_PARAMETERS_5     (dev_priv->mipi_mmio_base + 0xba54)
+#define DSC_C_RC_RANGE_PARAMETERS_6     (dev_priv->mipi_mmio_base + 0xba58)
+#define DSC_C_RC_RANGE_PARAMETERS_7     (dev_priv->mipi_mmio_base + 0xba5C)
+
+#define DSC_PICTURE_PARAMETER_SET_0(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_0, DSC_C_PICTURE_PARAMETER_SET_0)
+#define DSC_PICTURE_PARAMETER_SET_1(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_1, DSC_C_PICTURE_PARAMETER_SET_1)
+#define DSC_PICTURE_PARAMETER_SET_2(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_2, DSC_C_PICTURE_PARAMETER_SET_2)
+#define DSC_PICTURE_PARAMETER_SET_3(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_3, DSC_C_PICTURE_PARAMETER_SET_3)
+#define DSC_PICTURE_PARAMETER_SET_4(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_4, DSC_C_PICTURE_PARAMETER_SET_4)
+#define DSC_PICTURE_PARAMETER_SET_5(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_5, DSC_C_PICTURE_PARAMETER_SET_5)
+#define DSC_PICTURE_PARAMETER_SET_6(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_6, DSC_C_PICTURE_PARAMETER_SET_6)
+#define DSC_PICTURE_PARAMETER_SET_7(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_7, DSC_C_PICTURE_PARAMETER_SET_7)
+#define DSC_PICTURE_PARAMETER_SET_8(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_8, DSC_C_PICTURE_PARAMETER_SET_8)
+#define DSC_PICTURE_PARAMETER_SET_9(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_9, DSC_C_PICTURE_PARAMETER_SET_9)
+#define DSC_PICTURE_PARAMETER_SET_10(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_10, DSC_C_PICTURE_PARAMETER_SET_10)
+#define DSC_PICTURE_PARAMETER_SET_11(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_11, DSC_C_PICTURE_PARAMETER_SET_11)
+#define DSC_PICTURE_PARAMETER_SET_12(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_12, DSC_C_PICTURE_PARAMETER_SET_12)
+#define DSC_PICTURE_PARAMETER_SET_13(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_13, DSC_C_PICTURE_PARAMETER_SET_13)
+#define DSC_PICTURE_PARAMETER_SET_14(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_14, DSC_C_PICTURE_PARAMETER_SET_14)
+#define DSC_PICTURE_PARAMETER_SET_15(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_15, DSC_C_PICTURE_PARAMETER_SET_15)
+#define DSC_PICTURE_PARAMETER_SET_16(port) _TRANSCODER(port, \
+		DSC_A_PICTURE_PARAMETER_SET_16, DSC_C_PICTURE_PARAMETER_SET_16)
+#define DSC_RC_BUF_THRESH_0_3(port) _TRANSCODER(port, \
+		DSC_A_RC_BUF_THRESH_0_3, DSC_C_RC_BUF_THRESH_0_3)
+#define DSC_RC_BUF_THRESH_4_7(port) _TRANSCODER(port, \
+		DSC_A_RC_BUF_THRESH_4_7, DSC_C_RC_BUF_THRESH_4_7)
+#define DSC_RC_BUF_THRESH_8_11(port) _TRANSCODER(port, \
+		DSC_A_RC_BUF_THRESH_8_11, DSC_C_RC_BUF_THRESH_8_11)
+#define DSC_RC_BUF_THRESH_12_13(port) _TRANSCODER(port, \
+		DSC_A_RC_BUF_THRESH_12_13, DSC_C_RC_BUF_THRESH_12_13)
+#define DSC_RC_RANGE_PARAMETERS_0(port) _TRANSCODER(port, \
+		DSC_A_RC_RANGE_PARAMETERS_0, DSC_C_RC_RANGE_PARAMETERS_0)
+#define DSC_RC_RANGE_PARAMETERS_1(port) _TRANSCODER(port, \
+		DSC_A_RC_RANGE_PARAMETERS_1, DSC_C_RC_RANGE_PARAMETERS_1)
+#define DSC_RC_RANGE_PARAMETERS_2(port) _TRANSCODER(port, \
+		DSC_A_RC_RANGE_PARAMETERS_2, DSC_C_RC_RANGE_PARAMETERS_2)
+#define DSC_RC_RANGE_PARAMETERS_3(port) _TRANSCODER(port, \
+		DSC_A_RC_RANGE_PARAMETERS_3, DSC_C_RC_RANGE_PARAMETERS_3)
+#define DSC_RC_RANGE_PARAMETERS_4(port) _TRANSCODER(port, \
+		DSC_A_RC_RANGE_PARAMETERS_4, DSC_C_RC_RANGE_PARAMETERS_4)
+#define DSC_RC_RANGE_PARAMETERS_5(port) _TRANSCODER(port, \
+		DSC_A_RC_RANGE_PARAMETERS_5, DSC_C_RC_RANGE_PARAMETERS_5)
+#define DSC_RC_RANGE_PARAMETERS_6(port) _TRANSCODER(port, \
+		DSC_A_RC_RANGE_PARAMETERS_6, DSC_C_RC_RANGE_PARAMETERS_6)
+#define DSC_RC_RANGE_PARAMETERS_7(port) _TRANSCODER(port, \
+		DSC_A_RC_RANGE_PARAMETERS_7, DSC_C_RC_RANGE_PARAMETERS_7)
+
+#define DSC_CRC_CTL                     (dev_priv->mipi_mmio_base + 0xb284)
+#define DSC_CRC_RES                     (dev_priv->mipi_mmio_base + 0xb288)
+
 /* For UMS only (deprecated): */
 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 8bc7c87..6b4d664 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -875,6 +875,7 @@ struct mipi_config {
 #define PIXEL_FORMAT_RGB666			0x2
 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
 #define PIXEL_FORMAT_RGB888			0x4
+#define PIXEL_FORMAT_COMPRESSED                 0x8
 	u32 videomode_color_format:4;
 
 	/* Bit 15:14 */
-- 
1.7.9.5

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[RFC 3/8] drm/i915/bxt: Init PPS, Calculate DSI frequency and DPHY parameters for DSC

[vikas.korjani]

From: vkorjani <vikas.korjani@intel.com>

This patch adds code to initialize Picture  Parameter set (PPS)
data structure for DSC.
DSC is enabled than the bitrate should be calculated using the
formula pixel_clock * bits_per_pixel / lane_count, where
bits_per_pixel can be 8bpp, 10bpp, 12bpp.
value of bits_per_pixel is available in step of 1/16 in
pps date structure.
DPHY parameters are computed based on data rate calculated
as per bits_per_pixel provided in pps data structure.

Signed-off-by: vkorjani <vikas.korjani@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.h           |    5 +++++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   11 +++++++++++
 drivers/gpu/drm/i915/intel_dsi_pll.c       |   24 ++++++++++++++++--------
 3 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 24fc550..699f995 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -96,6 +96,11 @@ struct intel_dsi {
 	u16 panel_on_delay;
 	u16 panel_off_delay;
 	u16 panel_pwr_cycle_delay;
+
+	/*DSC Support */
+	u8 dsc_enable;
+	struct vesa_dsc_pps_data pps_data;
+	u8 dsc_bpp;
 };
 
 struct intel_dsi_host {
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index a5e99ac..f893d37 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -413,6 +413,17 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 		bits_per_pixel = 18;
 	else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
 		bits_per_pixel = 16;
+	else if (intel_dsi->pixel_format == VID_MODE_FORMAT_COMPRESSED &&
+			dev_priv->vbt.dsc_param.dsc_support) {
+		intel_dsi->dsc_enable = true;
+		intel_dsi->dsc_bpp =
+			(intel_dsi->pps_data.bits_per_pixel / 16);
+		bits_per_pixel = intel_dsi->dsc_bpp;
+		intel_dsi->pps_data =
+			dev_priv->vbt.dsc_param.pps_data;
+		/*TODO If PPS not available in VBT compute PPS
+		 * from capablity parameter set in vbt */
+	}
 
 	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
 	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index b647f13..38c9433 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -143,10 +143,17 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode,
 #else
 
 /* Get DSI clock from pixel clock */
-static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
+static u32 dsi_clk_from_pclk(struct intel_encoder *encoder,
+			u32 pclk, int pixel_format, int lane_count)
 {
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 dsi_clk_khz;
-	u32 bpp = dsi_pixel_format_bpp(pixel_format);
+	u32 bpp;
+
+	if (intel_dsi->dsc_enable)
+		bpp =  intel_dsi->dsc_bpp;
+	else
+		bpp = dsi_pixel_format_bpp(pixel_format);
 
 	/* DSI data rate = pixel clock * bits per pixel / lane count
 	   pixel clock is converted from KHz to Hz */
@@ -223,8 +230,8 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
 	struct dsi_mnp dsi_mnp;
 	u32 dsi_clk;
 
-	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
-				    intel_dsi->lane_count);
+	dsi_clk = dsi_clk_from_pclk(encoder, intel_dsi->pclk,
+			intel_dsi->pixel_format, intel_dsi->lane_count);
 
 	ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
 	if (ret) {
@@ -410,8 +417,9 @@ u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
 
 	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
 
-	/* pixel_format and pipe_bpp should agree */
-	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
+	/* pixel_format and pipe_bpp should agree if DSC is not enabled */
+	if (!intel_dsi->dsc_enable)
+		assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
 
 	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
 
@@ -475,8 +483,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
 	u32 dsi_clk;
 	u32 val;
 
-	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
-			intel_dsi->lane_count);
+	dsi_clk = dsi_clk_from_pclk(encoder, intel_dsi->pclk,
+			intel_dsi->pixel_format, intel_dsi->lane_count);
 
 	/*
 	 * From clock diagram, to get PLL ratio divider, divide double of DSI
-- 
1.7.9.5

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[RFC 4/8] drm/i915/bxt: MIPI DSI Register Programming for DSC

[vikas.korjani]

From: vkorjani <vikas.korjani@intel.com>

For compression enabled, the number of bytes in active
region cannot be calculated just by multiplying number
of pixels and bits per pixel, formula in HLD is

ceil((ceil(pixels/num_slice) * bpp) / 8) * num_slice

hence modifying txbyteclkhs() to accommodate calculation
for DSC Enable/Disable  and created a separate
function pixel_to_bytes().

Using modified txbyteclkhs to calculate MIPI_HS_TX_TIMEOUT
As per HLD for computing MIPI_HS_TX_TIMEOUT per line,
1) calculate number of bytes in active region
2) calculate number of bytes in blanking region
Add above two and compute byteclkhs.
similarly for MIPI_HX_TX_TIMEOUT per frame, Add bytes in
active and blanking region should be calculated separately.

Signed-off-by: vkorjani <vikas.korjani@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   74 ++++++++++++++++++++++++++++++--------
 1 file changed, 59 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 36fcb86..e566750 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -760,12 +760,48 @@ static u16 txclkesc(u32 divider, unsigned int us)
 	}
 }
 
+static int compute_num_slice(struct drm_encoder *encoder)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+
+	return DIV_ROUND_UP(intel_dsi->pps_data.pic_height*
+			intel_dsi->pps_data.pic_width,
+			intel_dsi->pps_data.slice_height*
+			intel_dsi->pps_data.slice_width);
+}
+
+static u32 pixel_to_bytes(struct drm_encoder *encoder, u16 pixels, int bpp)
+{
+
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+	int num_slice;
+
+	if (intel_dsi->dsc_enable) {
+		num_slice = compute_num_slice(encoder);
+		if (num_slice <= 0)
+			num_slice = 1;
+		bpp =  intel_dsi->pps_data.bits_per_pixel / 16;
+		return DIV_ROUND_UP((DIV_ROUND_UP(pixels, num_slice)) * bpp, 8)
+			* num_slice;
+	} else
+		return DIV_ROUND_UP((pixels * bpp), 8);
+}
+
+
 /* return pixels in terms of txbyteclkhs */
-static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
-		       u16 burst_mode_ratio)
+static u16 txbyteclkhs(struct drm_encoder *encoder, u16 pixels, int bpp,
+		int lane_count, u16 burst_mode_ratio, bool dsc_calc)
 {
-	return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
-					 8 * 100), lane_count);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+	u32 pixel_bytes;
+
+	if (intel_dsi->dsc_enable && dsc_calc) {
+		pixel_bytes = pixel_to_bytes(encoder, pixels, bpp);
+		return DIV_ROUND_UP(DIV_ROUND_UP(pixel_bytes *
+					burst_mode_ratio, 100), lane_count);
+	} else
+		return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp *
+			burst_mode_ratio, 8 * 100), lane_count);
 }
 
 static void set_dsi_timings(struct drm_encoder *encoder,
@@ -800,12 +836,14 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 	vbp = mode->vtotal - mode->vsync_end;
 
 	/* horizontal values are in terms of high speed byte clock */
-	hactive = txbyteclkhs(hactive, bpp, lane_count,
-			      intel_dsi->burst_mode_ratio);
-	hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
-	hsync = txbyteclkhs(hsync, bpp, lane_count,
-			    intel_dsi->burst_mode_ratio);
-	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
+	hactive = txbyteclkhs(encoder, hactive, bpp, lane_count,
+			      intel_dsi->burst_mode_ratio, true);
+	hfp = txbyteclkhs(encoder, hfp, bpp, lane_count,
+				intel_dsi->burst_mode_ratio, true);
+	hsync = txbyteclkhs(encoder, hsync, bpp, lane_count,
+			    intel_dsi->burst_mode_ratio, true);
+	hbp = txbyteclkhs(encoder, hbp, bpp, lane_count,
+				intel_dsi->burst_mode_ratio, true);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
 		if (IS_BROXTON(dev)) {
@@ -851,6 +889,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	unsigned int bpp = intel_crtc->config->pipe_bpp;
 	u32 val, tmp;
 	u16 mode_hdisplay;
+	u32 hactive, hblank;
 
 	DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 
@@ -943,18 +982,23 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 		 * said value is recommended.
 		 */
 
+		hactive = pixel_to_bytes(encoder, adjusted_mode->hdisplay, bpp);
+		hblank = pixel_to_bytes(encoder, (adjusted_mode->htotal -
+					adjusted_mode->hsync_end), bpp);
+
 		if (is_vid_mode(intel_dsi) &&
 			intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-				txbyteclkhs(adjusted_mode->htotal, bpp,
+				txbyteclkhs(encoder, (hactive + hblank), bpp,
 					intel_dsi->lane_count,
-					intel_dsi->burst_mode_ratio) + 1);
+					intel_dsi->burst_mode_ratio, true) + 1);
 		} else {
 			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
-				txbyteclkhs(adjusted_mode->vtotal *
-					adjusted_mode->htotal,
+				txbyteclkhs(encoder, adjusted_mode->vtotal *
+					(hactive + hblank),
 					bpp, intel_dsi->lane_count,
-					intel_dsi->burst_mode_ratio) + 1);
+					intel_dsi->burst_mode_ratio, false) +
+					1);
 		}
 		I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
 		I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
-- 
1.7.9.5

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[RFC 5/8] drm/i915/bxt: Program MIPI_DPI_RESOLUTION for DSC

[vikas.korjani]

From: vkorjani <vikas.korjani@intel.com>

Program the MIPI_DPI_RESOLUTION register horizontal
resolution using the byte_to_pixels() DSC specific
function in case of compression enabled.
For non-compressed video, the number of pixels
in active region are computed as usual.

Change-Id: Iacea79352fa67a40a1d305494539f7c99f2715d0
Signed-off-by: vkorjani <vikas.korjani@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index e566750..9963ec2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -901,6 +901,9 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 			mode_hdisplay += intel_dsi->pixel_overlap;
 	}
 
+	if (intel_dsi->dsc_enable)
+		mode_hdisplay =  pixel_to_bytes(encoder, mode_hdisplay, bpp);
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		if (IS_VALLEYVIEW(dev)) {
 			/*
-- 
1.7.9.5

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[RFC 6/8] drm/i915/bxt: Enable/Disable DSC and programme PPS.

[vikas.korjani]

From: vkorjani <vikas.korjani@intel.com>

Program the PPS data from intel_dsc->vesa_dsc_pps_data
into display controller register DSCx_PICTURE_PARAMETER_SET_x.
DSC should be enabled in MIPI Port control register, after
programming PPS register
Disable DSC in disable sequence after disabling port.

Signed-off-by: vkorjani <vikas.korjani@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |  197 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 196 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 9963ec2..c011966 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -411,7 +411,12 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 		/* de-assert ip_tg_enable signal */
 		port_ctrl = GET_DSI_PORT_CTRL(dev);
 		temp = I915_READ(port_ctrl);
-		I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
+		temp &= ~DPI_ENABLE;
+		if (intel_dsi->dsc_enable) {
+			temp &= ~BXT_DSC_ENABLE;
+			temp &= ~RGB_FLIP_TO_BGR;
+		}
+		I915_WRITE(port_ctrl, temp);
 		POSTING_READ(port_ctrl);
 	}
 }
@@ -876,6 +881,188 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 	}
 }
 
+static void intel_dsi_program_pps(struct drm_encoder *encoder, int port)
+{
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+	u32 tmp = 0;
+
+	tmp |= intel_dsi->pps_data.dsc_ver_major << 0;
+	tmp |= intel_dsi->pps_data.dsc_ver_minor << 4;
+	tmp |= intel_dsi->pps_data.bit_per_comp << 8;
+	tmp |= intel_dsi->pps_data.line_buf_depth << 12;
+	tmp |= intel_dsi->pps_data.block_pred_enable << 16;
+	tmp |= intel_dsi->pps_data.convert_rgb << 17;
+	tmp |= intel_dsi->pps_data.enable_422 << 18;
+	tmp |= intel_dsi->pps_data.enable_vbr << 19;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_0(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.bits_per_pixel << 0;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_1(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.pic_height << 0;
+	tmp |= intel_dsi->pps_data.pic_width << 16;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_2(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.slice_height << 0;
+	tmp |= intel_dsi->pps_data.slice_width << 16;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_3(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.initial_xmit_delay << 0;
+	tmp |= intel_dsi->pps_data.initial_dec_delay << 16;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_4(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.scale_increment_interval << 0;
+	tmp |= intel_dsi->pps_data.scale_decrement_interval << 16;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_5(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.initial_scale_value << 0;
+	tmp |= intel_dsi->pps_data.first_line_bpg_offset << 8;
+	tmp |= intel_dsi->pps_data.flatness_min_qp << 16;
+	tmp |= intel_dsi->pps_data.flatness_max_qp << 24;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_6(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.slice_bpg_offset << 0;
+	tmp |= intel_dsi->pps_data.nfl_bpg_offset << 16;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_7(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.final_offset << 0;
+	tmp |= intel_dsi->pps_data.initial_offset << 16;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_8(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.rc_param.model_size << 0;
+	tmp |= intel_dsi->pps_data.rc_param.rc_edge_factor << 16;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_9(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.rc_param.rc_quant_incr_limit0 << 0;
+	tmp |= intel_dsi->pps_data.rc_param.rc_quant_incr_limit1 << 8;
+	tmp |= intel_dsi->pps_data.rc_param.rc_tgt_offset_hi << 16;
+	tmp |= intel_dsi->pps_data.rc_param.rc_tgt_offset_lo << 20;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_10(port), tmp);
+
+	tmp = 0;
+	tmp |= intel_dsi->pps_data.chunk_size << 0;
+	tmp |= 0x04 << 16;
+	tmp |= 0x78 << 20;
+	I915_WRITE(DSC_PICTURE_PARAMETER_SET_16(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_buf_thresh[0] << 0 |
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[1] << 8 |
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[2] << 16|
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[3] << 24;
+	I915_WRITE(DSC_RC_BUF_THRESH_0_3(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_buf_thresh[4] << 0 |
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[5] << 8 |
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[6] << 16 |
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[7] << 24;
+	I915_WRITE(DSC_RC_BUF_THRESH_4_7(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_buf_thresh[8]  << 0 |
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[9] << 8 |
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[10] << 16 |
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[11] << 24;
+	I915_WRITE(DSC_RC_BUF_THRESH_8_11(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_buf_thresh[12] << 0 |
+		intel_dsi->pps_data.rc_param.rc_buf_thresh[13] << 8;
+	I915_WRITE(DSC_RC_BUF_THRESH_12_13(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_range[0].range_min_qp|
+		intel_dsi->pps_data.rc_param.rc_range[0].range_max_qp << 5|
+		intel_dsi->pps_data.rc_param.rc_range[0].range_bpg_offset << 10|
+		intel_dsi->pps_data.rc_param.rc_range[1].range_min_qp << 16|
+		intel_dsi->pps_data.rc_param.rc_range[1].range_max_qp << 21|
+		intel_dsi->pps_data.rc_param.rc_range[1].
+		range_bpg_offset << 26;
+	I915_WRITE(DSC_RC_RANGE_PARAMETERS_0(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_range[2].range_min_qp|
+		intel_dsi->pps_data.rc_param.rc_range[2].range_max_qp << 5|
+		intel_dsi->pps_data.rc_param.rc_range[2].range_bpg_offset << 10|
+		intel_dsi->pps_data.rc_param.rc_range[3].range_min_qp << 16 |
+		intel_dsi->pps_data.rc_param.rc_range[3].range_max_qp << 21 |
+		intel_dsi->pps_data.rc_param.rc_range[3].range_bpg_offset << 26;
+	I915_WRITE(DSC_RC_RANGE_PARAMETERS_1(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_range[4].range_min_qp |
+		intel_dsi->pps_data.rc_param.rc_range[4].range_max_qp << 5 |
+		intel_dsi->pps_data.rc_param.rc_range[4].range_bpg_offset << 10|
+		intel_dsi->pps_data.rc_param.rc_range[5].range_min_qp << 16 |
+		intel_dsi->pps_data.rc_param.rc_range[5].range_max_qp << 21 |
+		intel_dsi->pps_data.rc_param.rc_range[5].range_bpg_offset << 26;
+	I915_WRITE(DSC_RC_RANGE_PARAMETERS_2(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_range[6].range_min_qp |
+		intel_dsi->pps_data.rc_param.rc_range[6].range_max_qp << 5 |
+		intel_dsi->pps_data.rc_param.rc_range[6].range_bpg_offset << 10|
+		intel_dsi->pps_data.rc_param.rc_range[7].range_min_qp << 16 |
+		intel_dsi->pps_data.rc_param.rc_range[7].range_max_qp << 21 |
+		intel_dsi->pps_data.rc_param.rc_range[7].range_bpg_offset << 26;
+	I915_WRITE(DSC_RC_RANGE_PARAMETERS_3(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_range[8].range_min_qp |
+		intel_dsi->pps_data.rc_param.rc_range[8].range_max_qp << 5 |
+		intel_dsi->pps_data.rc_param.rc_range[8].range_bpg_offset << 10|
+		intel_dsi->pps_data.rc_param.rc_range[9].range_min_qp << 16 |
+		intel_dsi->pps_data.rc_param.rc_range[9].range_max_qp << 21 |
+		intel_dsi->pps_data.rc_param.rc_range[9].range_bpg_offset << 26;
+	I915_WRITE(DSC_RC_RANGE_PARAMETERS_4(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_range[10].range_min_qp |
+		intel_dsi->pps_data.rc_param.rc_range[10].range_max_qp << 5 |
+		intel_dsi->pps_data.rc_param.rc_range[10].
+		range_bpg_offset << 10|
+		intel_dsi->pps_data.rc_param.rc_range[11].range_min_qp << 16 |
+		intel_dsi->pps_data.rc_param.rc_range[11].range_max_qp << 21 |
+		intel_dsi->pps_data.rc_param.rc_range[11].
+		range_bpg_offset << 26;
+	I915_WRITE(DSC_RC_RANGE_PARAMETERS_5(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_range[12].range_min_qp |
+		intel_dsi->pps_data.rc_param.rc_range[12].range_max_qp << 5 |
+		intel_dsi->pps_data.rc_param.rc_range[12].
+		range_bpg_offset << 10|
+		intel_dsi->pps_data.rc_param.rc_range[13].range_min_qp << 16 |
+		intel_dsi->pps_data.rc_param.rc_range[13].range_max_qp << 21 |
+		intel_dsi->pps_data.rc_param.rc_range[13].
+		range_bpg_offset << 26;
+	I915_WRITE(DSC_RC_RANGE_PARAMETERS_6(port), tmp);
+
+	tmp = 0;
+	tmp = intel_dsi->pps_data.rc_param.rc_range[14].range_min_qp |
+	       intel_dsi->pps_data.rc_param.rc_range[14].range_max_qp << 5 |
+	       intel_dsi->pps_data.rc_param.rc_range[14].
+	       range_bpg_offset << 10|
+	       intel_dsi->pps_data.rc_param.rc_range[15].range_min_qp << 16 |
+	       intel_dsi->pps_data.rc_param.rc_range[15].range_max_qp << 21 |
+	       intel_dsi->pps_data.rc_param.rc_range[15].
+	       range_bpg_offset << 26;
+	I915_WRITE(DSC_RC_RANGE_PARAMETERS_7(port), tmp);
+}
+
 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 {
 	struct drm_encoder *encoder = &intel_encoder->base;
@@ -932,6 +1119,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 			tmp &= ~BXT_PIPE_SELECT_MASK;
 			(port == PORT_C) ? (tmp |= BXT_PIPE_SELECT_C) :
 				(tmp |= BXT_PIPE_SELECT_A);
+
+			if (intel_dsi->dsc_enable) {
+				intel_dsi_program_pps(encoder, port);
+				/* Need to verify this delay */
+				msleep(20);
+				tmp |= BXT_DSC_ENABLE;
+				tmp |= RGB_FLIP_TO_BGR;
+			}
 			I915_WRITE(MIPI_CTRL(port), tmp);
 		}
 
-- 
1.7.9.5

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[RFC 7/8] drm: Add support for pps and compression mode command packet

[vikas.korjani]

From: vkorjani <vikas.korjani@intel.com>

After enabling DSC we need to send compression mode command packet
and pps data packet, for which 2 new data types are added
07h  Compression Mode Data Type Write , short write, 2 parameters
0Ah  PPS Long Write (word count determines number of bytes)
This patch adds support to send these packets.

Cc: David Airlie <airlied@linux.ie>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-fbdev@vger.kernel.org

Signed-off-by: vkorjani <vikas.korjani@intel.com>
---
 drivers/gpu/drm/drm_mipi_dsi.c |   29 +++++++++++++++++++++++++++++
 include/drm/drm_mipi_dsi.h     |    4 +++-
 include/video/mipi_display.h   |    3 +++
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index 2d5ca8ee..cd536d1 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -521,6 +521,35 @@ ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi,
 EXPORT_SYMBOL(mipi_dsi_dcs_write_buffer);
 
 /**
+ *   mipi_dsi_dsc_pps_write_buffer() - transmit a DSC command with payload
+ *   @dsi: DSI peripheral device
+ *   @data: buffer containing data to be transmitted
+ *   @len: size of transmission buffer
+ *
+ *   function will automatically choose the right data type depending on
+ *   the command payload length.
+ *
+ *   Return: The number of bytes successfully transmitted or a negative error
+ *   code on failure.*/
+ssize_t mipi_dsi_dsc_pps_write_buffer(struct mipi_dsi_device *dsi,
+		const void *data, size_t len)
+{
+	 struct mipi_dsi_msg msg = {
+		.channel = dsi->channel,
+		.tx_buf = data,
+		.tx_len = len
+	 };
+
+	if (len == 0)
+		msg.type = MIPI_DSI_DCS_COMPRESSION_MODE;
+	else
+		msg.type = MIPI_DSI_PPS_LONG_WRITE;
+
+	return  mipi_dsi_device_transfer(dsi, &msg);
+}
+EXPORT_SYMBOL(mipi_dsi_dsc_pps_write_buffer);
+
+/**
  * mipi_dsi_dcs_write() - send DCS write command
  * @dsi: DSI peripheral device
  * @cmd: DCS command
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..2aa5120 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -197,7 +197,9 @@ ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi,
 ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,
 			   const void *data, size_t len);
 ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,
-			  size_t len);
+				size_t len);
+ssize_t mipi_dsi_dsc_pps_write_buffer(struct mipi_dsi_device *dsi,
+				const void *data, size_t len);
 int mipi_dsi_dcs_nop(struct mipi_dsi_device *dsi);
 int mipi_dsi_dcs_soft_reset(struct mipi_dsi_device *dsi);
 int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode);
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index ddcc8ca..880e6e6 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -38,6 +38,9 @@ enum {
 
 	MIPI_DSI_DCS_READ				= 0x06,
 
+	MIPI_DSI_DCS_COMPRESSION_MODE                   = 0x07,
+	MIPI_DSI_PPS_LONG_WRITE                         = 0x0A,
+
 	MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE		= 0x37,
 
 	MIPI_DSI_END_OF_TRANSMISSION			= 0x08,
-- 
1.7.9.5

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[RFC 8/8] drm/i915/bxt: Send PPS packet and compression mode command packet

[vikas.korjani]

From: vkorjani <vikas.korjani@intel.com>

This patch adds code to send pps long packet and compression mode
command packet.

Signed-off-by: vkorjani <vikas.korjani@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f893d37..813b126 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -292,6 +292,15 @@ static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
 	}
 }
 
+static void send_dsc_pps_block(struct intel_dsi *intel_dsi)
+{
+	u8 *data;
+
+	mipi_dsi_dsc_pps_write_buffer(dsi_device, NULL, 0);
+	data = (u8 *)&intel_dsi->pps_data;
+	mipi_dsi_dsc_pps_write_buffer(dsi_device, data, 128);
+}
+
 static int vbt_panel_prepare(struct drm_panel *panel)
 {
 	struct vbt_panel *vbt_panel = to_vbt_panel(panel);
@@ -306,6 +315,9 @@ static int vbt_panel_prepare(struct drm_panel *panel)
 	sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
 	generic_exec_sequence(intel_dsi, sequence);
 
+	if (intel_dsi->dsc_enable)
+		send_dsc_pps_block(intel_dsi);
+
 	return 0;
 }
 
-- 
1.7.9.5

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Re: [RFC 3/8] drm/i915/bxt: Init PPS, Calculate DSI frequency and DPHY parameters for DSC

[Daniel Vetter]

On Wed, Aug 12, 2015 at 03:23:48PM +0530, vikas.korjani@intel.com wrote:
> From: vkorjani <vikas.korjani@intel.com>
> 
> This patch adds code to initialize Picture  Parameter set (PPS)
> data structure for DSC.
> DSC is enabled than the bitrate should be calculated using the
> formula pixel_clock * bits_per_pixel / lane_count, where
> bits_per_pixel can be 8bpp, 10bpp, 12bpp.
> value of bits_per_pixel is available in step of 1/16 in
> pps date structure.
> DPHY parameters are computed based on data rate calculated
> as per bits_per_pixel provided in pps data structure.
> 
> Signed-off-by: vkorjani <vikas.korjani@intel.com>
> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.h           |    5 +++++
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   11 +++++++++++
>  drivers/gpu/drm/i915/intel_dsi_pll.c       |   24 ++++++++++++++++--------
>  3 files changed, 32 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 24fc550..699f995 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -96,6 +96,11 @@ struct intel_dsi {
>  	u16 panel_on_delay;
>  	u16 panel_off_delay;
>  	u16 panel_pwr_cycle_delay;
> +
> +	/*DSC Support */
> +	u8 dsc_enable;
> +	struct vesa_dsc_pps_data pps_data;
> +	u8 dsc_bpp;
>  };
>  
>  struct intel_dsi_host {
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index a5e99ac..f893d37 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -413,6 +413,17 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  		bits_per_pixel = 18;
>  	else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
>  		bits_per_pixel = 16;
> +	else if (intel_dsi->pixel_format == VID_MODE_FORMAT_COMPRESSED &&
> +			dev_priv->vbt.dsc_param.dsc_support) {
> +		intel_dsi->dsc_enable = true;
> +		intel_dsi->dsc_bpp =
> +			(intel_dsi->pps_data.bits_per_pixel / 16);
> +		bits_per_pixel = intel_dsi->dsc_bpp;
> +		intel_dsi->pps_data =
> +			dev_priv->vbt.dsc_param.pps_data;
> +		/*TODO If PPS not available in VBT compute PPS
> +		 * from capablity parameter set in vbt */

We don't seem to feed back the dsi bits_per_pixel information into our
computation of pipe_config->pipe_bpp. We probably need to fix that to
actually be able to drive the higher bpc modes ...

Wiring this up correctly should probably be a prep patch.

Also do we have to compute bpp differently for dsc? Can't we just store
bits_per_pixel somewhere?
-Daniel

> +	}
>  
>  	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
>  	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index b647f13..38c9433 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -143,10 +143,17 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode,
>  #else
>  
>  /* Get DSI clock from pixel clock */
> -static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
> +static u32 dsi_clk_from_pclk(struct intel_encoder *encoder,
> +			u32 pclk, int pixel_format, int lane_count)
>  {
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u32 dsi_clk_khz;
> -	u32 bpp = dsi_pixel_format_bpp(pixel_format);
> +	u32 bpp;
> +
> +	if (intel_dsi->dsc_enable)
> +		bpp =  intel_dsi->dsc_bpp;
> +	else
> +		bpp = dsi_pixel_format_bpp(pixel_format);
>  
>  	/* DSI data rate = pixel clock * bits per pixel / lane count
>  	   pixel clock is converted from KHz to Hz */
> @@ -223,8 +230,8 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>  	struct dsi_mnp dsi_mnp;
>  	u32 dsi_clk;
>  
> -	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> -				    intel_dsi->lane_count);
> +	dsi_clk = dsi_clk_from_pclk(encoder, intel_dsi->pclk,
> +			intel_dsi->pixel_format, intel_dsi->lane_count);
>  
>  	ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
>  	if (ret) {
> @@ -410,8 +417,9 @@ u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
>  
>  	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
>  
> -	/* pixel_format and pipe_bpp should agree */
> -	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
> +	/* pixel_format and pipe_bpp should agree if DSC is not enabled */
> +	if (!intel_dsi->dsc_enable)
> +		assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
>  
>  	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
>  
> @@ -475,8 +483,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
>  	u32 dsi_clk;
>  	u32 val;
>  
> -	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> -			intel_dsi->lane_count);
> +	dsi_clk = dsi_clk_from_pclk(encoder, intel_dsi->pclk,
> +			intel_dsi->pixel_format, intel_dsi->lane_count);
>  
>  	/*
>  	 * From clock diagram, to get PLL ratio divider, divide double of DSI
> -- 
> 1.7.9.5
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [RFC 0/8] *** DSC Inital Design RFC ***

[Daniel Vetter]

jn Wed, Aug 12, 2015 at 03:23:45PM +0530, vikas.korjani@intel.com wrote:
> From: vkorjani <vikas.korjani@intel.com>
> 
> s RFC is for feature Display Stream Compression (DSC) for BXT,
> It is a VESA defined standard to compress and decompress image in display
> streams in a link independent manner. Some of the basic requirements of
> the standard are to support higher resolution on a given display link
> with fewer lanes or lower rate.
> 
> DSC is architected to work in current Intel Display Engine design
> without modification how current display pipeline works. DSC hardware
> as per HAS is in b/n port and MIPI DSI controller. so most of the
> changes are at port level.
> 
> At begining of frame display can start sending valid pixels to DSC
> at normal rate, DSC start compressing this image according to
> pps parameters programmed already to 8bpp, 10bpp, 12bpp.
> 
> /*This bitstream is temprory stored in output buffer and sent as byte
> stream to DSI controller as soon as it is valid.
> */

Where exactly is that bistream stored? In some on-chip buffer which is
hidden from us, or do we need to allocate some memory for this? I din't
spot anything of the latter form ...
-Daniel

> Following are the set of patches as per  initial design in HLD, one
> can refer DSC HLD if more details about the changes is required.
> 
> Tested these patches on fulsim simulation enviornment.
> 
> 
> vkorjani (8):
>   drm/915/bxt: Adding DSC VBT parameter and PPS structures
>   drm/i915/bxt: Adding registers to support DSC
>   drm/i915/bxt: Init PPS, Calculate DSI frequency and DPHY parameters
>     for DSC
>   drm/i915/bxt: MIPI DSI Register Programming for DSC
>   drm/i915/bxt: Program MIPI_DPI_RESOLUTION for DSC
>   drm/i915/bxt: Enable/Disable DSC and programme PPS.
>   drm: Add support for pps and compression mode command packet
>   drm/i915/bxt: Send PPS packet and compression mode command packet
> 
>  drivers/gpu/drm/drm_mipi_dsi.c             |   29 +++
>  drivers/gpu/drm/i915/i915_drv.h            |    2 +
>  drivers/gpu/drm/i915/i915_reg.h            |  126 +++++++++++++
>  drivers/gpu/drm/i915/intel_bios.h          |   74 ++++++++
>  drivers/gpu/drm/i915/intel_dsi.c           |  274 ++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_dsi.h           |    5 +
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   23 +++
>  drivers/gpu/drm/i915/intel_dsi_pll.c       |   24 ++-
>  include/drm/drm_mipi_dsi.h                 |    4 +-
>  include/video/mipi_display.h               |    3 +
>  10 files changed, 539 insertions(+), 25 deletions(-)
> 
> -- 
> 1.7.9.5
> 
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [RFC 3/8] drm/i915/bxt: Init PPS, Calculate DSI frequency and DPHY parameters for DSC

[vkorjani]

On Wednesday 12 August 2015 07:05 PM, Daniel Vetter wrote:
> On Wed, Aug 12, 2015 at 03:23:48PM +0530, vikas.korjani@intel.com wrote:
>> From: vkorjani <vikas.korjani@intel.com>
>>
>> This patch adds code to initialize Picture  Parameter set (PPS)
>> data structure for DSC.
>> DSC is enabled than the bitrate should be calculated using the
>> formula pixel_clock * bits_per_pixel / lane_count, where
>> bits_per_pixel can be 8bpp, 10bpp, 12bpp.
>> value of bits_per_pixel is available in step of 1/16 in
>> pps date structure.
>> DPHY parameters are computed based on data rate calculated
>> as per bits_per_pixel provided in pps data structure.
>>
>> Signed-off-by: vkorjani <vikas.korjani@intel.com>
>> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi.h           |    5 +++++
>>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   11 +++++++++++
>>   drivers/gpu/drm/i915/intel_dsi_pll.c       |   24 ++++++++++++++++--------
>>   3 files changed, 32 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index 24fc550..699f995 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -96,6 +96,11 @@ struct intel_dsi {
>>   	u16 panel_on_delay;
>>   	u16 panel_off_delay;
>>   	u16 panel_pwr_cycle_delay;
>> +
>> +	/*DSC Support */
>> +	u8 dsc_enable;
>> +	struct vesa_dsc_pps_data pps_data;
>> +	u8 dsc_bpp;
>>   };
>>   
>>   struct intel_dsi_host {
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index a5e99ac..f893d37 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -413,6 +413,17 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>   		bits_per_pixel = 18;
>>   	else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
>>   		bits_per_pixel = 16;
>> +	else if (intel_dsi->pixel_format == VID_MODE_FORMAT_COMPRESSED &&
>> +			dev_priv->vbt.dsc_param.dsc_support) {
>> +		intel_dsi->dsc_enable = true;
>> +		intel_dsi->dsc_bpp =
>> +			(intel_dsi->pps_data.bits_per_pixel / 16);
>> +		bits_per_pixel = intel_dsi->dsc_bpp;
>> +		intel_dsi->pps_data =
>> +			dev_priv->vbt.dsc_param.pps_data;
>> +		/*TODO If PPS not available in VBT compute PPS
>> +		 * from capablity parameter set in vbt */
> We don't seem to feed back the dsi bits_per_pixel information into our
> computation of pipe_config->pipe_bpp. We probably need to fix that to
> actually be able to drive the higher bpc modes ...
>
> Wiring this up correctly should probably be a prep patch.
Yes will fix this.
>
> Also do we have to compute bpp differently for dsc? Can't we just store
> bits_per_pixel somewhere?
> -Daniel
intel_dsi->dsc_bpp stores target bpp after compression.
We can store orginal bpp in intel_dsi->dsi_bpp, some thing similar
is done in this patch

http://lists.freedesktop.org/archives/intel-gfx/2015-May/067627.html
which is still under review.

>
>> +	}
>>   
>>   	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
>>   	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index b647f13..38c9433 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -143,10 +143,17 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode,
>>   #else
>>   
>>   /* Get DSI clock from pixel clock */
>> -static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
>> +static u32 dsi_clk_from_pclk(struct intel_encoder *encoder,
>> +			u32 pclk, int pixel_format, int lane_count)
>>   {
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>   	u32 dsi_clk_khz;
>> -	u32 bpp = dsi_pixel_format_bpp(pixel_format);
>> +	u32 bpp;
>> +
>> +	if (intel_dsi->dsc_enable)
>> +		bpp =  intel_dsi->dsc_bpp;
>> +	else
>> +		bpp = dsi_pixel_format_bpp(pixel_format);
>>   
>>   	/* DSI data rate = pixel clock * bits per pixel / lane count
>>   	   pixel clock is converted from KHz to Hz */
>> @@ -223,8 +230,8 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>>   	struct dsi_mnp dsi_mnp;
>>   	u32 dsi_clk;
>>   
>> -	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
>> -				    intel_dsi->lane_count);
>> +	dsi_clk = dsi_clk_from_pclk(encoder, intel_dsi->pclk,
>> +			intel_dsi->pixel_format, intel_dsi->lane_count);
>>   
>>   	ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);
>>   	if (ret) {
>> @@ -410,8 +417,9 @@ u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
>>   
>>   	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
>>   
>> -	/* pixel_format and pipe_bpp should agree */
>> -	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
>> +	/* pixel_format and pipe_bpp should agree if DSC is not enabled */
>> +	if (!intel_dsi->dsc_enable)
>> +		assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
>>   
>>   	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
>>   
>> @@ -475,8 +483,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
>>   	u32 dsi_clk;
>>   	u32 val;
>>   
>> -	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
>> -			intel_dsi->lane_count);
>> +	dsi_clk = dsi_clk_from_pclk(encoder, intel_dsi->pclk,
>> +			intel_dsi->pixel_format, intel_dsi->lane_count);
>>   
>>   	/*
>>   	 * From clock diagram, to get PLL ratio divider, divide double of DSI
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [RFC 0/8] *** DSC Inital Design RFC ***

[vkorjani]

On Wednesday 12 August 2015 07:09 PM, Daniel Vetter wrote:
> jn Wed, Aug 12, 2015 at 03:23:45PM +0530, vikas.korjani@intel.com wrote:
>> From: vkorjani <vikas.korjani@intel.com>
>>
>> s RFC is for feature Display Stream Compression (DSC) for BXT,
>> It is a VESA defined standard to compress and decompress image in display
>> streams in a link independent manner. Some of the basic requirements of
>> the standard are to support higher resolution on a given display link
>> with fewer lanes or lower rate.
>>
>> DSC is architected to work in current Intel Display Engine design
>> without modification how current display pipeline works. DSC hardware
>> as per HAS is in b/n port and MIPI DSI controller. so most of the
>> changes are at port level.
>>
>> At begining of frame display can start sending valid pixels to DSC
>> at normal rate, DSC start compressing this image according to
>> pps parameters programmed already to 8bpp, 10bpp, 12bpp.
>>
>> /*This bitstream is temprory stored in output buffer and sent as byte
>> stream to DSI controller as soon as it is valid.
>> */
> Where exactly is that bistream stored? In some on-chip buffer which is
> hidden from us, or do we need to allocate some memory for this? I din't
> spot anything of the latter form ...
> -Daniel
Yes this is a on-chip buffer.
>
>> Following are the set of patches as per  initial design in HLD, one
>> can refer DSC HLD if more details about the changes is required.
>>
>> Tested these patches on fulsim simulation enviornment.
>>
>>
>> vkorjani (8):
>>    drm/915/bxt: Adding DSC VBT parameter and PPS structures
>>    drm/i915/bxt: Adding registers to support DSC
>>    drm/i915/bxt: Init PPS, Calculate DSI frequency and DPHY parameters
>>      for DSC
>>    drm/i915/bxt: MIPI DSI Register Programming for DSC
>>    drm/i915/bxt: Program MIPI_DPI_RESOLUTION for DSC
>>    drm/i915/bxt: Enable/Disable DSC and programme PPS.
>>    drm: Add support for pps and compression mode command packet
>>    drm/i915/bxt: Send PPS packet and compression mode command packet
>>
>>   drivers/gpu/drm/drm_mipi_dsi.c             |   29 +++
>>   drivers/gpu/drm/i915/i915_drv.h            |    2 +
>>   drivers/gpu/drm/i915/i915_reg.h            |  126 +++++++++++++
>>   drivers/gpu/drm/i915/intel_bios.h          |   74 ++++++++
>>   drivers/gpu/drm/i915/intel_dsi.c           |  274 ++++++++++++++++++++++++++--
>>   drivers/gpu/drm/i915/intel_dsi.h           |    5 +
>>   drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   23 +++
>>   drivers/gpu/drm/i915/intel_dsi_pll.c       |   24 ++-
>>   include/drm/drm_mipi_dsi.h                 |    4 +-
>>   include/video/mipi_display.h               |    3 +
>>   10 files changed, 539 insertions(+), 25 deletions(-)
>>
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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