From: Sunil Kamath <sunil.kamath@intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [DMC_BUGFIX_SKL_V2 1/5] drm/i915/skl: Added a check for the hardware status of csr fw before loading.
Date: Mon, 07 Sep 2015 16:34:30 +0530 [thread overview]
Message-ID: <55ED6F3E.7030205@intel.com> (raw)
In-Reply-To: <1440533169-32265-2-git-send-email-animesh.manna@intel.com>
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On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote:
> Dmc will restore the csr program except DC9, cold boot,
> warm reset, PCI function level reset, and hibernate/suspend.
>
> intel_csr_load_program() function is used to load the firmware
> data from kernel memory to csr address space.
>
> All values of csr address space will be zero if it got reset and
> the first byte of csr program is always a non-zero if firmware
> is loaded successfuly. Based on hardware status will load the
> firmware.
>
> Without this condition check if we overwrite the firmware data the
> counters exposed for dc5/dc6 (help for debugging) will be nullified.
>
> v1: Initial version.
>
> v2: Based on review comments from Daniel,
> - Added a check to know hardware status and load the firmware if not loaded.
>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index ba1ae03..682cc26 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -252,6 +252,15 @@ void intel_csr_load_program(struct drm_device *dev)
> return;
> }
>
> + /*
> + * Dmc will restore the csr the program except DC9, cold boot,
> + * warm reset, PCI function level reset, and hibernate/suspend.
> + * This condition will help to check if csr address space is reset/
> + * not loaded.
> + */
> + if (I915_READ(CSR_PROGRAM_BASE))
> + return;
> +
> mutex_lock(&dev_priv->csr_lock);
> fw_size = dev_priv->csr.dmc_fw_size;
> for (i = 0; i < fw_size; i++)
Valid fix and patch is ready for merge now.
Reviewed-by: A.Sunil Kamath <sunil.kamath@intel.com>
<mailto:sunil.kamath@intel.com>
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next prev parent reply other threads:[~2015-09-07 11:04 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-25 20:06 [DMC_BUGFIX_SKL_V2 0/5] pc10 entry fixes for skl Animesh Manna
2015-08-25 20:06 ` [DMC_BUGFIX_SKL_V2 1/5] drm/i915/skl: Added a check for the hardware status of csr fw before loading Animesh Manna
2015-08-26 13:10 ` Daniel Vetter
2015-08-26 14:10 ` Animesh Manna
2015-09-02 8:54 ` Daniel Vetter
2015-09-09 20:28 ` Animesh Manna
2015-09-10 14:45 ` Daniel Vetter
2015-09-10 19:05 ` Animesh Manna
2015-09-10 19:06 ` Animesh Manna
2015-09-14 7:46 ` Daniel Vetter
2015-09-16 19:23 ` Animesh Manna
2015-09-23 7:57 ` Daniel Vetter
2015-09-23 16:27 ` Daniel Vetter
2015-09-23 16:28 ` Daniel Vetter
2015-09-23 17:17 ` Daniel Vetter
2015-09-23 20:49 ` Rafael J. Wysocki
2015-09-28 6:52 ` Daniel Vetter
2015-09-28 23:54 ` Rafael J. Wysocki
2015-09-29 8:51 ` Daniel Vetter
2015-09-30 0:50 ` Rafael J. Wysocki
2015-09-30 12:14 ` Daniel Vetter
2015-09-30 23:34 ` Rafael J. Wysocki
2015-09-07 11:04 ` Sunil Kamath [this message]
2015-09-07 16:22 ` Daniel Vetter
2015-09-09 20:33 ` Animesh Manna
2015-09-28 7:03 ` Daniel Vetter
2015-08-25 20:06 ` [DMC_BUGFIX_SKL_V2 2/5] drm/i915/skl Remove the call for csr uninitialization from suspend path Animesh Manna
2015-09-07 11:05 ` Sunil Kamath
2015-08-25 20:06 ` [DMC_BUGFIX_SKL_V2 3/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow Animesh Manna
2015-09-07 11:06 ` Sunil Kamath
2015-09-28 7:21 ` Daniel Vetter
2015-09-28 18:49 ` Hindman, Gavin
2015-09-29 5:31 ` [DMC_BUGFIX_V3] " Animesh Manna
2015-10-16 12:22 ` Imre Deak
2015-10-19 9:26 ` Daniel Vetter
2015-09-29 5:38 ` [DMC_BUGFIX_SKL_V2 3/5] " Animesh Manna
2015-09-29 9:01 ` Daniel Vetter
2015-09-29 12:35 ` Patrik Jakobsson
2015-09-29 13:01 ` Daniel Vetter
2015-09-29 13:23 ` Ville Syrjälä
2015-09-29 14:00 ` Daniel Vetter
2015-08-25 20:06 ` [DMC_BUGFIX_SKL_V2 4/5] drm/i915/skl: Do not disable cdclk PLL if csr firmware is present Animesh Manna
2015-08-26 13:11 ` Daniel Vetter
2015-08-26 14:31 ` Animesh Manna
2015-08-31 1:03 ` Hindman, Gavin
2015-09-02 8:58 ` Daniel Vetter
2015-09-07 11:07 ` Sunil Kamath
2015-08-25 20:06 ` [DMC_BUGFIX_SKL_V2 5/5] drm/i915/skl: Block disable call for pw1 if dmc " Animesh Manna
2015-09-07 11:09 ` Sunil Kamath
2015-09-28 7:24 ` Daniel Vetter
2015-10-09 13:58 ` [DMC_BUGFIX_SKL_V2 0/5] pc10 entry fixes for skl Imre Deak
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