From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sunil Kamath Subject: Re: [DMC_BUGFIX_SKL_V2 4/5] drm/i915/skl: Do not disable cdclk PLL if csr firmware is present Date: Mon, 07 Sep 2015 16:37:10 +0530 Message-ID: <55ED6FDE.1070104@intel.com> References: <1440533169-32265-1-git-send-email-animesh.manna@intel.com> <1440533169-32265-5-git-send-email-animesh.manna@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0632871386==" Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 889466E283 for ; Mon, 7 Sep 2015 04:07:13 -0700 (PDT) In-Reply-To: <1440533169-32265-5-git-send-email-animesh.manna@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Animesh Manna Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, Rajneesh Bhardwaj List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0632871386== Content-Type: multipart/alternative; boundary="------------030604010505000300050208" This is a multi-part message in MIME format. --------------030604010505000300050208 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote: > While display engine entering into low power state no need to disable > cdclk pll as CSR firmware of dmc will take care. If pll is already > enabled firmware execution sequence will be blocked. This is one > of the criteria for dmc to work properly. > > v1: Initial version. > > v2: Based on review comment from Daniel added code commnent. > > Cc: Daniel Vetter > Cc: Damien Lespiau > Cc: Imre Deak > Cc: Sunil Kamath > Signed-off-by: Animesh Manna > Signed-off-bt: Vathsala Nagaraju > Signed-off-by: Rajneesh Bhardwaj > --- > drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index f604ce1..b6bef20 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5687,10 +5687,16 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv) > if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) > DRM_ERROR("DBuf power disable timeout\n"); > > - /* disable DPLL0 */ > - I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); > - if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) > - DRM_ERROR("Couldn't disable DPLL0\n"); > + /* > + * DMC assumes ownership of LCPLL and will get confused if we touch it. > + */ > + if (dev_priv->csr.dmc_payload) { > + /* disable DPLL0 */ > + I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & > + ~LCPLL_PLL_ENABLE); > + if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) > + DRM_ERROR("Couldn't disable DPLL0\n"); > + } > > intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); > } Valid fix and patch is ready for merge now. Reviewed-by: A.Sunil Kamath --------------030604010505000300050208 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit
On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote:
While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be blocked. This is one
of the criteria for dmc to work properly.

v1: Initial version.

v2: Based on review comment from Daniel added code commnent.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-bt: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f604ce1..b6bef20 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5687,10 +5687,16 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
 		DRM_ERROR("DBuf power disable timeout\n");
 
-	/* disable DPLL0 */
-	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
-	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
-		DRM_ERROR("Couldn't disable DPLL0\n");
+	/*
+	 * DMC assumes ownership of LCPLL and will get confused if we touch it.
+	 */
+	if (dev_priv->csr.dmc_payload) {
+		/* disable DPLL0 */
+		I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
+					~LCPLL_PLL_ENABLE);
+		if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
+			DRM_ERROR("Couldn't disable DPLL0\n");
+	}
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }

Valid fix and patch is ready for merge now.

Reviewed-by: A.Sunil Kamath <sunil.kamath@intel.com>

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