From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sunil Kamath Subject: Re: [DMC_BUGFIX_SKL_V2 5/5] drm/i915/skl: Block disable call for pw1 if dmc firmware is present. Date: Mon, 07 Sep 2015 16:39:19 +0530 Message-ID: <55ED705F.8070505@intel.com> References: <1440533169-32265-1-git-send-email-animesh.manna@intel.com> <1440533169-32265-6-git-send-email-animesh.manna@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0729160831==" Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id C5DF66E309 for ; Mon, 7 Sep 2015 04:09:25 -0700 (PDT) In-Reply-To: <1440533169-32265-6-git-send-email-animesh.manna@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Animesh Manna Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0729160831== Content-Type: multipart/alternative; boundary="------------070301050307090905030508" This is a multi-part message in MIME format. --------------070301050307090905030508 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote: > Another interesting criteria to work dmc as expected is pw1 to be > enabled by driver and dmc will shut it off in its execution > sequence. If already disabled by driver dmc will get confuse and > behave differently than expected found during pc10 entry issue > for skl. > > So berfore we disable power-well 1, added check if dmc firmware is > present and driver will not disable power well 1, but for any reason > if firmware is not present of failed to load we can shut off the > power well 1 which will save some power. > > As skl is currently fully dependent on dmc to go in lowest possible > power state (dc6) but the same is not applicable for bxt. Display > engine can enter into dc9 without dmc, hence unblocking disable call. > > v1: Initial version. > > v2: Rebased as per current patch series. > > Cc: Daniel Vetter > Cc: Damien Lespiau > Cc: Imre Deak > Cc: Sunil Kamath > Signed-off-by: Animesh Manna > Signed-off-by: Vathsala Nagaraju > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 23a3aa3..340f386 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -652,9 +652,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, > } > } else { > if (enable_requested) { > - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); > - POSTING_READ(HSW_PWR_WELL_DRIVER); > - DRM_DEBUG_KMS("Disabling %s\n", power_well->name); > + if (IS_SKYLAKE(dev) && > + (power_well->data == SKL_DISP_PW_1) && > + (intel_csr_load_status_get(dev_priv) == FW_LOADED)) > + DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n"); > + else { > + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); > + POSTING_READ(HSW_PWR_WELL_DRIVER); > + DRM_DEBUG_KMS("Disabling %s\n", power_well->name); > + } > > if (GEN9_ENABLE_DC5(dev) && > power_well->data == SKL_DISP_PW_2) { Valid fix and patch is ready for merge now. Reviewed-by: A.Sunil Kamath --------------070301050307090905030508 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit
On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote:
Another interesting criteria to work dmc as expected is pw1 to be
enabled by driver and dmc will shut it off in its execution
sequence. If already disabled by driver dmc will get confuse and
behave differently than expected found during pc10 entry issue
for skl.

So berfore we disable power-well 1, added check if dmc firmware is
present and driver will not disable power well 1, but for any reason
if firmware is not present of failed to load we can shut off the
power well 1 which will save some power.

As skl is currently fully dependent on dmc to go in lowest possible
power state (dc6) but the same is not applicable for bxt. Display
engine can enter into dc9 without dmc, hence unblocking disable call.

v1: Initial version.

v2: Rebased as per current patch series.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 23a3aa3..340f386 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -652,9 +652,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 		}
 	} else {
 		if (enable_requested) {
-			I915_WRITE(HSW_PWR_WELL_DRIVER,	tmp & ~req_mask);
-			POSTING_READ(HSW_PWR_WELL_DRIVER);
-			DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
+			if (IS_SKYLAKE(dev) &&
+				(power_well->data == SKL_DISP_PW_1) &&
+				(intel_csr_load_status_get(dev_priv) == FW_LOADED))
+				DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
+			else {
+				I915_WRITE(HSW_PWR_WELL_DRIVER,	tmp & ~req_mask);
+				POSTING_READ(HSW_PWR_WELL_DRIVER);
+				DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
+			}
 
 			if (GEN9_ENABLE_DC5(dev) &&
 				power_well->data == SKL_DISP_PW_2) {

Valid fix and patch is ready for merge now.

Reviewed-by: A.Sunil Kamath <sunil.kamath@intel.com>

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