[PATCH 1/4] drm/i915/bxt: Enable WaVSRefCountFullforceMissDisable

[PATCH 1/4] drm/i915/bxt: Enable WaVSRefCountFullforceMissDisable

[Nick Hoath]

From: Rafael Barbalho <rafael.barbalho@intel.com>

Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..d635d0a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -59,6 +59,11 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 	/* WaEnableLbsSlaRetryTimerDecrement:skl */
 	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+
+	/* WaVSRefCountFullforceMissDisable:skl,bxt */
+	I915_WRITE(GEN7_FF_THREAD_MODE,
+		   I915_READ(GEN7_FF_THREAD_MODE) &
+		   ~(GEN7_FF_VS_REF_CNT_FFME));
 }
 
 static void skl_init_clock_gating(struct drm_device *dev)
-- 
2.1.1

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[PATCH 2/4] drm/i915/bxt: Enable WaDSRefCountFullforceMissDisable

[Nick Hoath]

From: Rafael Barbalho <rafael.barbalho@intel.com>

Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d635d0a..f29e575 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -60,10 +60,13 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 
-	/* WaVSRefCountFullforceMissDisable:skl,bxt */
+	/*
+	 * WaVSRefCountFullforceMissDisable:skl,bxt
+	 * WaDSRefCountFullforceMissDisable:skl,bxt
+	 */
 	I915_WRITE(GEN7_FF_THREAD_MODE,
 		   I915_READ(GEN7_FF_THREAD_MODE) &
-		   ~(GEN7_FF_VS_REF_CNT_FFME));
+		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
 }
 
 static void skl_init_clock_gating(struct drm_device *dev)
-- 
2.1.1

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[PATCH 3/4] drm/i915/bxt: Enable WaOCLCoherentLineFlush

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Cc: Rafael Barbalho <rafael.barbalho@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b9f6b8c..115911a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5807,6 +5807,7 @@ enum skl_disp_power_wells {
 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
 
 #define GEN7_L3SQCREG4				0xb034
+#define  GEN8_PIPELINE_FLUSH_COHERENT_LINES	(1<<21)
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
 
 #define GEN8_L3SQCREG4				0xb118
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f29e575..26ef146 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -67,6 +67,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN7_FF_THREAD_MODE,
 		   I915_READ(GEN7_FF_THREAD_MODE) &
 		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
+
+	/* WaOCLCoherentLineFlush:skl,bxt */
+	I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+			GEN8_PIPELINE_FLUSH_COHERENT_LINES);
 }
 
 static void skl_init_clock_gating(struct drm_device *dev)
-- 
2.1.1

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[PATCH 4/4] drm/i915/bxt: Clean up bxt_init_clock_gating

[Nick Hoath]

Add stepping check for A0 workarounds, and remove the associated
FIXME tags.
Split out unrelated WAs for later condition checking.

v2: Fixed format (PeterL)
v3: Corrected stepping check for WaDisableSDEUnitClockGating
    - Ignoring comment, following hardware spec instead. (ChrisH)
    Added description for TILECTL setting (JonB)

Cc: Peter Lawthers <peter.lawthers@intel.com>
Cc: Chris Harris <chris.harris@intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 26ef146..86a4ced 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -115,18 +115,24 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 
 	gen9_init_clock_gating(dev);
 
+	/* WaDisableSDEUnitClockGating:bxt */
+	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
 	/*
 	 * FIXME:
-	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
 	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 	 */
-	 /* WaDisableSDEUnitClockGating:bxt */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
 		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 
-	/* FIXME: apply on A0 only */
-	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
+	if (INTEL_REVID(dev) == BXT_REVID_A0) {
+		/*
+		 * Hardware specification requires this bit to be
+		 * set to 1 for A0
+		 */
+		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
+	}
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
-- 
2.1.1

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Re: [PATCH 1/4] drm/i915/bxt: Enable WaVSRefCountFullforceMissDisable

[Mika Kuoppala]

Hi,

Nick Hoath <nicholas.hoath@intel.com> writes:

> From: Rafael Barbalho <rafael.barbalho@intel.com>
>
> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 32ff034..d635d0a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -59,6 +59,11 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>  	/* WaEnableLbsSlaRetryTimerDecrement:skl */
>  	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
>  		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
> +
> +	/* WaVSRefCountFullforceMissDisable:skl,bxt */
> +	I915_WRITE(GEN7_FF_THREAD_MODE,
> +		   I915_READ(GEN7_FF_THREAD_MODE) &
> +		   ~(GEN7_FF_VS_REF_CNT_FFME));
>  }
>  

This bit 19 seems to be about Tesselation DOP gating disable
with gen9+ onwards. And with that workaroundname, the applicability
should be hsw,bdw. I am confused.

-Mika


>  static void skl_init_clock_gating(struct drm_device *dev)
> -- 
> 2.1.1
>
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Re: [PATCH 1/4] drm/i915/bxt: Enable WaVSRefCountFullforceMissDisable

[Nick Hoath]

On 29/06/2015 15:08, Mika Kuoppala wrote:
>
> Hi,
>
> Nick Hoath <nicholas.hoath@intel.com> writes:
>
>> From: Rafael Barbalho <rafael.barbalho@intel.com>
>>
>> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
>> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 32ff034..d635d0a 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -59,6 +59,11 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>>   	/* WaEnableLbsSlaRetryTimerDecrement:skl */
>>   	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
>>   		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
>> +
>> +	/* WaVSRefCountFullforceMissDisable:skl,bxt */
>> +	I915_WRITE(GEN7_FF_THREAD_MODE,
>> +		   I915_READ(GEN7_FF_THREAD_MODE) &
>> +		   ~(GEN7_FF_VS_REF_CNT_FFME));
>>   }
>>
>
> This bit 19 seems to be about Tesselation DOP gating disable
> with gen9+ onwards. And with that workaroundname, the applicability
> should be hsw,bdw. I am confused.
>

The specs say these WAs are required for GEN9+, BDW & HSW. So I'm
at a loss to see the confusion.

> -Mika
>
>
>>   static void skl_init_clock_gating(struct drm_device *dev)
>> --
>> 2.1.1
>>
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 4/4] drm/i915/bxt: Clean up bxt_init_clock_gating

[Mika Kuoppala]

Nick Hoath <nicholas.hoath@intel.com> writes:

> Add stepping check for A0 workarounds, and remove the associated
> FIXME tags.
> Split out unrelated WAs for later condition checking.
>
> v2: Fixed format (PeterL)
> v3: Corrected stepping check for WaDisableSDEUnitClockGating
>     - Ignoring comment, following hardware spec instead. (ChrisH)
>     Added description for TILECTL setting (JonB)
>
> Cc: Peter Lawthers <peter.lawthers@intel.com>
> Cc: Chris Harris <chris.harris@intel.com>
> Cc: Jon Bloomfield <jon.bloomfield@intel.com>
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 26ef146..86a4ced 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -115,18 +115,24 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>  
>  	gen9_init_clock_gating(dev);
>  
> +	/* WaDisableSDEUnitClockGating:bxt */
> +	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> +		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
>  	/*
>  	 * FIXME:
> -	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
>  	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
>  	 */
> -	 /* WaDisableSDEUnitClockGating:bxt */
>  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
>  		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>  

I guess you decided not to combine the writes due to FIXME.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>


> -	/* FIXME: apply on A0 only */
> -	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
> +	if (INTEL_REVID(dev) == BXT_REVID_A0) {
> +		/*
> +		 * Hardware specification requires this bit to be
> +		 * set to 1 for A0
> +		 */
> +		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
> +	}
>  }
>  
>  static void i915_pineview_get_mem_freq(struct drm_device *dev)
> -- 
> 2.1.1
>
> _______________________________________________
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Re: [PATCH 1/4] drm/i915/bxt: Enable WaVSRefCountFullforceMissDisable

[Mika Kuoppala]

Nick Hoath <nicholas.hoath@intel.com> writes:

> On 29/06/2015 15:08, Mika Kuoppala wrote:
>>
>> Hi,
>>
>> Nick Hoath <nicholas.hoath@intel.com> writes:
>>
>>> From: Rafael Barbalho <rafael.barbalho@intel.com>
>>>
>>> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
>>> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>>>   1 file changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 32ff034..d635d0a 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -59,6 +59,11 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>>>   	/* WaEnableLbsSlaRetryTimerDecrement:skl */
>>>   	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
>>>   		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
>>> +
>>> +	/* WaVSRefCountFullforceMissDisable:skl,bxt */
>>> +	I915_WRITE(GEN7_FF_THREAD_MODE,
>>> +		   I915_READ(GEN7_FF_THREAD_MODE) &
>>> +		   ~(GEN7_FF_VS_REF_CNT_FFME));
>>>   }
>>>
>>
>> This bit 19 seems to be about Tesselation DOP gating disable
>> with gen9+ onwards. And with that workaroundname, the applicability
>> should be hsw,bdw. I am confused.
>>
>
> The specs say these WAs are required for GEN9+, BDW & HSW. So I'm
> at a loss to see the confusion.
>

I was wrong about the bit 19. It is bit 15. But the issue remains,
bit 15 is not about VS reference counts but TDS bypassing on SKL.
The meaning of bitsfield have changed on skl. So we need to hunt
down where the refcount disable has been moved?

-Mika


>> -Mika
>>
>>
>>>   static void skl_init_clock_gating(struct drm_device *dev)
>>> --
>>> 2.1.1
>>>
>>> _______________________________________________
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>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 4/4] drm/i915/bxt: Clean up bxt_init_clock_gating

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6665
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  302/302              302/302
SNB                                  312/316              312/316
IVB                                  343/343              343/343
BYT                 -2              287/287              285/287
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*BYT  igt@gem_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
*BYT  igt@gem_partial_pwrite_pread@reads-display      PASS(1)      FAIL(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 4/4] drm/i915/bxt: Clean up bxt_init_clock_gating

[Nick Hoath]

On 29/06/2015 15:29, Mika Kuoppala wrote:
> Nick Hoath <nicholas.hoath@intel.com> writes:
>
>> Add stepping check for A0 workarounds, and remove the associated
>> FIXME tags.
>> Split out unrelated WAs for later condition checking.
>>
>> v2: Fixed format (PeterL)
>> v3: Corrected stepping check for WaDisableSDEUnitClockGating
>>      - Ignoring comment, following hardware spec instead. (ChrisH)
>>      Added description for TILECTL setting (JonB)
>>
>> Cc: Peter Lawthers <peter.lawthers@intel.com>
>> Cc: Chris Harris <chris.harris@intel.com>
>> Cc: Jon Bloomfield <jon.bloomfield@intel.com>
>> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
>>   1 file changed, 11 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 26ef146..86a4ced 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -115,18 +115,24 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>>
>>   	gen9_init_clock_gating(dev);
>>
>> +	/* WaDisableSDEUnitClockGating:bxt */
>> +	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> +		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>> +
>>   	/*
>>   	 * FIXME:
>> -	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
>>   	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
>>   	 */
>> -	 /* WaDisableSDEUnitClockGating:bxt */
>>   	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> -		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
>>   		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>>
>
> I guess you decided not to combine the writes due to FIXME.
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Looks like this one has fallen through the cracks & not been merged...

>
>
>> -	/* FIXME: apply on A0 only */
>> -	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
>> +	if (INTEL_REVID(dev) == BXT_REVID_A0) {
>> +		/*
>> +		 * Hardware specification requires this bit to be
>> +		 * set to 1 for A0
>> +		 */
>> +		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
>> +	}
>>   }
>>
>>   static void i915_pineview_get_mem_freq(struct drm_device *dev)
>> --
>> 2.1.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 4/4] drm/i915/bxt: Clean up bxt_init_clock_gating

[Daniel Vetter]

On Mon, Sep 07, 2015 at 02:55:08PM +0100, Nick Hoath wrote:
> On 29/06/2015 15:29, Mika Kuoppala wrote:
> >Nick Hoath <nicholas.hoath@intel.com> writes:
> >
> >>Add stepping check for A0 workarounds, and remove the associated
> >>FIXME tags.
> >>Split out unrelated WAs for later condition checking.
> >>
> >>v2: Fixed format (PeterL)
> >>v3: Corrected stepping check for WaDisableSDEUnitClockGating
> >>     - Ignoring comment, following hardware spec instead. (ChrisH)
> >>     Added description for TILECTL setting (JonB)
> >>
> >>Cc: Peter Lawthers <peter.lawthers@intel.com>
> >>Cc: Chris Harris <chris.harris@intel.com>
> >>Cc: Jon Bloomfield <jon.bloomfield@intel.com>
> >>Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> >>---
> >>  drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
> >>  1 file changed, 11 insertions(+), 5 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >>index 26ef146..86a4ced 100644
> >>--- a/drivers/gpu/drm/i915/intel_pm.c
> >>+++ b/drivers/gpu/drm/i915/intel_pm.c
> >>@@ -115,18 +115,24 @@ static void bxt_init_clock_gating(struct drm_device *dev)
> >>
> >>  	gen9_init_clock_gating(dev);
> >>
> >>+	/* WaDisableSDEUnitClockGating:bxt */
> >>+	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >>+		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> >>+
> >>  	/*
> >>  	 * FIXME:
> >>-	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
> >>  	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
> >>  	 */
> >>-	 /* WaDisableSDEUnitClockGating:bxt */
> >>  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >>-		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
> >>  		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
> >>
> >
> >I guess you decided not to combine the writes due to FIXME.
> >
> >Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> 
> Looks like this one has fallen through the cracks & not been merged...

Thanks for the ping, applied to dinq.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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