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From: Dave Gordon <david.s.gordon@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Fix a bug in GuC status check
Date: Tue, 8 Sep 2015 09:06:50 +0100	[thread overview]
Message-ID: <55EE971A.2090308@intel.com> (raw)
In-Reply-To: <1441234332-7446-1-git-send-email-yu.dai@intel.com>

On 02/09/15 23:52, yu.dai@intel.com wrote:
> From: Alex Dai <yu.dai@intel.com>
>
> Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE
> status is a reliable readiness flag only when resuming from RC6.
> This fix a racing issue that allocation of doorbell fails whilst
> GuC init is not finished.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_reg.h     | 1 +
>   drivers/gpu/drm/i915/intel_guc_loader.c | 5 +++--
>   2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 8c8e574..dd0e1e8 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -37,6 +37,7 @@
>   #define   GS_UKERNEL_READY		  (0xF0 << GS_UKERNEL_SHIFT)
>   #define   GS_MIA_SHIFT			16
>   #define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
> +#define   GS_MIA_CORE_STATE		  (1 << GS_MIA_SHIFT)
>
>   #define SOFT_SCRATCH(n)			(0xc180 + ((n) * 4))
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 5eafd31..5823615 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -209,9 +209,10 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
>   				      u32 *status)
>   {
>   	u32 val = I915_READ(GUC_STATUS);
> +	u32 uk_val = val & GS_UKERNEL_MASK;
>   	*status = val;
> -	return ((val & GS_UKERNEL_MASK) == GS_UKERNEL_READY ||
> -		(val & GS_UKERNEL_MASK) == GS_UKERNEL_LAPIC_DONE);
> +	return (uk_val == GS_UKERNEL_READY ||
> +		((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
>   }
>
>   /*

This does indeed fix the problem of not being able to *re*initialise the 
GuC correctly after a hang/reset/reload cycle :) However I think the 
last line looks quite confusing, especially because of the mix of 
bitwise and logical operators (we have &, &&, and || all in one expression).

So I think it might be clearer if spelled out in two stages:

  {
         u32 val = I915_READ(GUC_STATUS);
+       u32 uk_val = val & GS_UKERNEL_MASK;
         *status = val;
-       return ((val & GS_UKERNEL_MASK) == GS_UKERNEL_READY ||
-               (val & GS_UKERNEL_MASK) == GS_UKERNEL_LAPIC_DONE);
+
+       /* Iff resuming from RC6, look for LAPIC_DONE */
+       if (val & GS_MIA_CORE_STATE)
+               if (uk_val == GS_UKERNEL_LAPIC_DONE)
+                       return true;
+
+       /* Otherwise just check whether the uKernel is READY */
+       return uk_val == GS_UKERNEL_READY;
  }

Other than that I'm quite happy with it, so either version gets a

Reviewed-by: Dave Gordon <david.s.gordon@intel.com>

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      reply	other threads:[~2015-09-08  8:06 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-02 22:52 [PATCH] drm/i915: Fix a bug in GuC status check yu.dai
2015-09-08  8:06 ` Dave Gordon [this message]

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