[PATCH v2 0/7] Gen9 RC6, Turbo, Coarse Power Gating Fixes

[PATCH v2 0/7] Gen9 RC6, Turbo, Coarse Power Gating Fixes

[Sagar Arun Kamble]

Combining all the patches together in this thread related to
RC6, Turbo and CPG.
Other pending patches under review are in the
	1. Several GuC related patches
	http://lists.freedesktop.org/archives/intel-gfx/2015-September/075663.html
	2. drm/i915: Increase maximum polling time to 50ms for forcewake request/clear ack
	http://lists.freedesktop.org/archives/intel-gfx/2015-August/074225.html
	3. drm/i915: Use only blitter forcewake
	http://lists.freedesktop.org/archives/intel-gfx/2015-August/074228.html

Alex Dai (1):
  drm/i915/guc: Notify coarse power gating configuration to GuC properly

Sagar Arun Kamble (6):
  drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro.
  drm/i915: WaRsDisableCoarsePowerGating
  drm/i915: WaRsUseTimeoutMode
  drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating
  drm/i915: Program GuC MAX IDLE Count
  drm/i915/bxt: WaGsvDisableTurbo

 drivers/gpu/drm/i915/i915_drv.h            |  5 ++++
 drivers/gpu/drm/i915/i915_guc_reg.h        |  1 +
 drivers/gpu/drm/i915/i915_guc_submission.c |  9 +++++-
 drivers/gpu/drm/i915/intel_pm.c            | 46 ++++++++++++++++++++++++------
 4 files changed, 52 insertions(+), 9 deletions(-)

-- 
1.9.1

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[PATCH v2 1/7] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro.

[Sagar Arun Kamble]

It will be usefull to specify w/a that affects only SKL GT3 and GT4.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5db246..1e48c86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2491,6 +2491,11 @@ struct drm_i915_cmd_table {
 #define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
 				 INTEL_DEVID(dev) == 0x1915 || \
 				 INTEL_DEVID(dev) == 0x191E)
+#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
+				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
+#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
+				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
+
 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
 
 #define SKL_REVID_A0		(0x0)
-- 
1.9.1

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[PATCH v2 2/7] drm/i915: WaRsDisableCoarsePowerGating

[Sagar Arun Kamble]

WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.

v2: Added GT3/GT4 Check.

Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1f6b5bb..c93d3a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4853,11 +4853,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
 
 	/*
 	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
-	 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
+	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
 	 */
-	I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
-			GEN9_MEDIA_PG_ENABLE : 0);
-
+	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
+		((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+		I915_WRITE(GEN9_PG_ENABLE, 0);
+	else
+		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
+				(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
-- 
1.9.1

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[PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode

[Sagar Arun Kamble]

Enable TO mode for RC6 for SKL till D0 and BXT till A0.

Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c93d3a7..6e4818d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4847,9 +4847,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
 		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
 	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
 			"on" : "off");
-	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
-				   GEN6_RC_CTL_EI_MODE(1) |
-				   rc6_mask);
+
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
+		(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
+                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+                                GEN7_RC_CTL_TO_MODE |
+                                rc6_mask);
+        else
+                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+                                GEN6_RC_CTL_EI_MODE(1) |
+                                rc6_mask);
 
 	/*
 	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
-- 
1.9.1

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[PATCH v2 4/7] drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating

[Sagar Arun Kamble]

Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e4818d..4d6bb6b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4830,7 +4830,13 @@ static void gen9_enable_rc6(struct drm_device *dev)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	/* 2b: Program RC6 thresholds.*/
-	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
+
+	/* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
+	if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
+					(INTEL_REVID(dev) <= SKL_REVID_E0)))
+		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
+	else
+		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
 	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
 	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
 	for_each_ring(ring, dev_priv, unused)
-- 
1.9.1

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[PATCH v2 5/7] drm/i915: Program GuC MAX IDLE Count

[Sagar Arun Kamble]

Cc: Alex Dai <yu.dai@intel.com>
Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c     | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 8c8e574..9d79a6b 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -53,6 +53,7 @@
 #define   START_DMA			  (1<<0)
 #define DMA_GUC_WOPCM_OFFSET		0xc340
 #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
+#define GUC_MAX_IDLE_COUNT		0xC3E4
 
 #define GUC_WOPCM_SIZE			0xc050
 #define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4d6bb6b..6843a48 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4841,6 +4841,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
 	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
 	for_each_ring(ring, dev_priv, unused)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+	if (HAS_GUC_UCODE(dev))
+		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
+
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
 
-- 
1.9.1

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[PATCH v2 6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly

[Sagar Arun Kamble]

From: Alex Dai <yu.dai@intel.com>

GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.

Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 792d0b9..05d1eff4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -155,10 +155,17 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
 				     struct i915_guc_client *client)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct drm_device *dev = dev_priv->dev;
 	u32 data[2];
 
 	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
-	data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
+
+	/* Notify GuC about Coarse Power Gating where supported */
+	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
+                ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+		data[1] = 0;
+        else
+		data[1] = (intel_enable_rc6(dev)) ? 3 : 0;
 
 	return host2guc_action(guc, data, 2);
 }
-- 
1.9.1

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[PATCH v2 7/7] drm/i915/bxt: WaGsvDisableTurbo

[Sagar Arun Kamble]

Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.

Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6843a48..90d8834 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4473,6 +4473,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
+	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
+		return;
+
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 	WARN_ON(val > dev_priv->rps.max_freq);
 	WARN_ON(val < dev_priv->rps.min_freq);
@@ -4793,6 +4797,12 @@ static void gen9_enable_rps(struct drm_device *dev)
 
 	gen6_init_rps_frequencies(dev);
 
+	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
+	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
+		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+		return;
+	}
+
 	/* Program defaults and thresholds for RPS*/
 	I915_WRITE(GEN6_RC_VIDEO_FREQ,
 		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
-- 
1.9.1

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[PATCH v3 1/1] drm/i915/bxt: WaGsvDisableTurbo

[Sagar Arun Kamble]

Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.

v3: Explicitly clear the Turbo control register (Akash)

Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 62de97e..b679e8e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4479,6 +4479,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
+	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
+		return;
+
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 	WARN_ON(val > dev_priv->rps.max_freq);
 	WARN_ON(val < dev_priv->rps.min_freq);
@@ -4799,6 +4803,22 @@ static void gen9_enable_rps(struct drm_device *dev)
 
 	gen6_init_rps_frequencies(dev);
 
+	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
+	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
+		/*
+		 * BIOS could leave the Hw Turbo enabled, so need to explicitly
+		 * clear out the Control register just to avoid inconsitency
+		 * with debugfs interface, which will show  Turbo as enabled
+		 * only, which is not expected by the User after adding the
+		 * WaGsvDisableTurbo. Apart from this there is no problem even
+		 * if the Turbo is left enabled in the Control register, as the
+		 * Up/Down interrupts would remain masked.
+		 */
+		I915_WRITE(GEN6_RP_CONTROL, 0);
+		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+		return;
+	}
+
 	/* Program defaults and thresholds for RPS*/
 	I915_WRITE(GEN6_RC_VIDEO_FREQ,
 		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
-- 
1.9.1

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Re: [PATCH v2 6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly

[Yu Dai]

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> From: Alex Dai <yu.dai@intel.com>
>
> GuC expects two bits for Render and Media domain separately when
> driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
> gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 792d0b9..05d1eff4 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -155,10 +155,17 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
>   				     struct i915_guc_client *client)
>   {
>   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	struct drm_device *dev = dev_priv->dev;
>   	u32 data[2];
>   
>   	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> -	data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
> +
> +	/* Notify GuC about Coarse Power Gating where supported */
> +	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> +                ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> +		data[1] = 0;
> +        else
> +		data[1] = (intel_enable_rc6(dev)) ? 3 : 0;
>   

Please hold off this patch. I plan to squash it into 
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075959.html, 
where we remove the magic code '3' here by defining forcewake domain flags.

Thanks,
Alex
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Re: [PATCH v2 1/7] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro.

[Yu Dai]

Looks good to me.
Reviewed-by: Alex Dai <yu.dai@intel.com>

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> It will be usefull to specify w/a that affects only SKL GT3 and GT4.
>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b5db246..1e48c86 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2491,6 +2491,11 @@ struct drm_i915_cmd_table {
>   #define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
>   				 INTEL_DEVID(dev) == 0x1915 || \
>   				 INTEL_DEVID(dev) == 0x191E)
> +#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
> +				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
> +#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
> +				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
> +
>   #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
>   
>   #define SKL_REVID_A0		(0x0)

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Re: [PATCH v2 2/7] drm/i915: WaRsDisableCoarsePowerGating

[Yu Dai]

Looks good to me.
Reviewed-by: Alex Dai <yu.dai@intel.com>

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
> disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
>
> v2: Added GT3/GT4 Check.
>
> Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
>   1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1f6b5bb..c93d3a7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4853,11 +4853,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
>   
>   	/*
>   	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> -	 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
> +	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
>   	 */
> -	I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> -			GEN9_MEDIA_PG_ENABLE : 0);
> -
> +	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> +		((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> +		I915_WRITE(GEN9_PG_ENABLE, 0);
> +	else
> +		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> +				(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
>   
>   	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>   

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Re: [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode

[Yu Dai]

Looks good to me.
Reviewed-by: Alex Dai <yu.dai@intel.com>

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> Enable TO mode for RC6 for SKL till D0 and BXT till A0.
>
> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
>   1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c93d3a7..6e4818d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4847,9 +4847,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
>   		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>   	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>   			"on" : "off");
> -	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> -				   GEN6_RC_CTL_EI_MODE(1) |
> -				   rc6_mask);
> +
> +	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> +		(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> +                                GEN7_RC_CTL_TO_MODE |
> +                                rc6_mask);
> +        else
> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> +                                GEN6_RC_CTL_EI_MODE(1) |
> +                                rc6_mask);
>   
>   	/*
>   	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.

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Re: [PATCH v2 4/7] drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating

[Yu Dai]

Looks good to me.
Reviewed-by: Alex Dai <yu.dai@intel.com>

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
>   1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6e4818d..4d6bb6b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4830,7 +4830,13 @@ static void gen9_enable_rc6(struct drm_device *dev)
>   	I915_WRITE(GEN6_RC_CONTROL, 0);
>   
>   	/* 2b: Program RC6 thresholds.*/
> -	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> +
> +	/* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
> +	if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
> +					(INTEL_REVID(dev) <= SKL_REVID_E0)))
> +		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> +	else
> +		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
>   	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>   	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>   	for_each_ring(ring, dev_priv, unused)

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Re: [PATCH v2 5/7] drm/i915: Program GuC MAX IDLE Count

[Yu Dai]

Looks good to me.
Reviewed-by: Alex Dai <yu.dai@intel.com>

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> Cc: Alex Dai <yu.dai@intel.com>
> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c     | 4 ++++
>   2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 8c8e574..9d79a6b 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -53,6 +53,7 @@
>   #define   START_DMA			  (1<<0)
>   #define DMA_GUC_WOPCM_OFFSET		0xc340
>   #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
> +#define GUC_MAX_IDLE_COUNT		0xC3E4
>   
>   #define GUC_WOPCM_SIZE			0xc050
>   #define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4d6bb6b..6843a48 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4841,6 +4841,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
>   	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>   	for_each_ring(ring, dev_priv, unused)
>   		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> +
> +	if (HAS_GUC_UCODE(dev))
> +		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
> +
>   	I915_WRITE(GEN6_RC_SLEEP, 0);
>   	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>   

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Re: [PATCH v2 7/7] drm/i915/bxt: WaGsvDisableTurbo

[Yu Dai]

Looks good to me.
Reviewed-by: Alex Dai <yu.dai@intel.com>

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.
>
> Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6843a48..90d8834 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4473,6 +4473,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>   
> +	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> +	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
> +		return;
> +
>   	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>   	WARN_ON(val > dev_priv->rps.max_freq);
>   	WARN_ON(val < dev_priv->rps.min_freq);
> @@ -4793,6 +4797,12 @@ static void gen9_enable_rps(struct drm_device *dev)
>   
>   	gen6_init_rps_frequencies(dev);
>   
> +	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> +	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
> +		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +		return;
> +	}
> +
>   	/* Program defaults and thresholds for RPS*/
>   	I915_WRITE(GEN6_RC_VIDEO_FREQ,
>   		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));

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Re: [PATCH v2 6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly

[Yu Dai]

This one can be discarded and I will amend a fix to my other patch series.

Thanks,
Alex

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> From: Alex Dai <yu.dai@intel.com>
>
> GuC expects two bits for Render and Media domain separately when
> driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
> gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 792d0b9..05d1eff4 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -155,10 +155,17 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
>   				     struct i915_guc_client *client)
>   {
>   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	struct drm_device *dev = dev_priv->dev;
>   	u32 data[2];
>   
>   	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> -	data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
> +
> +	/* Notify GuC about Coarse Power Gating where supported */
> +	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> +                ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> +		data[1] = 0;
> +        else
> +		data[1] = (intel_enable_rc6(dev)) ? 3 : 0;
>   
>   	return host2guc_action(guc, data, 2);
>   }

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Re: [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode

[O'Rourke, Tom]

Hello,
This change looks good but incomplete.

When changing RC6 from EI mode to TO mode,
should the time value in GEN6_RC6_THRESHOLD
be changed to hold the timeout value instead
of the evaluation interval period?

Should the workaround name be included in a comment?
While this workaround is unnamed for Broadwell, it is
called WaRsUseTimeoutMode for Skylake.

If possible, I would like to see those changes
squashed into this patch.  If not, then putting
those changes in a followup patch would be OK.

Thanks,
Tom

On Mon, Sep 21, 2015 at 11:49:58AM -0700, Yu Dai wrote:
> Looks good to me.
> Reviewed-by: Alex Dai <yu.dai@intel.com>
> 
> On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> >Enable TO mode for RC6 for SKL till D0 and BXT till A0.
> >
> >Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
> >Cc: Akash Goel <akash.goel@intel.com>
> >Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> >---
> >  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
> >  1 file changed, 10 insertions(+), 3 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index c93d3a7..6e4818d 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -4847,9 +4847,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
> >  		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> >  	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> >  			"on" : "off");
> >-	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> >-				   GEN6_RC_CTL_EI_MODE(1) |
> >-				   rc6_mask);
> >+
> >+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> >+		(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> >+                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> >+                                GEN7_RC_CTL_TO_MODE |
> >+                                rc6_mask);
> >+        else
> >+                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> >+                                GEN6_RC_CTL_EI_MODE(1) |
> >+                                rc6_mask);
> >  	/*
> >  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> 
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Re: [PATCH v2 6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly

[Yu Dai]

On 09/21/2015 09:51 AM, Yu Dai wrote:
> On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> > From: Alex Dai <yu.dai@intel.com>
> >
> > GuC expects two bits for Render and Media domain separately when
> > driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
> > gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
> >
> > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++++-
> >   1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> > index 792d0b9..05d1eff4 100644
> > --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> > @@ -155,10 +155,17 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
> >   				     struct i915_guc_client *client)
> >   {
> >   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> > +	struct drm_device *dev = dev_priv->dev;
> >   	u32 data[2];
> >
> >   	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> > -	data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
> > +
> > +	/* Notify GuC about Coarse Power Gating where supported */
> > +	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> > +                ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> > +		data[1] = 0;
> > +        else
> > +		data[1] = (intel_enable_rc6(dev)) ? 3 : 0;
> >
>
> Please hold off this patch. I plan to squash it into
> http://lists.freedesktop.org/archives/intel-gfx/2015-September/075959.html,
> where we remove the magic code '3' here by defining forcewake domain flags.
>
>

I did not add this w/a checking to my new patch series. 
http://lists.freedesktop.org/archives/intel-gfx/2015-September/076348.html. 
We still need this one. Is it better to add definition like 
HAS_CPG(dev)? So we can use it here and also in gen9_enable_rc6.

Thanks,
Alex
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Re: [PATCH v2 7/7] drm/i915/bxt: WaGsvDisableTurbo

[Kamble, Sagar A]

Hi Alex,

Could you review and provide r-b tag for 3rd rev: 
http://lists.freedesktop.org/archives/intel-gfx/2015-September/076223.html

Thanks
Sagar


On 9/22/2015 12:20 AM, Yu Dai wrote:
> Looks good to me.
> Reviewed-by: Alex Dai <yu.dai@intel.com>
>
> On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
>> Disable Turbo on steppings prior to B0 on BXT due to hangs seen 
>> during GT CPD exit.
>>
>> Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 6843a48..90d8834 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4473,6 +4473,10 @@ static void gen6_set_rps(struct drm_device 
>> *dev, u8 val)
>>   {
>>       struct drm_i915_private *dev_priv = dev->dev_private;
>>   +    /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
>> +    if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
>> +        return;
>> +
>>       WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>>       WARN_ON(val > dev_priv->rps.max_freq);
>>       WARN_ON(val < dev_priv->rps.min_freq);
>> @@ -4793,6 +4797,12 @@ static void gen9_enable_rps(struct drm_device 
>> *dev)
>>         gen6_init_rps_frequencies(dev);
>>   +    /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
>> +    if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
>> +        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>> +        return;
>> +    }
>> +
>>       /* Program defaults and thresholds for RPS*/
>>       I915_WRITE(GEN6_RC_VIDEO_FREQ,
>>           GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
>

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Re: [PATCH v2 2/7] drm/i915: WaRsDisableCoarsePowerGating

[Daniel Vetter]

On Sat, Sep 12, 2015 at 10:17:51AM +0530, Sagar Arun Kamble wrote:
> WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
> disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
> 
> v2: Added GT3/GT4 Check.
> 
> Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1f6b5bb..c93d3a7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4853,11 +4853,14 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  
>  	/*
>  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> -	 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
> +	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
>  	 */
> -	I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> -			GEN9_MEDIA_PG_ENABLE : 0);
> -
> +	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> +		((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))

I fixed up the continuation to be aligned properly while applying.
-Daniel

> +		I915_WRITE(GEN9_PG_ENABLE, 0);
> +	else
> +		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> +				(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>  
> -- 
> 1.9.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode

[Daniel Vetter]

On Sat, Sep 12, 2015 at 10:17:52AM +0530, Sagar Arun Kamble wrote:
> Enable TO mode for RC6 for SKL till D0 and BXT till A0.
> 
> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c93d3a7..6e4818d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4847,9 +4847,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>  	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>  			"on" : "off");
> -	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> -				   GEN6_RC_CTL_EI_MODE(1) |
> -				   rc6_mask);
> +
> +	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> +		(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))

Again I fixed the continuation alignment here ...
-Daniel

> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> +                                GEN7_RC_CTL_TO_MODE |
> +                                rc6_mask);
> +        else
> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> +                                GEN6_RC_CTL_EI_MODE(1) |
> +                                rc6_mask);
>  
>  	/*
>  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH v2 4/7] drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating

[Daniel Vetter]

On Sat, Sep 12, 2015 at 10:17:53AM +0530, Sagar Arun Kamble wrote:
> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6e4818d..4d6bb6b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4830,7 +4830,13 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  	I915_WRITE(GEN6_RC_CONTROL, 0);
>  
>  	/* 2b: Program RC6 thresholds.*/
> -	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> +
> +	/* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
> +	if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
> +					(INTEL_REVID(dev) <= SKL_REVID_E0)))

Same deal again.
-Daniel

> +		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> +	else
> +		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
>  	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>  	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>  	for_each_ring(ring, dev_priv, unused)
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH v2 7/7] drm/i915/bxt: WaGsvDisableTurbo

[Daniel Vetter]

On Mon, Sep 21, 2015 at 11:50:53AM -0700, Yu Dai wrote:
> Looks good to me.
> Reviewed-by: Alex Dai <yu.dai@intel.com>
> 
> On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> >Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit.
> >
> >Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
> >Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

I didn't pick up this one since there's a newer revision. Merged the other
patches from this series with an r-b tag.

Thanks, Daniel
> >---
> >  drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index 6843a48..90d8834 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -4473,6 +4473,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >+	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> >+	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
> >+		return;
> >+
> >  	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> >  	WARN_ON(val > dev_priv->rps.max_freq);
> >  	WARN_ON(val < dev_priv->rps.min_freq);
> >@@ -4793,6 +4797,12 @@ static void gen9_enable_rps(struct drm_device *dev)
> >  	gen6_init_rps_frequencies(dev);
> >+	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
> >+	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
> >+		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> >+		return;
> >+	}
> >+
> >  	/* Program defaults and thresholds for RPS*/
> >  	I915_WRITE(GEN6_RC_VIDEO_FREQ,
> >  		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode

[Kamble, Sagar A]

Thank you.
I am sending another change Tom wanted as part of this patch.
Kindly stash into the current patch.

Thanks
Sagar


On 9/23/2015 2:20 PM, Daniel Vetter wrote:
> On Sat, Sep 12, 2015 at 10:17:52AM +0530, Sagar Arun Kamble wrote:
>> Enable TO mode for RC6 for SKL till D0 and BXT till A0.
>>
>> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Cc: Akash Goel <akash.goel@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
>>   1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index c93d3a7..6e4818d 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4847,9 +4847,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
>>   		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>>   	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>>   			"on" : "off");
>> -	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>> -				   GEN6_RC_CTL_EI_MODE(1) |
>> -				   rc6_mask);
>> +
>> +	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
>> +		(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> Again I fixed the continuation alignment here ...
> -Daniel
>
>> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>> +                                GEN7_RC_CTL_TO_MODE |
>> +                                rc6_mask);
>> +        else
>> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>> +                                GEN6_RC_CTL_EI_MODE(1) |
>> +                                rc6_mask);
>>   
>>   	/*
>>   	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
>> -- 
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[PATCH 1/1] drm/i915: Update Promotion timer for RC6 TO Mode

[Sagar Arun Kamble]

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a878147..ebde43d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4842,7 +4842,6 @@ static void gen9_enable_rc6(struct drm_device *dev)
 	for_each_ring(ring, dev_priv, unused)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
 	I915_WRITE(GEN6_RC_SLEEP, 0);
-	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
 
 	/* 2c: Program Coarse Power Gating Policies. */
 	I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
@@ -4854,15 +4853,19 @@ static void gen9_enable_rc6(struct drm_device *dev)
 	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
 			"on" : "off");
 
+	/* WaRsUseTimeoutMode */
 	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
-	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
+		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
                                 GEN7_RC_CTL_TO_MODE |
                                 rc6_mask);
-        else
+	} else {
+		I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
                                 GEN6_RC_CTL_EI_MODE(1) |
                                 rc6_mask);
+	}
 
 	/*
 	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
-- 
1.9.1

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Re: [PATCH 1/1] drm/i915: Update Promotion timer for RC6 TO Mode

[O'Rourke, Tom]

This change looks good and is necessary, but the
commit message should have more detail.

I would add:
"When using RC6 timeout mode, the timeout value
should be written to GEN6_RC6_THRESHOLD."

With that,
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>

On Wed, Sep 23, 2015 at 03:06:42PM +0530, Sagar Arun Kamble wrote:
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a878147..ebde43d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4842,7 +4842,6 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  	for_each_ring(ring, dev_priv, unused)
>  		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
>  	I915_WRITE(GEN6_RC_SLEEP, 0);
> -	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>  
>  	/* 2c: Program Coarse Power Gating Policies. */
>  	I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
> @@ -4854,15 +4853,19 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>  			"on" : "off");
>  
> +	/* WaRsUseTimeoutMode */
>  	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> -	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
> +		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
>                  I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>                                  GEN7_RC_CTL_TO_MODE |
>                                  rc6_mask);
> -        else
> +	} else {
> +		I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>                  I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>                                  GEN6_RC_CTL_EI_MODE(1) |
>                                  rc6_mask);
> +	}
>  
>  	/*
>  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> -- 
> 1.9.1
> 
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[PATCH v2 1/1] drm/i915: Update Promotion timer for RC6 TO Mode

[Sagar Arun Kamble]

When using RC6 timeout mode, the timeout value
should be written to GEN6_RC6_THRESHOLD.

v2: Updated commit message. (Tom)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a878147..ebde43d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4842,7 +4842,6 @@ static void gen9_enable_rc6(struct drm_device *dev)
 	for_each_ring(ring, dev_priv, unused)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
 	I915_WRITE(GEN6_RC_SLEEP, 0);
-	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
 
 	/* 2c: Program Coarse Power Gating Policies. */
 	I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
@@ -4854,15 +4853,19 @@ static void gen9_enable_rc6(struct drm_device *dev)
 	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
 			"on" : "off");
 
+	/* WaRsUseTimeoutMode */
 	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
-	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
+		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
                                 GEN7_RC_CTL_TO_MODE |
                                 rc6_mask);
-        else
+	} else {
+		I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
                                 GEN6_RC_CTL_EI_MODE(1) |
                                 rc6_mask);
+	}
 
 	/*
 	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
-- 
1.9.1

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Re: [PATCH v2 1/1] drm/i915: Update Promotion timer for RC6 TO Mode

[O'Rourke, Tom]

On Wed, Sep 30, 2015 at 04:13:43PM +0530, Sagar Arun Kamble wrote:
> When using RC6 timeout mode, the timeout value
> should be written to GEN6_RC6_THRESHOLD.
> 
> v2: Updated commit message. (Tom)
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a878147..ebde43d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4842,7 +4842,6 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  	for_each_ring(ring, dev_priv, unused)
>  		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
>  	I915_WRITE(GEN6_RC_SLEEP, 0);
> -	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>  
>  	/* 2c: Program Coarse Power Gating Policies. */
>  	I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
> @@ -4854,15 +4853,19 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>  			"on" : "off");
>  
> +	/* WaRsUseTimeoutMode */
>  	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> -	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
> +		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
>                  I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>                                  GEN7_RC_CTL_TO_MODE |
>                                  rc6_mask);
> -        else
> +	} else {
> +		I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>                  I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>                                  GEN6_RC_CTL_EI_MODE(1) |
>                                  rc6_mask);
> +	}
>  
>  	/*
>  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> -- 
> 1.9.1
> 
> _______________________________________________
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Re: [PATCH v2 1/1] drm/i915: Update Promotion timer for RC6 TO Mode

[Daniel Vetter]

On Wed, Sep 30, 2015 at 04:13:43PM +0530, Sagar Arun Kamble wrote:
> When using RC6 timeout mode, the timeout value
> should be written to GEN6_RC6_THRESHOLD.
> 
> v2: Updated commit message. (Tom)
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a878147..ebde43d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4842,7 +4842,6 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  	for_each_ring(ring, dev_priv, unused)
>  		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
>  	I915_WRITE(GEN6_RC_SLEEP, 0);
> -	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>  
>  	/* 2c: Program Coarse Power Gating Policies. */
>  	I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
> @@ -4854,15 +4853,19 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>  			"on" : "off");
>  
> +	/* WaRsUseTimeoutMode */
>  	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> -	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
> +		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
>                  I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>                                  GEN7_RC_CTL_TO_MODE |
>                                  rc6_mask);

This patch here needs to be regenerated since the whitespace doesn't match
- I've fixed it up when applying the previous patch.
-Daniel

> -        else
> +	} else {
> +		I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>                  I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>                                  GEN6_RC_CTL_EI_MODE(1) |
>                                  rc6_mask);
> +	}
>  
>  	/*
>  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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