From: Yu Dai <yu.dai@intel.com>
To: Sagar Arun Kamble <sagar.a.kamble@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly
Date: Tue, 22 Sep 2015 15:51:44 -0700 [thread overview]
Message-ID: <5601DB80.9080407@intel.com> (raw)
In-Reply-To: <5600358D.1040809@intel.com>
On 09/21/2015 09:51 AM, Yu Dai wrote:
> On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> > From: Alex Dai <yu.dai@intel.com>
> >
> > GuC expects two bits for Render and Media domain separately when
> > driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
> > gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
> >
> > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> > index 792d0b9..05d1eff4 100644
> > --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> > @@ -155,10 +155,17 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
> > struct i915_guc_client *client)
> > {
> > struct drm_i915_private *dev_priv = guc_to_i915(guc);
> > + struct drm_device *dev = dev_priv->dev;
> > u32 data[2];
> >
> > data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> > - data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
> > +
> > + /* Notify GuC about Coarse Power Gating where supported */
> > + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> > + ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> > + data[1] = 0;
> > + else
> > + data[1] = (intel_enable_rc6(dev)) ? 3 : 0;
> >
>
> Please hold off this patch. I plan to squash it into
> http://lists.freedesktop.org/archives/intel-gfx/2015-September/075959.html,
> where we remove the magic code '3' here by defining forcewake domain flags.
>
>
I did not add this w/a checking to my new patch series.
http://lists.freedesktop.org/archives/intel-gfx/2015-September/076348.html.
We still need this one. Is it better to add definition like
HAS_CPG(dev)? So we can use it here and also in gen9_enable_rc6.
Thanks,
Alex
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next prev parent reply other threads:[~2015-09-22 22:53 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-12 4:47 [PATCH v2 0/7] Gen9 RC6, Turbo, Coarse Power Gating Fixes Sagar Arun Kamble
2015-09-12 4:47 ` [PATCH v2 1/7] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro Sagar Arun Kamble
2015-09-21 18:49 ` Yu Dai
2015-09-12 4:47 ` [PATCH v2 2/7] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
2015-09-21 18:49 ` Yu Dai
2015-09-23 8:49 ` Daniel Vetter
2015-09-12 4:47 ` [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode Sagar Arun Kamble
2015-09-21 18:49 ` Yu Dai
2015-09-21 21:47 ` O'Rourke, Tom
2015-09-23 8:50 ` Daniel Vetter
2015-09-23 9:33 ` Kamble, Sagar A
2015-09-23 9:36 ` [PATCH 1/1] drm/i915: Update Promotion timer for RC6 TO Mode Sagar Arun Kamble
2015-09-24 21:11 ` O'Rourke, Tom
2015-09-30 10:43 ` [PATCH v2 " Sagar Arun Kamble
2015-09-30 16:38 ` O'Rourke, Tom
2015-10-01 8:21 ` Daniel Vetter
2015-09-12 4:47 ` [PATCH v2 4/7] drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating Sagar Arun Kamble
2015-09-21 18:50 ` Yu Dai
2015-09-23 8:51 ` Daniel Vetter
2015-09-12 4:47 ` [PATCH v2 5/7] drm/i915: Program GuC MAX IDLE Count Sagar Arun Kamble
2015-09-21 18:50 ` Yu Dai
2015-09-12 4:47 ` [PATCH v2 6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly Sagar Arun Kamble
2015-09-21 16:51 ` Yu Dai
2015-09-22 22:51 ` Yu Dai [this message]
2015-09-21 18:59 ` Yu Dai
2015-09-12 4:47 ` [PATCH v2 7/7] drm/i915/bxt: WaGsvDisableTurbo Sagar Arun Kamble
2015-09-21 11:24 ` [PATCH v3 1/1] " Sagar Arun Kamble
2015-09-21 18:50 ` [PATCH v2 7/7] " Yu Dai
2015-09-23 6:32 ` Kamble, Sagar A
2015-09-23 8:53 ` Daniel Vetter
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