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From: "Kamble, Sagar A" <sagar.a.kamble@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org, Akash Goel <akash.goel@intel.com>
Subject: Re: [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode
Date: Wed, 23 Sep 2015 15:03:45 +0530	[thread overview]
Message-ID: <560271F9.7070600@intel.com> (raw)
In-Reply-To: <20150923085027.GV3383@phenom.ffwll.local>

Thank you.
I am sending another change Tom wanted as part of this patch.
Kindly stash into the current patch.

Thanks
Sagar


On 9/23/2015 2:20 PM, Daniel Vetter wrote:
> On Sat, Sep 12, 2015 at 10:17:52AM +0530, Sagar Arun Kamble wrote:
>> Enable TO mode for RC6 for SKL till D0 and BXT till A0.
>>
>> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
>> Cc: Akash Goel <akash.goel@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
>>   1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index c93d3a7..6e4818d 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4847,9 +4847,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
>>   		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>>   	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>>   			"on" : "off");
>> -	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>> -				   GEN6_RC_CTL_EI_MODE(1) |
>> -				   rc6_mask);
>> +
>> +	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
>> +		(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> Again I fixed the continuation alignment here ...
> -Daniel
>
>> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>> +                                GEN7_RC_CTL_TO_MODE |
>> +                                rc6_mask);
>> +        else
>> +                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>> +                                GEN6_RC_CTL_EI_MODE(1) |
>> +                                rc6_mask);
>>   
>>   	/*
>>   	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
>> -- 
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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  reply	other threads:[~2015-09-23  9:33 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-12  4:47 [PATCH v2 0/7] Gen9 RC6, Turbo, Coarse Power Gating Fixes Sagar Arun Kamble
2015-09-12  4:47 ` [PATCH v2 1/7] drm/i915: Add IS_SKL_GT3 and IS_SKL_GT4 macro Sagar Arun Kamble
2015-09-21 18:49   ` Yu Dai
2015-09-12  4:47 ` [PATCH v2 2/7] drm/i915: WaRsDisableCoarsePowerGating Sagar Arun Kamble
2015-09-21 18:49   ` Yu Dai
2015-09-23  8:49   ` Daniel Vetter
2015-09-12  4:47 ` [PATCH v2 3/7] drm/i915: WaRsUseTimeoutMode Sagar Arun Kamble
2015-09-21 18:49   ` Yu Dai
2015-09-21 21:47     ` O'Rourke, Tom
2015-09-23  8:50   ` Daniel Vetter
2015-09-23  9:33     ` Kamble, Sagar A [this message]
2015-09-23  9:36     ` [PATCH 1/1] drm/i915: Update Promotion timer for RC6 TO Mode Sagar Arun Kamble
2015-09-24 21:11       ` O'Rourke, Tom
2015-09-30 10:43         ` [PATCH v2 " Sagar Arun Kamble
2015-09-30 16:38           ` O'Rourke, Tom
2015-10-01  8:21           ` Daniel Vetter
2015-09-12  4:47 ` [PATCH v2 4/7] drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating Sagar Arun Kamble
2015-09-21 18:50   ` Yu Dai
2015-09-23  8:51   ` Daniel Vetter
2015-09-12  4:47 ` [PATCH v2 5/7] drm/i915: Program GuC MAX IDLE Count Sagar Arun Kamble
2015-09-21 18:50   ` Yu Dai
2015-09-12  4:47 ` [PATCH v2 6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly Sagar Arun Kamble
2015-09-21 16:51   ` Yu Dai
2015-09-22 22:51     ` Yu Dai
2015-09-21 18:59   ` Yu Dai
2015-09-12  4:47 ` [PATCH v2 7/7] drm/i915/bxt: WaGsvDisableTurbo Sagar Arun Kamble
2015-09-21 11:24   ` [PATCH v3 1/1] " Sagar Arun Kamble
2015-09-21 18:50   ` [PATCH v2 7/7] " Yu Dai
2015-09-23  6:32     ` Kamble, Sagar A
2015-09-23  8:53     ` Daniel Vetter

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