From: Michel Thierry <michel.thierry@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915/gen8: Flip the 48b switch
Date: Thu, 1 Oct 2015 15:40:44 +0100 [thread overview]
Message-ID: <560D45EC.6010004@intel.com> (raw)
In-Reply-To: <20151001131628.GY3383@phenom.ffwll.local>
On 10/1/2015 2:16 PM, Daniel Vetter wrote:
> On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote:
>> Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
>> Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.
>>
>> Note, aliasing PPGTT remains 32b only.
>>
>> v2: s/full_64b/full_48b/. (Akash)
>> v3: Add sanitize_enable_ppgtt changes until here. (Akash)
>> v4: Update param description (Chris)
>>
>> Cc: Akash Goel <akash.goel@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>
> Queued for -next, thanks for the patch. Can you please ping someone from
> mesa to push the libdrm/mesa patches too?
>
Sure, I'll start the libdmr-mesa process.
Thanks,
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next prev parent reply other threads:[~2015-10-01 14:40 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-30 14:36 [PATCH 0/2] Wa32bit & Enable 48bit PPGTT Michel Thierry
2015-09-30 14:36 ` [PATCH 1/2] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-09-30 14:42 ` Chris Wilson
2015-09-30 15:45 ` Tvrtko Ursulin
2015-09-30 15:53 ` Chris Wilson
2015-10-01 12:33 ` [PATCH v2 (not really v2)] " Michel Thierry
2015-10-01 13:15 ` Daniel Vetter
2015-09-30 14:36 ` [PATCH 2/2] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-10-01 13:16 ` Daniel Vetter
2015-10-01 14:40 ` Michel Thierry [this message]
2015-10-16 12:23 ` Michel Thierry
2015-10-19 9:44 ` Daniel Vetter
2015-10-19 10:01 ` Chris Wilson
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