From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 02/14] drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL
Date: Thu, 29 Oct 2015 12:33:50 -0700 [thread overview]
Message-ID: <5632749E.20901@virtuousgeek.org> (raw)
In-Reply-To: <1446146763-31821-3-git-send-email-ville.syrjala@linux.intel.com>
On 10/29/2015 12:25 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rather than looking at crtc->mode (which is the user mode) dig up the
> sync polarity settings from the adjusted_mode when programming
> TRANS_DP_CTL on CPT/PPT.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d3cd177..99fb33f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4170,6 +4170,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
> /* For PCH DP, enable TRANS_DP_CTL */
> if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
> + const struct drm_display_mode *adjusted_mode =
> + &intel_crtc->config->base.adjusted_mode;
> u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> reg = TRANS_DP_CTL(pipe);
> temp = I915_READ(reg);
> @@ -4179,9 +4181,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> temp |= TRANS_DP_OUTPUT_ENABLE;
> temp |= bpc << 9; /* same format but at 11:9 */
>
> - if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
> - if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
> + if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
>
> switch (intel_trans_dp_port_sel(crtc)) {
>
God I wish we'd rename these structs a bit... "adjusted" and
"crtc->mode" don't really communicate much.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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next prev parent reply other threads:[~2015-10-29 19:33 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-29 19:25 [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms ville.syrjala
2015-10-29 19:25 ` [PATCH 01/14] drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config around ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 02/14] drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL ville.syrjala
2015-10-29 19:33 ` Jesse Barnes [this message]
2015-10-29 19:25 ` [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:57 ` Paulo Zanoni
2015-10-29 21:21 ` Ville Syrjälä
2015-10-30 15:42 ` Daniel Vetter
2015-10-30 10:06 ` Jani Nikula
2015-10-30 12:08 ` Ville Syrjälä
2015-10-30 12:31 ` Jani Nikula
2015-10-30 15:41 ` Daniel Vetter
2015-10-30 17:20 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 04/14] drm/i915: Enable PCH FIFO underruns later on HSW+ ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 05/14] drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled ville.syrjala
2015-10-29 19:36 ` Jesse Barnes
2015-10-29 21:39 ` Ville Syrjälä
2015-10-30 17:21 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 06/14] drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPT ville.syrjala
2015-10-30 15:45 ` Daniel Vetter
2015-10-30 17:22 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 07/14] drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder() ville.syrjala
2015-10-29 19:37 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 08/14] drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround ville.syrjala
2015-10-29 19:38 ` Jesse Barnes
2015-10-30 10:11 ` Jani Nikula
2015-10-30 12:15 ` Ville Syrjälä
2015-10-30 17:23 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 09/14] drm/i915: Hide underruns from eDP PLL and port enable on ILK ville.syrjala
2015-10-29 19:39 ` Jesse Barnes
2015-10-29 21:33 ` Ville Syrjälä
2015-10-29 19:25 ` [PATCH 10/14] drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/ ville.syrjala
2015-10-30 15:49 ` Daniel Vetter
2015-10-29 19:26 ` [PATCH 11/14] drm/i915: Remove ILK-A eDP PLL workaround notes ville.syrjala
2015-10-29 19:40 ` Jesse Barnes
2015-10-29 19:26 ` [PATCH 12/14] drm/i915: Clean up eDP PLL state asserts ville.syrjala
2015-10-30 15:53 ` Daniel Vetter
2015-10-29 19:26 ` [PATCH 13/14] drm/i915: Use intel_dp->DP in eDP PLL setup ville.syrjala
2015-10-30 16:00 ` Daniel Vetter
2015-10-30 16:36 ` Ville Syrjälä
2015-11-10 14:37 ` Jani Nikula
2015-11-10 14:16 ` [PATCH v2 " ville.syrjala
2015-11-10 14:43 ` Jani Nikula
2015-10-29 19:26 ` [PATCH 14/14] drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on() ville.syrjala
2015-10-30 16:01 ` Daniel Vetter
2015-10-30 13:30 ` [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms Jani Nikula
2015-11-10 15:04 ` Ville Syrjälä
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