* [PATCH 0/6] Kabylake patches V2
@ 2015-10-27 17:14 Rodrigo Vivi
2015-10-27 17:14 ` [PATCH 1/6] drm/i915: Define IS_BROXTON properly Rodrigo Vivi
` (6 more replies)
0 siblings, 7 replies; 28+ messages in thread
From: Rodrigo Vivi @ 2015-10-27 17:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Rodrigo Vivi
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This is the second version of the Kabylake enabling patches.
This new version Kabylake is defined totally independent from Skylake
and without doing the revid+7 hack.
An special thanks to Jani that did a great job on redefining the REVID
macros used for Workarounds. That made my life here when creating
a Kabylake separated from Skylake. Thanks!
I also brings new PCI IDs for GT4.
Deepak S (2):
drm/i915/kbl: Add Kabylake PCI ID
drm/i915/kbl: Add Kabylake GT4 PCI ID
Rodrigo Vivi (4):
drm/i915: Define IS_BROXTON properly.
drm/i915/kbl: Introduce Kabylake platform defition.
drm/i915/kbl: Use propper ddi buffer translation table for Kabylake
ULT and ULX.
drm/i915/kbl: Fix DMC load on Kabylake.
drivers/gpu/drm/i915/i915_debugfs.c | 16 +++++++----
drivers/gpu/drm/i915/i915_dma.c | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 51 ++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++--
drivers/gpu/drm/i915/i915_gem_stolen.c | 3 +-
drivers/gpu/drm/i915/intel_audio.c | 9 +++---
drivers/gpu/drm/i915/intel_csr.c | 36 +++++++++++++++++++----
drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++---------
drivers/gpu/drm/i915/intel_display.c | 12 ++++----
drivers/gpu/drm/i915/intel_dp.c | 6 ++--
drivers/gpu/drm/i915/intel_fbc.c | 3 +-
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 11 +++----
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
include/drm/i915_pciids.h | 36 +++++++++++++++++++++++
15 files changed, 175 insertions(+), 58 deletions(-)
--
2.4.3
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^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH 1/6] drm/i915: Define IS_BROXTON properly. 2015-10-27 17:14 [PATCH 0/6] Kabylake patches V2 Rodrigo Vivi @ 2015-10-27 17:14 ` Rodrigo Vivi 2015-10-28 9:27 ` Jani Nikula 2015-10-27 17:14 ` [PATCH 2/6] drm/i915/kbl: Introduce Kabylake platform defition Rodrigo Vivi ` (5 subsequent siblings) 6 siblings, 1 reply; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-27 17:14 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Rodrigo Vivi Kabylake will also be defined as gen9 and !is_skylake. So we need start by creating a proper Broxton definition, otherwise we will break broxton with the introduction of Kabylake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b1f1dec..70f9d3d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -383,6 +383,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { static const struct intel_device_info intel_broxton_info = { .is_preliminary = 1, + .is_broxton = 1, .gen = 9, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9a15ebe..565e63a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -765,6 +765,7 @@ struct intel_csr { func(is_valleyview) sep \ func(is_haswell) sep \ func(is_skylake) sep \ + func(is_broxton) sep \ func(is_preliminary) sep \ func(has_fbc) sep \ func(has_pipe_cxsr) sep \ @@ -2475,7 +2476,7 @@ struct drm_i915_cmd_table { #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) -#define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) +#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 1/6] drm/i915: Define IS_BROXTON properly. 2015-10-27 17:14 ` [PATCH 1/6] drm/i915: Define IS_BROXTON properly Rodrigo Vivi @ 2015-10-28 9:27 ` Jani Nikula 0 siblings, 0 replies; 28+ messages in thread From: Jani Nikula @ 2015-10-28 9:27 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi On Tue, 27 Oct 2015, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > Kabylake will also be defined as gen9 and !is_skylake. > So we need start by creating a proper Broxton > definition, otherwise we will break broxton with the > introduction of Kabylake. > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 1 + > drivers/gpu/drm/i915/i915_drv.h | 3 ++- > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index b1f1dec..70f9d3d 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -383,6 +383,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { > > static const struct intel_device_info intel_broxton_info = { > .is_preliminary = 1, > + .is_broxton = 1, > .gen = 9, > .need_gfx_hws = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 9a15ebe..565e63a 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -765,6 +765,7 @@ struct intel_csr { > func(is_valleyview) sep \ > func(is_haswell) sep \ > func(is_skylake) sep \ > + func(is_broxton) sep \ > func(is_preliminary) sep \ > func(has_fbc) sep \ > func(has_pipe_cxsr) sep \ > @@ -2475,7 +2476,7 @@ struct drm_i915_cmd_table { > #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) > #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) > #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) > -#define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) > +#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) > #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) > #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ > (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/6] drm/i915/kbl: Introduce Kabylake platform defition. 2015-10-27 17:14 [PATCH 0/6] Kabylake patches V2 Rodrigo Vivi 2015-10-27 17:14 ` [PATCH 1/6] drm/i915: Define IS_BROXTON properly Rodrigo Vivi @ 2015-10-27 17:14 ` Rodrigo Vivi 2015-10-28 11:39 ` Jani Nikula 2015-10-27 17:14 ` [PATCH 3/6] drm/i915/kbl: Add Kabylake PCI ID Rodrigo Vivi ` (4 subsequent siblings) 6 siblings, 1 reply; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-27 17:14 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Rodrigo Vivi Kabylake is a Intel® Processor containing Intel® HD Graphics following Skylake. It is Gen9p5, so it inherits everything from Skylake. First version adding PCI IDs was also defining the platform with is_skylake=1. But this was bringing even more confusion to the platform definitions. So let's start by adding the platform separated from Skylake but reusing most of all features, functions etc. Later we rebase the PCI-ID patch so we don't replace what original Author did there. Few IS_SKYLAKEs if statements are not being covered by this patch on purpose: - Workarounds: Kabylake is derivated from Skylake H0 so no W/As apply here. Also Jani already reworked the REVID in a way that they will be only applied to the right platform and stepping without any extra work required here. - GuC: A following patch removes Kabylake support with an explanation: No firmware available yet. - DMC/CSR: Done in a separated patch since we need to be carefull and load the version for revision 7 since Kabylake is Skylake H0. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 16 +++++++----- drivers/gpu/drm/i915/i915_dma.c | 3 ++- drivers/gpu/drm/i915/i915_drv.c | 44 ++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/i915_drv.h | 6 +++-- drivers/gpu/drm/i915/i915_gem_stolen.c | 3 ++- drivers/gpu/drm/i915/intel_audio.c | 9 ++++--- drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++------ drivers/gpu/drm/i915/intel_display.c | 12 ++++----- drivers/gpu/drm/i915/intel_dp.c | 6 ++--- drivers/gpu/drm/i915/intel_fbc.c | 3 ++- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 11 +++++---- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- 13 files changed, 88 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index eca94d0..5125aa5 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1252,18 +1252,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused) max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : rp_state_cap >> 16) & 0xff; - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? + GEN9_FREQ_SCALER : 1); seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); max_freq = (rp_state_cap & 0xff00) >> 8; - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? + GEN9_FREQ_SCALER : 1); seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : rp_state_cap >> 0) & 0xff; - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? + GEN9_FREQ_SCALER : 1); seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); seq_printf(m, "Max overclocked frequency: %dMHz\n", @@ -1801,7 +1804,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) if (ret) goto out; - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq = dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; @@ -1821,7 +1824,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) &ia_freq); seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", intel_gpu_freq(dev_priv, (gpu_freq * - (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))), + (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? + GEN9_FREQ_SCALER : 1))), ((ia_freq >> 0) & 0xff) * 100, ((ia_freq >> 8) & 0xff) * 100); } @@ -5029,7 +5033,7 @@ static void gen9_sseu_device_status(struct drm_device *dev, stat->slice_total++; - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) ss_cnt = INTEL_INFO(dev)->subslice_per_slice; for (ss = 0; ss < ss_max; ss++) { diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 2336af9..ddd1d46 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -668,7 +668,8 @@ static void gen9_sseu_info_init(struct drm_device *dev) * supports EU power gating on devices with more than one EU * pair per subslice. */ - info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1)); + info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && + (info->slice_total > 1)); info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); info->has_eu_pg = (info->eu_per_subslice > 2); } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 70f9d3d..c9e80fb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -395,6 +395,36 @@ static const struct intel_device_info intel_broxton_info = { IVB_CURSOR_OFFSETS, }; +static const struct intel_device_info intel_kabylake_info = { + .is_preliminary = 1, + .is_kabylake = 1, + .gen = 9, + .num_pipes = 3, + .need_gfx_hws = 1, .has_hotplug = 1, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .has_llc = 1, + .has_ddi = 1, + .has_fpga_dbg = 1, + .has_fbc = 1, + GEN_DEFAULT_PIPEOFFSETS, + IVB_CURSOR_OFFSETS, +}; + +static const struct intel_device_info intel_kabylake_gt3_info = { + .is_preliminary = 1, + .is_kabylake = 1, + .gen = 9, + .num_pipes = 3, + .need_gfx_hws = 1, .has_hotplug = 1, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .has_llc = 1, + .has_ddi = 1, + .has_fpga_dbg = 1, + .has_fbc = 1, + GEN_DEFAULT_PIPEOFFSETS, + IVB_CURSOR_OFFSETS, +}; + /* * Make sure any device matches here are from most specific to most * general. For example, since the Quanta match is based on the subsystem @@ -464,7 +494,7 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { ret = PCH_LPT; DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); - } else if (IS_SKYLAKE(dev)) { + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { ret = PCH_SPT; DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); } @@ -527,11 +557,13 @@ void intel_detect_pch(struct drm_device *dev) } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_SPT; DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); - WARN_ON(!IS_SKYLAKE(dev)); + WARN_ON(!IS_SKYLAKE(dev) && + !IS_KABYLAKE(dev)); } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_SPT; DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); - WARN_ON(!IS_SKYLAKE(dev)); + WARN_ON(!IS_SKYLAKE(dev) && + !IS_KABYLAKE(dev)); } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) { dev_priv->pch_type = intel_virt_detect_pch(dev); } else @@ -839,7 +871,7 @@ static int i915_drm_resume_early(struct drm_device *dev) if (IS_BROXTON(dev)) ret = bxt_resume_prepare(dev_priv); - else if (IS_SKYLAKE(dev_priv)) + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ret = skl_resume_prepare(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hsw_disable_pc8(dev_priv); @@ -1586,7 +1618,7 @@ static int intel_runtime_resume(struct device *device) if (IS_BROXTON(dev)) ret = bxt_resume_prepare(dev_priv); - else if (IS_SKYLAKE(dev)) + else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) ret = skl_resume_prepare(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hsw_disable_pc8(dev_priv); @@ -1630,7 +1662,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv) if (IS_BROXTON(dev_priv)) ret = bxt_suspend_complete(dev_priv); - else if (IS_SKYLAKE(dev_priv)) + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ret = skl_suspend_complete(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) ret = hsw_suspend_complete(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 565e63a..3982d1a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -766,6 +766,7 @@ struct intel_csr { func(is_haswell) sep \ func(is_skylake) sep \ func(is_broxton) sep \ + func(is_kabylake) sep \ func(is_preliminary) sep \ func(has_fbc) sep \ func(has_pipe_cxsr) sep \ @@ -2477,6 +2478,7 @@ struct drm_i915_cmd_table { #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) +#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) @@ -2597,10 +2599,10 @@ struct drm_i915_cmd_table { #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ - IS_SKYLAKE(dev)) + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ - IS_SKYLAKE(dev)) + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index cdacf3f..598ed2f 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -433,7 +433,8 @@ int i915_gem_init_stolen(struct drm_device *dev) &reserved_size); break; default: - if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) + if (IS_BROADWELL(dev_priv) || + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev)) bdw_get_stolen_reserved(dev_priv, &reserved_base, &reserved_size); else diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 4dccd9b..63d4706 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -591,7 +591,7 @@ static void i915_audio_component_codec_wake_override(struct device *dev, struct drm_i915_private *dev_priv = dev_to_i915(dev); u32 tmp; - if (!IS_SKYLAKE(dev_priv)) + if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) return; /* @@ -642,10 +642,11 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, u32 tmp; int n; - /* HSW, BDW SKL need this fix */ + /* HSW, BDW, SKL, KBL need this fix */ if (!IS_SKYLAKE(dev_priv) && - !IS_BROADWELL(dev_priv) && - !IS_HASWELL(dev_priv)) + !IS_KABYLAKE(dev_priv) && + !IS_BROADWELL(dev_priv) && + !IS_HASWELL(dev_priv)) return 0; mutex_lock(&dev_priv->av_mutex); diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a163741..8dd9fae 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -448,7 +448,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bxt_ddi_vswing_sequence(dev, hdmi_level, port, INTEL_OUTPUT_HDMI); return; - } else if (IS_SKYLAKE(dev)) { + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { ddi_translations_fdi = NULL; ddi_translations_dp = skl_get_buf_trans_dp(dev, &n_dp_entries); @@ -1184,7 +1184,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder, if (INTEL_INFO(dev)->gen <= 8) hsw_ddi_clock_get(encoder, pipe_config); - else if (IS_SKYLAKE(dev)) + else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) skl_ddi_clock_get(encoder, pipe_config); else if (IS_BROXTON(dev)) bxt_ddi_clock_get(encoder, pipe_config); @@ -1768,7 +1768,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, struct intel_encoder *intel_encoder = intel_ddi_get_crtc_new_encoder(crtc_state); - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) return skl_ddi_pll_select(intel_crtc, crtc_state, intel_encoder); else if (IS_BROXTON(dev)) @@ -2251,7 +2251,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) level = translate_signal_level(signal_levels); - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) skl_ddi_set_iboost(dev, level, port, encoder->type); else if (IS_BROXTON(dev)) bxt_ddi_vswing_sequence(dev, level, port, encoder->type); @@ -2274,7 +2274,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) intel_edp_panel_on(intel_dp); } - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { uint32_t dpll = crtc->config->ddi_pll_sel; uint32_t val; @@ -2369,7 +2369,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) intel_edp_panel_off(intel_dp); } - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port))); else if (INTEL_INFO(dev)->gen < 9) @@ -2937,14 +2937,14 @@ void intel_ddi_pll_init(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; uint32_t val = I915_READ(LCPLL_CTL); - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) skl_shared_dplls_init(dev_priv); else if (IS_BROXTON(dev)) bxt_shared_dplls_init(dev_priv); else hsw_shared_dplls_init(dev_priv); - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { int cdclk_freq; cdclk_freq = dev_priv->display.get_display_clock_speed(dev); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3390fcc..f19b306 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5301,7 +5301,7 @@ static void intel_update_max_cdclk(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; if (limit == SKL_DFSM_CDCLK_LIMIT_675) @@ -9747,7 +9747,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) skylake_get_ddi_pll(dev_priv, port, pipe_config); else if (IS_BROXTON(dev)) bxt_get_ddi_pll(dev_priv, port, pipe_config); @@ -12031,7 +12031,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->dpll_hw_state.pll9, pipe_config->dpll_hw_state.pll10, pipe_config->dpll_hw_state.pcsdw12); - } else if (IS_SKYLAKE(dev)) { + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", pipe_config->ddi_pll_sel, @@ -14090,7 +14090,7 @@ static void intel_setup_outputs(struct drm_device *dev) */ found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; /* WaIgnoreDDIAStrap: skl */ - if (found || IS_SKYLAKE(dev)) + if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) intel_ddi_init(dev, PORT_A); /* DDI B, C and D detection is indicated by the SFUSE_STRAP @@ -14106,7 +14106,7 @@ static void intel_setup_outputs(struct drm_device *dev) /* * On SKL we don't have a way to detect DDI-E so we rely on VBT. */ - if (IS_SKYLAKE(dev) && + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) @@ -14551,7 +14551,7 @@ static void intel_init_display(struct drm_device *dev) } /* Returns the core display clock speed */ - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) dev_priv->display.get_display_clock_speed = skylake_get_display_clock_speed; else if (IS_BROXTON(dev)) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8287df4..1cb1f3f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1023,7 +1023,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) /* On SKL we don't have Aux for port E so we rely on VBT to set * a proper alternate aux channel. */ - if (IS_SKYLAKE(dev) && port == PORT_E) { + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) { switch (info->alternate_aux_channel) { case DP_AUX_B: porte_aux_ctl_reg = DPB_AUX_CH_CTL; @@ -1210,7 +1210,7 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) if (IS_BROXTON(dev)) { *source_rates = bxt_rates; size = ARRAY_SIZE(bxt_rates); - } else if (IS_SKYLAKE(dev)) { + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { *source_rates = skl_rates; size = ARRAY_SIZE(skl_rates); } else { @@ -1530,7 +1530,7 @@ found: &pipe_config->dp_m2_n2); } - if (IS_SKYLAKE(dev) && is_edp(intel_dp)) + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp)) skl_edp_set_pll_config(pipe_config); else if (IS_BROXTON(dev)) /* handled in ddi */; diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index cf47352..fda5fc5 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -581,7 +581,8 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, * reserved range size, so it always assumes the maximum (8mb) is used. * If we enable FBC using a CFB on that memory range we'll get FIFO * underruns, even if that range is not reserved by the BIOS. */ - if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) + if (IS_BROADWELL(dev_priv) || + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; else end = dev_priv->gtt.stolen_usable_size; diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 6d3c6c0..b258a2a 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -143,7 +143,7 @@ static bool get_mocs_settings(struct drm_device *dev, { bool result = false; - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { table->size = ARRAY_SIZE(skylake_mocs_table); table->table = skylake_mocs_table; result = true; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7b110cd..dd63bba 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4567,7 +4567,8 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; - if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { ret = sandybridge_pcode_read(dev_priv, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, &ddcc_status); @@ -4579,7 +4580,7 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) dev_priv->rps.max_freq); } - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { /* Store the frequency values in 16.66 MHZ units, which is the natural hardware unit for SKL */ dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; @@ -4935,7 +4936,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) /* convert DDR frequency from units of 266.6MHz to bandwidth */ min_ring_freq = mult_frac(min_ring_freq, 8, 3); - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; @@ -4953,7 +4954,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) int diff = max_gpu_freq - gpu_freq; unsigned int ia_freq = 0, ring_freq = 0; - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { /* * ring_freq = 2 * GT. ring_freq is in 100MHz units * No floor required for ring frequency on SKL. @@ -6081,7 +6082,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) } else if (INTEL_INFO(dev)->gen >= 9) { gen9_enable_rc6(dev); gen9_enable_rps(dev); - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) __gen6_update_ring_freq(dev); } else if (IS_BROADWELL(dev)) { gen8_enable_rps(dev); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index e50cc88..1017555 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1832,7 +1832,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) set_power_wells(power_domains, hsw_power_wells); } else if (IS_BROADWELL(dev_priv->dev)) { set_power_wells(power_domains, bdw_power_wells); - } else if (IS_SKYLAKE(dev_priv->dev)) { + } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) { set_power_wells(power_domains, skl_power_wells); } else if (IS_BROXTON(dev_priv->dev)) { set_power_wells(power_domains, bxt_power_wells); -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 2/6] drm/i915/kbl: Introduce Kabylake platform defition. 2015-10-27 17:14 ` [PATCH 2/6] drm/i915/kbl: Introduce Kabylake platform defition Rodrigo Vivi @ 2015-10-28 11:39 ` Jani Nikula 2015-10-28 11:16 ` [PATCH] " Rodrigo Vivi 0 siblings, 1 reply; 28+ messages in thread From: Jani Nikula @ 2015-10-28 11:39 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi On Tue, 27 Oct 2015, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > Kabylake is a Intel® Processor containing Intel® HD Graphics > following Skylake. > > It is Gen9p5, so it inherits everything from Skylake. > > First version adding PCI IDs was also defining the platform > with is_skylake=1. But this was bringing even more confusion > to the platform definitions. > > So let's start by adding the platform separated from Skylake > but reusing most of all features, functions etc. Later we > rebase the PCI-ID patch so we don't replace what original > Author did there. > > Few IS_SKYLAKEs if statements are not being covered by this patch > on purpose: > - Workarounds: Kabylake is derivated from Skylake H0 so no > W/As apply here. Also Jani already reworked > the REVID in a way that they will be only > applied to the right platform and stepping > without any extra work required here. > - GuC: A following patch removes Kabylake support with an > explanation: No firmware available yet. > - DMC/CSR: Done in a separated patch since we need to be carefull > and load the version for revision 7 since > Kabylake is Skylake H0. I think in this case the commit message could be cleaner without all of the history. I think you've missed updates to intel_i2c.c. Otherwise LGTM. BR, Jani. > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 16 +++++++----- > drivers/gpu/drm/i915/i915_dma.c | 3 ++- > drivers/gpu/drm/i915/i915_drv.c | 44 ++++++++++++++++++++++++++++----- > drivers/gpu/drm/i915/i915_drv.h | 6 +++-- > drivers/gpu/drm/i915/i915_gem_stolen.c | 3 ++- > drivers/gpu/drm/i915/intel_audio.c | 9 ++++--- > drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++------ > drivers/gpu/drm/i915/intel_display.c | 12 ++++----- > drivers/gpu/drm/i915/intel_dp.c | 6 ++--- > drivers/gpu/drm/i915/intel_fbc.c | 3 ++- > drivers/gpu/drm/i915/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 11 +++++---- > drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- > 13 files changed, 88 insertions(+), 45 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index eca94d0..5125aa5 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1252,18 +1252,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > > max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : > rp_state_cap >> 16) & 0xff; > - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); > + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? > + GEN9_FREQ_SCALER : 1); > seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", > intel_gpu_freq(dev_priv, max_freq)); > > max_freq = (rp_state_cap & 0xff00) >> 8; > - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); > + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? > + GEN9_FREQ_SCALER : 1); > seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", > intel_gpu_freq(dev_priv, max_freq)); > > max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : > rp_state_cap >> 0) & 0xff; > - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); > + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? > + GEN9_FREQ_SCALER : 1); > seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", > intel_gpu_freq(dev_priv, max_freq)); > seq_printf(m, "Max overclocked frequency: %dMHz\n", > @@ -1801,7 +1804,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) > if (ret) > goto out; > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > /* Convert GT frequency to 50 HZ units */ > min_gpu_freq = > dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; > @@ -1821,7 +1824,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) > &ia_freq); > seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", > intel_gpu_freq(dev_priv, (gpu_freq * > - (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))), > + (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? > + GEN9_FREQ_SCALER : 1))), > ((ia_freq >> 0) & 0xff) * 100, > ((ia_freq >> 8) & 0xff) * 100); > } > @@ -5029,7 +5033,7 @@ static void gen9_sseu_device_status(struct drm_device *dev, > > stat->slice_total++; > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > ss_cnt = INTEL_INFO(dev)->subslice_per_slice; > > for (ss = 0; ss < ss_max; ss++) { > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 2336af9..ddd1d46 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -668,7 +668,8 @@ static void gen9_sseu_info_init(struct drm_device *dev) > * supports EU power gating on devices with more than one EU > * pair per subslice. > */ > - info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1)); > + info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && > + (info->slice_total > 1)); > info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); > info->has_eu_pg = (info->eu_per_subslice > 2); > } > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 70f9d3d..c9e80fb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -395,6 +395,36 @@ static const struct intel_device_info intel_broxton_info = { > IVB_CURSOR_OFFSETS, > }; > > +static const struct intel_device_info intel_kabylake_info = { > + .is_preliminary = 1, > + .is_kabylake = 1, > + .gen = 9, > + .num_pipes = 3, > + .need_gfx_hws = 1, .has_hotplug = 1, > + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > + .has_llc = 1, > + .has_ddi = 1, > + .has_fpga_dbg = 1, > + .has_fbc = 1, > + GEN_DEFAULT_PIPEOFFSETS, > + IVB_CURSOR_OFFSETS, > +}; > + > +static const struct intel_device_info intel_kabylake_gt3_info = { > + .is_preliminary = 1, > + .is_kabylake = 1, > + .gen = 9, > + .num_pipes = 3, > + .need_gfx_hws = 1, .has_hotplug = 1, > + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, > + .has_llc = 1, > + .has_ddi = 1, > + .has_fpga_dbg = 1, > + .has_fbc = 1, > + GEN_DEFAULT_PIPEOFFSETS, > + IVB_CURSOR_OFFSETS, > +}; > + > /* > * Make sure any device matches here are from most specific to most > * general. For example, since the Quanta match is based on the subsystem > @@ -464,7 +494,7 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) > } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > ret = PCH_LPT; > DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); > - } else if (IS_SKYLAKE(dev)) { > + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > ret = PCH_SPT; > DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); > } > @@ -527,11 +557,13 @@ void intel_detect_pch(struct drm_device *dev) > } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { > dev_priv->pch_type = PCH_SPT; > DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); > - WARN_ON(!IS_SKYLAKE(dev)); > + WARN_ON(!IS_SKYLAKE(dev) && > + !IS_KABYLAKE(dev)); > } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { > dev_priv->pch_type = PCH_SPT; > DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); > - WARN_ON(!IS_SKYLAKE(dev)); > + WARN_ON(!IS_SKYLAKE(dev) && > + !IS_KABYLAKE(dev)); > } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) { > dev_priv->pch_type = intel_virt_detect_pch(dev); > } else > @@ -839,7 +871,7 @@ static int i915_drm_resume_early(struct drm_device *dev) > > if (IS_BROXTON(dev)) > ret = bxt_resume_prepare(dev_priv); > - else if (IS_SKYLAKE(dev_priv)) > + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > ret = skl_resume_prepare(dev_priv); > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > hsw_disable_pc8(dev_priv); > @@ -1586,7 +1618,7 @@ static int intel_runtime_resume(struct device *device) > > if (IS_BROXTON(dev)) > ret = bxt_resume_prepare(dev_priv); > - else if (IS_SKYLAKE(dev)) > + else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > ret = skl_resume_prepare(dev_priv); > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > hsw_disable_pc8(dev_priv); > @@ -1630,7 +1662,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv) > > if (IS_BROXTON(dev_priv)) > ret = bxt_suspend_complete(dev_priv); > - else if (IS_SKYLAKE(dev_priv)) > + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > ret = skl_suspend_complete(dev_priv); > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > ret = hsw_suspend_complete(dev_priv); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 565e63a..3982d1a 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -766,6 +766,7 @@ struct intel_csr { > func(is_haswell) sep \ > func(is_skylake) sep \ > func(is_broxton) sep \ > + func(is_kabylake) sep \ > func(is_preliminary) sep \ > func(has_fbc) sep \ > func(has_pipe_cxsr) sep \ > @@ -2477,6 +2478,7 @@ struct drm_i915_cmd_table { > #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) > #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) > #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) > +#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) > #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) > #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ > (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) > @@ -2597,10 +2599,10 @@ struct drm_i915_cmd_table { > #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) > #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ > IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ > - IS_SKYLAKE(dev)) > + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ > IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ > - IS_SKYLAKE(dev)) > + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) > #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) > > diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c > index cdacf3f..598ed2f 100644 > --- a/drivers/gpu/drm/i915/i915_gem_stolen.c > +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c > @@ -433,7 +433,8 @@ int i915_gem_init_stolen(struct drm_device *dev) > &reserved_size); > break; > default: > - if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) > + if (IS_BROADWELL(dev_priv) || > + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev)) > bdw_get_stolen_reserved(dev_priv, &reserved_base, > &reserved_size); > else > diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c > index 4dccd9b..63d4706 100644 > --- a/drivers/gpu/drm/i915/intel_audio.c > +++ b/drivers/gpu/drm/i915/intel_audio.c > @@ -591,7 +591,7 @@ static void i915_audio_component_codec_wake_override(struct device *dev, > struct drm_i915_private *dev_priv = dev_to_i915(dev); > u32 tmp; > > - if (!IS_SKYLAKE(dev_priv)) > + if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) > return; > > /* > @@ -642,10 +642,11 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, > u32 tmp; > int n; > > - /* HSW, BDW SKL need this fix */ > + /* HSW, BDW, SKL, KBL need this fix */ > if (!IS_SKYLAKE(dev_priv) && > - !IS_BROADWELL(dev_priv) && > - !IS_HASWELL(dev_priv)) > + !IS_KABYLAKE(dev_priv) && > + !IS_BROADWELL(dev_priv) && > + !IS_HASWELL(dev_priv)) > return 0; > > mutex_lock(&dev_priv->av_mutex); > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index a163741..8dd9fae 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -448,7 +448,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, > bxt_ddi_vswing_sequence(dev, hdmi_level, port, > INTEL_OUTPUT_HDMI); > return; > - } else if (IS_SKYLAKE(dev)) { > + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > ddi_translations_fdi = NULL; > ddi_translations_dp = > skl_get_buf_trans_dp(dev, &n_dp_entries); > @@ -1184,7 +1184,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder, > > if (INTEL_INFO(dev)->gen <= 8) > hsw_ddi_clock_get(encoder, pipe_config); > - else if (IS_SKYLAKE(dev)) > + else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > skl_ddi_clock_get(encoder, pipe_config); > else if (IS_BROXTON(dev)) > bxt_ddi_clock_get(encoder, pipe_config); > @@ -1768,7 +1768,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, > struct intel_encoder *intel_encoder = > intel_ddi_get_crtc_new_encoder(crtc_state); > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > return skl_ddi_pll_select(intel_crtc, crtc_state, > intel_encoder); > else if (IS_BROXTON(dev)) > @@ -2251,7 +2251,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) > > level = translate_signal_level(signal_levels); > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > skl_ddi_set_iboost(dev, level, port, encoder->type); > else if (IS_BROXTON(dev)) > bxt_ddi_vswing_sequence(dev, level, port, encoder->type); > @@ -2274,7 +2274,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) > intel_edp_panel_on(intel_dp); > } > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > uint32_t dpll = crtc->config->ddi_pll_sel; > uint32_t val; > > @@ -2369,7 +2369,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) > intel_edp_panel_off(intel_dp); > } > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | > DPLL_CTRL2_DDI_CLK_OFF(port))); > else if (INTEL_INFO(dev)->gen < 9) > @@ -2937,14 +2937,14 @@ void intel_ddi_pll_init(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t val = I915_READ(LCPLL_CTL); > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > skl_shared_dplls_init(dev_priv); > else if (IS_BROXTON(dev)) > bxt_shared_dplls_init(dev_priv); > else > hsw_shared_dplls_init(dev_priv); > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > int cdclk_freq; > > cdclk_freq = dev_priv->display.get_display_clock_speed(dev); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 3390fcc..f19b306 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5301,7 +5301,7 @@ static void intel_update_max_cdclk(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; > > if (limit == SKL_DFSM_CDCLK_LIMIT_675) > @@ -9747,7 +9747,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, > > port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > skylake_get_ddi_pll(dev_priv, port, pipe_config); > else if (IS_BROXTON(dev)) > bxt_get_ddi_pll(dev_priv, port, pipe_config); > @@ -12031,7 +12031,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, > pipe_config->dpll_hw_state.pll9, > pipe_config->dpll_hw_state.pll10, > pipe_config->dpll_hw_state.pcsdw12); > - } else if (IS_SKYLAKE(dev)) { > + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " > "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", > pipe_config->ddi_pll_sel, > @@ -14090,7 +14090,7 @@ static void intel_setup_outputs(struct drm_device *dev) > */ > found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; > /* WaIgnoreDDIAStrap: skl */ > - if (found || IS_SKYLAKE(dev)) > + if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > intel_ddi_init(dev, PORT_A); > > /* DDI B, C and D detection is indicated by the SFUSE_STRAP > @@ -14106,7 +14106,7 @@ static void intel_setup_outputs(struct drm_device *dev) > /* > * On SKL we don't have a way to detect DDI-E so we rely on VBT. > */ > - if (IS_SKYLAKE(dev) && > + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && > (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || > dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || > dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) > @@ -14551,7 +14551,7 @@ static void intel_init_display(struct drm_device *dev) > } > > /* Returns the core display clock speed */ > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > dev_priv->display.get_display_clock_speed = > skylake_get_display_clock_speed; > else if (IS_BROXTON(dev)) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 8287df4..1cb1f3f 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1023,7 +1023,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) > /* On SKL we don't have Aux for port E so we rely on VBT to set > * a proper alternate aux channel. > */ > - if (IS_SKYLAKE(dev) && port == PORT_E) { > + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) { > switch (info->alternate_aux_channel) { > case DP_AUX_B: > porte_aux_ctl_reg = DPB_AUX_CH_CTL; > @@ -1210,7 +1210,7 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) > if (IS_BROXTON(dev)) { > *source_rates = bxt_rates; > size = ARRAY_SIZE(bxt_rates); > - } else if (IS_SKYLAKE(dev)) { > + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > *source_rates = skl_rates; > size = ARRAY_SIZE(skl_rates); > } else { > @@ -1530,7 +1530,7 @@ found: > &pipe_config->dp_m2_n2); > } > > - if (IS_SKYLAKE(dev) && is_edp(intel_dp)) > + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp)) > skl_edp_set_pll_config(pipe_config); > else if (IS_BROXTON(dev)) > /* handled in ddi */; > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > index cf47352..fda5fc5 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -581,7 +581,8 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, > * reserved range size, so it always assumes the maximum (8mb) is used. > * If we enable FBC using a CFB on that memory range we'll get FIFO > * underruns, even if that range is not reserved by the BIOS. */ > - if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) > + if (IS_BROADWELL(dev_priv) || > + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; > else > end = dev_priv->gtt.stolen_usable_size; > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c > index 6d3c6c0..b258a2a 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -143,7 +143,7 @@ static bool get_mocs_settings(struct drm_device *dev, > { > bool result = false; > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > table->size = ARRAY_SIZE(skylake_mocs_table); > table->table = skylake_mocs_table; > result = true; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 7b110cd..dd63bba 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4567,7 +4567,8 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) > dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; > > dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; > - if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { > + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || > + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > ret = sandybridge_pcode_read(dev_priv, > HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, > &ddcc_status); > @@ -4579,7 +4580,7 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) > dev_priv->rps.max_freq); > } > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > /* Store the frequency values in 16.66 MHZ units, which is > the natural hardware unit for SKL */ > dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; > @@ -4935,7 +4936,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) > /* convert DDR frequency from units of 266.6MHz to bandwidth */ > min_ring_freq = mult_frac(min_ring_freq, 8, 3); > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > /* Convert GT frequency to 50 HZ units */ > min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; > max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; > @@ -4953,7 +4954,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) > int diff = max_gpu_freq - gpu_freq; > unsigned int ia_freq = 0, ring_freq = 0; > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > /* > * ring_freq = 2 * GT. ring_freq is in 100MHz units > * No floor required for ring frequency on SKL. > @@ -6081,7 +6082,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) > } else if (INTEL_INFO(dev)->gen >= 9) { > gen9_enable_rc6(dev); > gen9_enable_rps(dev); > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > __gen6_update_ring_freq(dev); > } else if (IS_BROADWELL(dev)) { > gen8_enable_rps(dev); > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index e50cc88..1017555 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -1832,7 +1832,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) > set_power_wells(power_domains, hsw_power_wells); > } else if (IS_BROADWELL(dev_priv->dev)) { > set_power_wells(power_domains, bdw_power_wells); > - } else if (IS_SKYLAKE(dev_priv->dev)) { > + } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) { > set_power_wells(power_domains, skl_power_wells); > } else if (IS_BROXTON(dev_priv->dev)) { > set_power_wells(power_domains, bxt_power_wells); -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH] drm/i915/kbl: Introduce Kabylake platform defition. 2015-10-28 11:39 ` Jani Nikula @ 2015-10-28 11:16 ` Rodrigo Vivi 2015-10-28 19:18 ` Jani Nikula 2015-10-28 19:31 ` Chris Wilson 0 siblings, 2 replies; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-28 11:16 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi Kabylake is a Intel® Processor containing Intel® HD Graphics following Skylake. It is Gen9p5, so it inherits everything from Skylake. Let's start by adding the platform separated from Skylake but reusing most of all features, functions etc. Later we rebase the PCI-ID patch without is_skylake=1 so we don't replace what original Author did there. Few IS_SKYLAKEs if statements are not being covered by this patch on purpose: - Workarounds: Kabylake is derivated from Skylake H0 so no W/As apply here. - GuC: A following patch removes Kabylake support with an explanation: No firmware available yet. - DMC/CSR: Done in a separated patch since we need to be carefull and load the version for revision 7 since Kabylake is Skylake H0. v2: relative cleaner commit message and added the missed IS_KABYLAKE to intel_i2c.c as pointed out by Jani. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 16 +++++++----- drivers/gpu/drm/i915/i915_dma.c | 3 ++- drivers/gpu/drm/i915/i915_drv.c | 44 ++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/i915_drv.h | 6 +++-- drivers/gpu/drm/i915/i915_gem_stolen.c | 3 ++- drivers/gpu/drm/i915/intel_audio.c | 9 ++++--- drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++------ drivers/gpu/drm/i915/intel_display.c | 12 ++++----- drivers/gpu/drm/i915/intel_dp.c | 6 ++--- drivers/gpu/drm/i915/intel_fbc.c | 3 ++- drivers/gpu/drm/i915/intel_i2c.c | 4 +-- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 11 +++++---- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- 14 files changed, 90 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index eca94d0..5125aa5 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1252,18 +1252,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused) max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : rp_state_cap >> 16) & 0xff; - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? + GEN9_FREQ_SCALER : 1); seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); max_freq = (rp_state_cap & 0xff00) >> 8; - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? + GEN9_FREQ_SCALER : 1); seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : rp_state_cap >> 0) & 0xff; - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? + GEN9_FREQ_SCALER : 1); seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); seq_printf(m, "Max overclocked frequency: %dMHz\n", @@ -1801,7 +1804,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) if (ret) goto out; - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq = dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; @@ -1821,7 +1824,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) &ia_freq); seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", intel_gpu_freq(dev_priv, (gpu_freq * - (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))), + (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? + GEN9_FREQ_SCALER : 1))), ((ia_freq >> 0) & 0xff) * 100, ((ia_freq >> 8) & 0xff) * 100); } @@ -5029,7 +5033,7 @@ static void gen9_sseu_device_status(struct drm_device *dev, stat->slice_total++; - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) ss_cnt = INTEL_INFO(dev)->subslice_per_slice; for (ss = 0; ss < ss_max; ss++) { diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 2336af9..ddd1d46 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -668,7 +668,8 @@ static void gen9_sseu_info_init(struct drm_device *dev) * supports EU power gating on devices with more than one EU * pair per subslice. */ - info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1)); + info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && + (info->slice_total > 1)); info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); info->has_eu_pg = (info->eu_per_subslice > 2); } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 70f9d3d..c9e80fb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -395,6 +395,36 @@ static const struct intel_device_info intel_broxton_info = { IVB_CURSOR_OFFSETS, }; +static const struct intel_device_info intel_kabylake_info = { + .is_preliminary = 1, + .is_kabylake = 1, + .gen = 9, + .num_pipes = 3, + .need_gfx_hws = 1, .has_hotplug = 1, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .has_llc = 1, + .has_ddi = 1, + .has_fpga_dbg = 1, + .has_fbc = 1, + GEN_DEFAULT_PIPEOFFSETS, + IVB_CURSOR_OFFSETS, +}; + +static const struct intel_device_info intel_kabylake_gt3_info = { + .is_preliminary = 1, + .is_kabylake = 1, + .gen = 9, + .num_pipes = 3, + .need_gfx_hws = 1, .has_hotplug = 1, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .has_llc = 1, + .has_ddi = 1, + .has_fpga_dbg = 1, + .has_fbc = 1, + GEN_DEFAULT_PIPEOFFSETS, + IVB_CURSOR_OFFSETS, +}; + /* * Make sure any device matches here are from most specific to most * general. For example, since the Quanta match is based on the subsystem @@ -464,7 +494,7 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { ret = PCH_LPT; DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); - } else if (IS_SKYLAKE(dev)) { + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { ret = PCH_SPT; DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); } @@ -527,11 +557,13 @@ void intel_detect_pch(struct drm_device *dev) } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_SPT; DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); - WARN_ON(!IS_SKYLAKE(dev)); + WARN_ON(!IS_SKYLAKE(dev) && + !IS_KABYLAKE(dev)); } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_SPT; DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); - WARN_ON(!IS_SKYLAKE(dev)); + WARN_ON(!IS_SKYLAKE(dev) && + !IS_KABYLAKE(dev)); } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) { dev_priv->pch_type = intel_virt_detect_pch(dev); } else @@ -839,7 +871,7 @@ static int i915_drm_resume_early(struct drm_device *dev) if (IS_BROXTON(dev)) ret = bxt_resume_prepare(dev_priv); - else if (IS_SKYLAKE(dev_priv)) + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ret = skl_resume_prepare(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hsw_disable_pc8(dev_priv); @@ -1586,7 +1618,7 @@ static int intel_runtime_resume(struct device *device) if (IS_BROXTON(dev)) ret = bxt_resume_prepare(dev_priv); - else if (IS_SKYLAKE(dev)) + else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) ret = skl_resume_prepare(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hsw_disable_pc8(dev_priv); @@ -1630,7 +1662,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv) if (IS_BROXTON(dev_priv)) ret = bxt_suspend_complete(dev_priv); - else if (IS_SKYLAKE(dev_priv)) + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ret = skl_suspend_complete(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) ret = hsw_suspend_complete(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 565e63a..3982d1a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -766,6 +766,7 @@ struct intel_csr { func(is_haswell) sep \ func(is_skylake) sep \ func(is_broxton) sep \ + func(is_kabylake) sep \ func(is_preliminary) sep \ func(has_fbc) sep \ func(has_pipe_cxsr) sep \ @@ -2477,6 +2478,7 @@ struct drm_i915_cmd_table { #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) +#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) @@ -2597,10 +2599,10 @@ struct drm_i915_cmd_table { #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ - IS_SKYLAKE(dev)) + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ - IS_SKYLAKE(dev)) + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index cdacf3f..598ed2f 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -433,7 +433,8 @@ int i915_gem_init_stolen(struct drm_device *dev) &reserved_size); break; default: - if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) + if (IS_BROADWELL(dev_priv) || + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev)) bdw_get_stolen_reserved(dev_priv, &reserved_base, &reserved_size); else diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 4dccd9b..63d4706 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -591,7 +591,7 @@ static void i915_audio_component_codec_wake_override(struct device *dev, struct drm_i915_private *dev_priv = dev_to_i915(dev); u32 tmp; - if (!IS_SKYLAKE(dev_priv)) + if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) return; /* @@ -642,10 +642,11 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, u32 tmp; int n; - /* HSW, BDW SKL need this fix */ + /* HSW, BDW, SKL, KBL need this fix */ if (!IS_SKYLAKE(dev_priv) && - !IS_BROADWELL(dev_priv) && - !IS_HASWELL(dev_priv)) + !IS_KABYLAKE(dev_priv) && + !IS_BROADWELL(dev_priv) && + !IS_HASWELL(dev_priv)) return 0; mutex_lock(&dev_priv->av_mutex); diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a163741..8dd9fae 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -448,7 +448,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bxt_ddi_vswing_sequence(dev, hdmi_level, port, INTEL_OUTPUT_HDMI); return; - } else if (IS_SKYLAKE(dev)) { + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { ddi_translations_fdi = NULL; ddi_translations_dp = skl_get_buf_trans_dp(dev, &n_dp_entries); @@ -1184,7 +1184,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder, if (INTEL_INFO(dev)->gen <= 8) hsw_ddi_clock_get(encoder, pipe_config); - else if (IS_SKYLAKE(dev)) + else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) skl_ddi_clock_get(encoder, pipe_config); else if (IS_BROXTON(dev)) bxt_ddi_clock_get(encoder, pipe_config); @@ -1768,7 +1768,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, struct intel_encoder *intel_encoder = intel_ddi_get_crtc_new_encoder(crtc_state); - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) return skl_ddi_pll_select(intel_crtc, crtc_state, intel_encoder); else if (IS_BROXTON(dev)) @@ -2251,7 +2251,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) level = translate_signal_level(signal_levels); - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) skl_ddi_set_iboost(dev, level, port, encoder->type); else if (IS_BROXTON(dev)) bxt_ddi_vswing_sequence(dev, level, port, encoder->type); @@ -2274,7 +2274,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) intel_edp_panel_on(intel_dp); } - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { uint32_t dpll = crtc->config->ddi_pll_sel; uint32_t val; @@ -2369,7 +2369,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) intel_edp_panel_off(intel_dp); } - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port))); else if (INTEL_INFO(dev)->gen < 9) @@ -2937,14 +2937,14 @@ void intel_ddi_pll_init(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; uint32_t val = I915_READ(LCPLL_CTL); - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) skl_shared_dplls_init(dev_priv); else if (IS_BROXTON(dev)) bxt_shared_dplls_init(dev_priv); else hsw_shared_dplls_init(dev_priv); - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { int cdclk_freq; cdclk_freq = dev_priv->display.get_display_clock_speed(dev); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3390fcc..f19b306 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5301,7 +5301,7 @@ static void intel_update_max_cdclk(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; if (limit == SKL_DFSM_CDCLK_LIMIT_675) @@ -9747,7 +9747,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) skylake_get_ddi_pll(dev_priv, port, pipe_config); else if (IS_BROXTON(dev)) bxt_get_ddi_pll(dev_priv, port, pipe_config); @@ -12031,7 +12031,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->dpll_hw_state.pll9, pipe_config->dpll_hw_state.pll10, pipe_config->dpll_hw_state.pcsdw12); - } else if (IS_SKYLAKE(dev)) { + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", pipe_config->ddi_pll_sel, @@ -14090,7 +14090,7 @@ static void intel_setup_outputs(struct drm_device *dev) */ found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; /* WaIgnoreDDIAStrap: skl */ - if (found || IS_SKYLAKE(dev)) + if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) intel_ddi_init(dev, PORT_A); /* DDI B, C and D detection is indicated by the SFUSE_STRAP @@ -14106,7 +14106,7 @@ static void intel_setup_outputs(struct drm_device *dev) /* * On SKL we don't have a way to detect DDI-E so we rely on VBT. */ - if (IS_SKYLAKE(dev) && + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) @@ -14551,7 +14551,7 @@ static void intel_init_display(struct drm_device *dev) } /* Returns the core display clock speed */ - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) dev_priv->display.get_display_clock_speed = skylake_get_display_clock_speed; else if (IS_BROXTON(dev)) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8287df4..1cb1f3f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1023,7 +1023,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) /* On SKL we don't have Aux for port E so we rely on VBT to set * a proper alternate aux channel. */ - if (IS_SKYLAKE(dev) && port == PORT_E) { + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) { switch (info->alternate_aux_channel) { case DP_AUX_B: porte_aux_ctl_reg = DPB_AUX_CH_CTL; @@ -1210,7 +1210,7 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) if (IS_BROXTON(dev)) { *source_rates = bxt_rates; size = ARRAY_SIZE(bxt_rates); - } else if (IS_SKYLAKE(dev)) { + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { *source_rates = skl_rates; size = ARRAY_SIZE(skl_rates); } else { @@ -1530,7 +1530,7 @@ found: &pipe_config->dp_m2_n2); } - if (IS_SKYLAKE(dev) && is_edp(intel_dp)) + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp)) skl_edp_set_pll_config(pipe_config); else if (IS_BROXTON(dev)) /* handled in ddi */; diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index cf47352..fda5fc5 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -581,7 +581,8 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, * reserved range size, so it always assumes the maximum (8mb) is used. * If we enable FBC using a CFB on that memory range we'll get FIFO * underruns, even if that range is not reserved by the BIOS. */ - if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) + if (IS_BROADWELL(dev_priv) || + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; else end = dev_priv->gtt.stolen_usable_size; diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 1369fc4..bd58da0 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -74,7 +74,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, { if (IS_BROXTON(dev_priv)) return &gmbus_pins_bxt[pin]; - else if (IS_SKYLAKE(dev_priv)) + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) return &gmbus_pins_skl[pin]; else if (IS_BROADWELL(dev_priv)) return &gmbus_pins_bdw[pin]; @@ -89,7 +89,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, if (IS_BROXTON(dev_priv)) size = ARRAY_SIZE(gmbus_pins_bxt); - else if (IS_SKYLAKE(dev_priv)) + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) size = ARRAY_SIZE(gmbus_pins_skl); else if (IS_BROADWELL(dev_priv)) size = ARRAY_SIZE(gmbus_pins_bdw); diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 6d3c6c0..b258a2a 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -143,7 +143,7 @@ static bool get_mocs_settings(struct drm_device *dev, { bool result = false; - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { table->size = ARRAY_SIZE(skylake_mocs_table); table->table = skylake_mocs_table; result = true; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7b110cd..dd63bba 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4567,7 +4567,8 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; - if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { ret = sandybridge_pcode_read(dev_priv, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, &ddcc_status); @@ -4579,7 +4580,7 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) dev_priv->rps.max_freq); } - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { /* Store the frequency values in 16.66 MHZ units, which is the natural hardware unit for SKL */ dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; @@ -4935,7 +4936,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) /* convert DDR frequency from units of 266.6MHz to bandwidth */ min_ring_freq = mult_frac(min_ring_freq, 8, 3); - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; @@ -4953,7 +4954,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) int diff = max_gpu_freq - gpu_freq; unsigned int ia_freq = 0, ring_freq = 0; - if (IS_SKYLAKE(dev)) { + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { /* * ring_freq = 2 * GT. ring_freq is in 100MHz units * No floor required for ring frequency on SKL. @@ -6081,7 +6082,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) } else if (INTEL_INFO(dev)->gen >= 9) { gen9_enable_rc6(dev); gen9_enable_rps(dev); - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) __gen6_update_ring_freq(dev); } else if (IS_BROADWELL(dev)) { gen8_enable_rps(dev); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index e50cc88..1017555 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1832,7 +1832,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) set_power_wells(power_domains, hsw_power_wells); } else if (IS_BROADWELL(dev_priv->dev)) { set_power_wells(power_domains, bdw_power_wells); - } else if (IS_SKYLAKE(dev_priv->dev)) { + } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) { set_power_wells(power_domains, skl_power_wells); } else if (IS_BROXTON(dev_priv->dev)) { set_power_wells(power_domains, bxt_power_wells); -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH] drm/i915/kbl: Introduce Kabylake platform defition. 2015-10-28 11:16 ` [PATCH] " Rodrigo Vivi @ 2015-10-28 19:18 ` Jani Nikula 2015-10-28 19:31 ` Chris Wilson 1 sibling, 0 replies; 28+ messages in thread From: Jani Nikula @ 2015-10-28 19:18 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi On Wed, 28 Oct 2015, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > Kabylake is a Intel® Processor containing Intel® HD Graphics > following Skylake. > > It is Gen9p5, so it inherits everything from Skylake. > > Let's start by adding the platform separated from Skylake > but reusing most of all features, functions etc. Later we > rebase the PCI-ID patch without is_skylake=1 > so we don't replace what original Author did there. > > Few IS_SKYLAKEs if statements are not being covered by this patch > on purpose: > - Workarounds: Kabylake is derivated from Skylake H0 so no > W/As apply here. > - GuC: A following patch removes Kabylake support with an > explanation: No firmware available yet. > - DMC/CSR: Done in a separated patch since we need to be carefull > and load the version for revision 7 since > Kabylake is Skylake H0. > > v2: relative cleaner commit message and added the missed > IS_KABYLAKE to intel_i2c.c as pointed out by Jani. > > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 16 +++++++----- > drivers/gpu/drm/i915/i915_dma.c | 3 ++- > drivers/gpu/drm/i915/i915_drv.c | 44 ++++++++++++++++++++++++++++----- > drivers/gpu/drm/i915/i915_drv.h | 6 +++-- > drivers/gpu/drm/i915/i915_gem_stolen.c | 3 ++- > drivers/gpu/drm/i915/intel_audio.c | 9 ++++--- > drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++------ > drivers/gpu/drm/i915/intel_display.c | 12 ++++----- > drivers/gpu/drm/i915/intel_dp.c | 6 ++--- > drivers/gpu/drm/i915/intel_fbc.c | 3 ++- > drivers/gpu/drm/i915/intel_i2c.c | 4 +-- > drivers/gpu/drm/i915/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 11 +++++---- > drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- > 14 files changed, 90 insertions(+), 47 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index eca94d0..5125aa5 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1252,18 +1252,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > > max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : > rp_state_cap >> 16) & 0xff; > - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); > + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? > + GEN9_FREQ_SCALER : 1); > seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", > intel_gpu_freq(dev_priv, max_freq)); > > max_freq = (rp_state_cap & 0xff00) >> 8; > - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); > + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? > + GEN9_FREQ_SCALER : 1); > seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", > intel_gpu_freq(dev_priv, max_freq)); > > max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : > rp_state_cap >> 0) & 0xff; > - max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); > + max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? > + GEN9_FREQ_SCALER : 1); > seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", > intel_gpu_freq(dev_priv, max_freq)); > seq_printf(m, "Max overclocked frequency: %dMHz\n", > @@ -1801,7 +1804,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) > if (ret) > goto out; > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > /* Convert GT frequency to 50 HZ units */ > min_gpu_freq = > dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; > @@ -1821,7 +1824,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) > &ia_freq); > seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", > intel_gpu_freq(dev_priv, (gpu_freq * > - (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))), > + (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? > + GEN9_FREQ_SCALER : 1))), > ((ia_freq >> 0) & 0xff) * 100, > ((ia_freq >> 8) & 0xff) * 100); > } > @@ -5029,7 +5033,7 @@ static void gen9_sseu_device_status(struct drm_device *dev, > > stat->slice_total++; > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > ss_cnt = INTEL_INFO(dev)->subslice_per_slice; > > for (ss = 0; ss < ss_max; ss++) { > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 2336af9..ddd1d46 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -668,7 +668,8 @@ static void gen9_sseu_info_init(struct drm_device *dev) > * supports EU power gating on devices with more than one EU > * pair per subslice. > */ > - info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1)); > + info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && > + (info->slice_total > 1)); > info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); > info->has_eu_pg = (info->eu_per_subslice > 2); > } > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 70f9d3d..c9e80fb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -395,6 +395,36 @@ static const struct intel_device_info intel_broxton_info = { > IVB_CURSOR_OFFSETS, > }; > > +static const struct intel_device_info intel_kabylake_info = { > + .is_preliminary = 1, > + .is_kabylake = 1, > + .gen = 9, > + .num_pipes = 3, > + .need_gfx_hws = 1, .has_hotplug = 1, > + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > + .has_llc = 1, > + .has_ddi = 1, > + .has_fpga_dbg = 1, > + .has_fbc = 1, > + GEN_DEFAULT_PIPEOFFSETS, > + IVB_CURSOR_OFFSETS, > +}; > + > +static const struct intel_device_info intel_kabylake_gt3_info = { > + .is_preliminary = 1, > + .is_kabylake = 1, > + .gen = 9, > + .num_pipes = 3, > + .need_gfx_hws = 1, .has_hotplug = 1, > + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, > + .has_llc = 1, > + .has_ddi = 1, > + .has_fpga_dbg = 1, > + .has_fbc = 1, > + GEN_DEFAULT_PIPEOFFSETS, > + IVB_CURSOR_OFFSETS, > +}; > + > /* > * Make sure any device matches here are from most specific to most > * general. For example, since the Quanta match is based on the subsystem > @@ -464,7 +494,7 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) > } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > ret = PCH_LPT; > DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); > - } else if (IS_SKYLAKE(dev)) { > + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > ret = PCH_SPT; > DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); > } > @@ -527,11 +557,13 @@ void intel_detect_pch(struct drm_device *dev) > } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { > dev_priv->pch_type = PCH_SPT; > DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); > - WARN_ON(!IS_SKYLAKE(dev)); > + WARN_ON(!IS_SKYLAKE(dev) && > + !IS_KABYLAKE(dev)); > } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { > dev_priv->pch_type = PCH_SPT; > DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); > - WARN_ON(!IS_SKYLAKE(dev)); > + WARN_ON(!IS_SKYLAKE(dev) && > + !IS_KABYLAKE(dev)); > } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) { > dev_priv->pch_type = intel_virt_detect_pch(dev); > } else > @@ -839,7 +871,7 @@ static int i915_drm_resume_early(struct drm_device *dev) > > if (IS_BROXTON(dev)) > ret = bxt_resume_prepare(dev_priv); > - else if (IS_SKYLAKE(dev_priv)) > + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > ret = skl_resume_prepare(dev_priv); > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > hsw_disable_pc8(dev_priv); > @@ -1586,7 +1618,7 @@ static int intel_runtime_resume(struct device *device) > > if (IS_BROXTON(dev)) > ret = bxt_resume_prepare(dev_priv); > - else if (IS_SKYLAKE(dev)) > + else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > ret = skl_resume_prepare(dev_priv); > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > hsw_disable_pc8(dev_priv); > @@ -1630,7 +1662,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv) > > if (IS_BROXTON(dev_priv)) > ret = bxt_suspend_complete(dev_priv); > - else if (IS_SKYLAKE(dev_priv)) > + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > ret = skl_suspend_complete(dev_priv); > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > ret = hsw_suspend_complete(dev_priv); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 565e63a..3982d1a 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -766,6 +766,7 @@ struct intel_csr { > func(is_haswell) sep \ > func(is_skylake) sep \ > func(is_broxton) sep \ > + func(is_kabylake) sep \ > func(is_preliminary) sep \ > func(has_fbc) sep \ > func(has_pipe_cxsr) sep \ > @@ -2477,6 +2478,7 @@ struct drm_i915_cmd_table { > #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) > #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) > #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) > +#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) > #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) > #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ > (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) > @@ -2597,10 +2599,10 @@ struct drm_i915_cmd_table { > #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) > #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ > IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ > - IS_SKYLAKE(dev)) > + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ > IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ > - IS_SKYLAKE(dev)) > + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) > #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) > > diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c > index cdacf3f..598ed2f 100644 > --- a/drivers/gpu/drm/i915/i915_gem_stolen.c > +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c > @@ -433,7 +433,8 @@ int i915_gem_init_stolen(struct drm_device *dev) > &reserved_size); > break; > default: > - if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) > + if (IS_BROADWELL(dev_priv) || > + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev)) > bdw_get_stolen_reserved(dev_priv, &reserved_base, > &reserved_size); > else > diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c > index 4dccd9b..63d4706 100644 > --- a/drivers/gpu/drm/i915/intel_audio.c > +++ b/drivers/gpu/drm/i915/intel_audio.c > @@ -591,7 +591,7 @@ static void i915_audio_component_codec_wake_override(struct device *dev, > struct drm_i915_private *dev_priv = dev_to_i915(dev); > u32 tmp; > > - if (!IS_SKYLAKE(dev_priv)) > + if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) > return; > > /* > @@ -642,10 +642,11 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, > u32 tmp; > int n; > > - /* HSW, BDW SKL need this fix */ > + /* HSW, BDW, SKL, KBL need this fix */ > if (!IS_SKYLAKE(dev_priv) && > - !IS_BROADWELL(dev_priv) && > - !IS_HASWELL(dev_priv)) > + !IS_KABYLAKE(dev_priv) && > + !IS_BROADWELL(dev_priv) && > + !IS_HASWELL(dev_priv)) > return 0; > > mutex_lock(&dev_priv->av_mutex); > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index a163741..8dd9fae 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -448,7 +448,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, > bxt_ddi_vswing_sequence(dev, hdmi_level, port, > INTEL_OUTPUT_HDMI); > return; > - } else if (IS_SKYLAKE(dev)) { > + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > ddi_translations_fdi = NULL; > ddi_translations_dp = > skl_get_buf_trans_dp(dev, &n_dp_entries); > @@ -1184,7 +1184,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder, > > if (INTEL_INFO(dev)->gen <= 8) > hsw_ddi_clock_get(encoder, pipe_config); > - else if (IS_SKYLAKE(dev)) > + else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > skl_ddi_clock_get(encoder, pipe_config); > else if (IS_BROXTON(dev)) > bxt_ddi_clock_get(encoder, pipe_config); > @@ -1768,7 +1768,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, > struct intel_encoder *intel_encoder = > intel_ddi_get_crtc_new_encoder(crtc_state); > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > return skl_ddi_pll_select(intel_crtc, crtc_state, > intel_encoder); > else if (IS_BROXTON(dev)) > @@ -2251,7 +2251,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) > > level = translate_signal_level(signal_levels); > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > skl_ddi_set_iboost(dev, level, port, encoder->type); > else if (IS_BROXTON(dev)) > bxt_ddi_vswing_sequence(dev, level, port, encoder->type); > @@ -2274,7 +2274,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) > intel_edp_panel_on(intel_dp); > } > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > uint32_t dpll = crtc->config->ddi_pll_sel; > uint32_t val; > > @@ -2369,7 +2369,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) > intel_edp_panel_off(intel_dp); > } > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | > DPLL_CTRL2_DDI_CLK_OFF(port))); > else if (INTEL_INFO(dev)->gen < 9) > @@ -2937,14 +2937,14 @@ void intel_ddi_pll_init(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t val = I915_READ(LCPLL_CTL); > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > skl_shared_dplls_init(dev_priv); > else if (IS_BROXTON(dev)) > bxt_shared_dplls_init(dev_priv); > else > hsw_shared_dplls_init(dev_priv); > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > int cdclk_freq; > > cdclk_freq = dev_priv->display.get_display_clock_speed(dev); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 3390fcc..f19b306 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5301,7 +5301,7 @@ static void intel_update_max_cdclk(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; > > if (limit == SKL_DFSM_CDCLK_LIMIT_675) > @@ -9747,7 +9747,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, > > port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; > > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > skylake_get_ddi_pll(dev_priv, port, pipe_config); > else if (IS_BROXTON(dev)) > bxt_get_ddi_pll(dev_priv, port, pipe_config); > @@ -12031,7 +12031,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, > pipe_config->dpll_hw_state.pll9, > pipe_config->dpll_hw_state.pll10, > pipe_config->dpll_hw_state.pcsdw12); > - } else if (IS_SKYLAKE(dev)) { > + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " > "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", > pipe_config->ddi_pll_sel, > @@ -14090,7 +14090,7 @@ static void intel_setup_outputs(struct drm_device *dev) > */ > found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; > /* WaIgnoreDDIAStrap: skl */ > - if (found || IS_SKYLAKE(dev)) > + if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > intel_ddi_init(dev, PORT_A); > > /* DDI B, C and D detection is indicated by the SFUSE_STRAP > @@ -14106,7 +14106,7 @@ static void intel_setup_outputs(struct drm_device *dev) > /* > * On SKL we don't have a way to detect DDI-E so we rely on VBT. > */ > - if (IS_SKYLAKE(dev) && > + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && > (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || > dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || > dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) > @@ -14551,7 +14551,7 @@ static void intel_init_display(struct drm_device *dev) > } > > /* Returns the core display clock speed */ > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > dev_priv->display.get_display_clock_speed = > skylake_get_display_clock_speed; > else if (IS_BROXTON(dev)) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 8287df4..1cb1f3f 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1023,7 +1023,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) > /* On SKL we don't have Aux for port E so we rely on VBT to set > * a proper alternate aux channel. > */ > - if (IS_SKYLAKE(dev) && port == PORT_E) { > + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) { > switch (info->alternate_aux_channel) { > case DP_AUX_B: > porte_aux_ctl_reg = DPB_AUX_CH_CTL; > @@ -1210,7 +1210,7 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) > if (IS_BROXTON(dev)) { > *source_rates = bxt_rates; > size = ARRAY_SIZE(bxt_rates); > - } else if (IS_SKYLAKE(dev)) { > + } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > *source_rates = skl_rates; > size = ARRAY_SIZE(skl_rates); > } else { > @@ -1530,7 +1530,7 @@ found: > &pipe_config->dp_m2_n2); > } > > - if (IS_SKYLAKE(dev) && is_edp(intel_dp)) > + if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp)) > skl_edp_set_pll_config(pipe_config); > else if (IS_BROXTON(dev)) > /* handled in ddi */; > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > index cf47352..fda5fc5 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -581,7 +581,8 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, > * reserved range size, so it always assumes the maximum (8mb) is used. > * If we enable FBC using a CFB on that memory range we'll get FIFO > * underruns, even if that range is not reserved by the BIOS. */ > - if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) > + if (IS_BROADWELL(dev_priv) || > + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; > else > end = dev_priv->gtt.stolen_usable_size; > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c > index 1369fc4..bd58da0 100644 > --- a/drivers/gpu/drm/i915/intel_i2c.c > +++ b/drivers/gpu/drm/i915/intel_i2c.c > @@ -74,7 +74,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, > { > if (IS_BROXTON(dev_priv)) > return &gmbus_pins_bxt[pin]; > - else if (IS_SKYLAKE(dev_priv)) > + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > return &gmbus_pins_skl[pin]; > else if (IS_BROADWELL(dev_priv)) > return &gmbus_pins_bdw[pin]; > @@ -89,7 +89,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, > > if (IS_BROXTON(dev_priv)) > size = ARRAY_SIZE(gmbus_pins_bxt); > - else if (IS_SKYLAKE(dev_priv)) > + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > size = ARRAY_SIZE(gmbus_pins_skl); > else if (IS_BROADWELL(dev_priv)) > size = ARRAY_SIZE(gmbus_pins_bdw); > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c > index 6d3c6c0..b258a2a 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -143,7 +143,7 @@ static bool get_mocs_settings(struct drm_device *dev, > { > bool result = false; > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > table->size = ARRAY_SIZE(skylake_mocs_table); > table->table = skylake_mocs_table; > result = true; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 7b110cd..dd63bba 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4567,7 +4567,8 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) > dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; > > dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; > - if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { > + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || > + IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > ret = sandybridge_pcode_read(dev_priv, > HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, > &ddcc_status); > @@ -4579,7 +4580,7 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) > dev_priv->rps.max_freq); > } > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > /* Store the frequency values in 16.66 MHZ units, which is > the natural hardware unit for SKL */ > dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; > @@ -4935,7 +4936,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) > /* convert DDR frequency from units of 266.6MHz to bandwidth */ > min_ring_freq = mult_frac(min_ring_freq, 8, 3); > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > /* Convert GT frequency to 50 HZ units */ > min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; > max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; > @@ -4953,7 +4954,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) > int diff = max_gpu_freq - gpu_freq; > unsigned int ia_freq = 0, ring_freq = 0; > > - if (IS_SKYLAKE(dev)) { > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > /* > * ring_freq = 2 * GT. ring_freq is in 100MHz units > * No floor required for ring frequency on SKL. > @@ -6081,7 +6082,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) > } else if (INTEL_INFO(dev)->gen >= 9) { > gen9_enable_rc6(dev); > gen9_enable_rps(dev); > - if (IS_SKYLAKE(dev)) > + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > __gen6_update_ring_freq(dev); > } else if (IS_BROADWELL(dev)) { > gen8_enable_rps(dev); > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index e50cc88..1017555 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -1832,7 +1832,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) > set_power_wells(power_domains, hsw_power_wells); > } else if (IS_BROADWELL(dev_priv->dev)) { > set_power_wells(power_domains, bdw_power_wells); > - } else if (IS_SKYLAKE(dev_priv->dev)) { > + } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) { > set_power_wells(power_domains, skl_power_wells); > } else if (IS_BROXTON(dev_priv->dev)) { > set_power_wells(power_domains, bxt_power_wells); > -- > 2.4.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH] drm/i915/kbl: Introduce Kabylake platform defition. 2015-10-28 11:16 ` [PATCH] " Rodrigo Vivi 2015-10-28 19:18 ` Jani Nikula @ 2015-10-28 19:31 ` Chris Wilson 2015-10-28 19:44 ` Rodrigo Vivi 1 sibling, 1 reply; 28+ messages in thread From: Chris Wilson @ 2015-10-28 19:31 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Jani Nikula, intel-gfx On Wed, Oct 28, 2015 at 04:16:45AM -0700, Rodrigo Vivi wrote: > +static const struct intel_device_info intel_kabylake_info = { > + .is_preliminary = 1, > + .is_kabylake = 1, > + .gen = 9, > + .num_pipes = 3, > + .need_gfx_hws = 1, .has_hotplug = 1, > + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > + .has_llc = 1, > + .has_ddi = 1, > + .has_fpga_dbg = 1, > + .has_fbc = 1, > + GEN_DEFAULT_PIPEOFFSETS, > + IVB_CURSOR_OFFSETS, > +}; > + > +static const struct intel_device_info intel_kabylake_gt3_info = { > + .is_preliminary = 1, > + .is_kabylake = 1, > + .gen = 9, > + .num_pipes = 3, > + .need_gfx_hws = 1, .has_hotplug = 1, > + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, > + .has_llc = 1, > + .has_ddi = 1, > + .has_fpga_dbg = 1, > + .has_fbc = 1, > + GEN_DEFAULT_PIPEOFFSETS, > + IVB_CURSOR_OFFSETS, > +}; Let's play spot the difference. Or you could share the base kabylake definitions as a macro and override the different fields. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH] drm/i915/kbl: Introduce Kabylake platform defition. 2015-10-28 19:31 ` Chris Wilson @ 2015-10-28 19:44 ` Rodrigo Vivi 2015-10-28 20:01 ` Chris Wilson 0 siblings, 1 reply; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-28 19:44 UTC (permalink / raw) To: Chris Wilson, Rodrigo Vivi, intel-gfx, Jani Nikula On Wed, Oct 28, 2015 at 12:31 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote: > On Wed, Oct 28, 2015 at 04:16:45AM -0700, Rodrigo Vivi wrote: > >> +static const struct intel_device_info intel_kabylake_info = { >> + .is_preliminary = 1, >> + .is_kabylake = 1, >> + .gen = 9, >> + .num_pipes = 3, >> + .need_gfx_hws = 1, .has_hotplug = 1, >> + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, >> + .has_llc = 1, >> + .has_ddi = 1, >> + .has_fpga_dbg = 1, >> + .has_fbc = 1, >> + GEN_DEFAULT_PIPEOFFSETS, >> + IVB_CURSOR_OFFSETS, >> +}; >> + >> +static const struct intel_device_info intel_kabylake_gt3_info = { >> + .is_preliminary = 1, >> + .is_kabylake = 1, >> + .gen = 9, >> + .num_pipes = 3, >> + .need_gfx_hws = 1, .has_hotplug = 1, >> + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, >> + .has_llc = 1, >> + .has_ddi = 1, >> + .has_fpga_dbg = 1, >> + .has_fbc = 1, >> + GEN_DEFAULT_PIPEOFFSETS, >> + IVB_CURSOR_OFFSETS, >> +}; > > Let's play spot the difference. Or you could share the base kabylake > definitions as a macro and override the different fields. yeap, just following the style it was already there... there are other things here that I don't like as well like has_fbc=1 here and HAS_<other_features> as defines... I believe we need a re-org on the platform definitions... to be done in a follow-up series... > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH] drm/i915/kbl: Introduce Kabylake platform defition. 2015-10-28 19:44 ` Rodrigo Vivi @ 2015-10-28 20:01 ` Chris Wilson 0 siblings, 0 replies; 28+ messages in thread From: Chris Wilson @ 2015-10-28 20:01 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Jani Nikula, intel-gfx, Rodrigo Vivi On Wed, Oct 28, 2015 at 12:44:30PM -0700, Rodrigo Vivi wrote: > On Wed, Oct 28, 2015 at 12:31 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > On Wed, Oct 28, 2015 at 04:16:45AM -0700, Rodrigo Vivi wrote: > > > >> +static const struct intel_device_info intel_kabylake_info = { > >> + .is_preliminary = 1, > >> + .is_kabylake = 1, > >> + .gen = 9, > >> + .num_pipes = 3, > >> + .need_gfx_hws = 1, .has_hotplug = 1, > >> + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > >> + .has_llc = 1, > >> + .has_ddi = 1, > >> + .has_fpga_dbg = 1, > >> + .has_fbc = 1, > >> + GEN_DEFAULT_PIPEOFFSETS, > >> + IVB_CURSOR_OFFSETS, > >> +}; > >> + > >> +static const struct intel_device_info intel_kabylake_gt3_info = { > >> + .is_preliminary = 1, > >> + .is_kabylake = 1, > >> + .gen = 9, > >> + .num_pipes = 3, > >> + .need_gfx_hws = 1, .has_hotplug = 1, > >> + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, > >> + .has_llc = 1, > >> + .has_ddi = 1, > >> + .has_fpga_dbg = 1, > >> + .has_fbc = 1, > >> + GEN_DEFAULT_PIPEOFFSETS, > >> + IVB_CURSOR_OFFSETS, > >> +}; > > > > Let's play spot the difference. Or you could share the base kabylake > > definitions as a macro and override the different fields. > > yeap, just following the style it was already there... Bah, blame broadwell for not following the trend we established in gen7 to reduce the duplication. > there are other things here that I don't like as well like has_fbc=1 here and > HAS_<other_features> as defines... > I believe we need a re-org on the platform definitions... Always. We always need to find new ways to consolidate the feature tests for code paths, just hw never follows a logical trend. The one major advantage we have for using device_info is that we can and do dump the capabilities/features. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 3/6] drm/i915/kbl: Add Kabylake PCI ID 2015-10-27 17:14 [PATCH 0/6] Kabylake patches V2 Rodrigo Vivi 2015-10-27 17:14 ` [PATCH 1/6] drm/i915: Define IS_BROXTON properly Rodrigo Vivi 2015-10-27 17:14 ` [PATCH 2/6] drm/i915/kbl: Introduce Kabylake platform defition Rodrigo Vivi @ 2015-10-27 17:14 ` Rodrigo Vivi 2015-10-28 19:19 ` [PATCH] " Rodrigo Vivi 2015-10-27 17:14 ` [PATCH 4/6] drm/i915/kbl: Add Kabylake GT4 " Rodrigo Vivi ` (3 subsequent siblings) 6 siblings, 1 reply; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-27 17:14 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Deepak S, Rodrigo Vivi From: Deepak S <deepak.s@intel.com> v2: separate out device info into different GT (Damien) v3: Add is_kabylake to the KBL gt3 structuer (Damien) Sort the platforms in older -> newer order (Damien) v4: Split platform definition since is_skylake=1 on kabylake structure was Nacked. (Rodrigo) Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Deepak S <deepak.s@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 5 ++++- include/drm/i915_pciids.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index c9e80fb..a3247e6 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -465,7 +465,10 @@ static const struct intel_device_info intel_kabylake_gt3_info = { INTEL_SKL_GT1_IDS(&intel_skylake_info), \ INTEL_SKL_GT2_IDS(&intel_skylake_info), \ INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \ - INTEL_BXT_IDS(&intel_broxton_info) + INTEL_BXT_IDS(&intel_broxton_info), \ + INTEL_KBL_GT1_IDS(&intel_kabylake_info), \ + INTEL_KBL_GT2_IDS(&intel_kabylake_info), \ + INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info) static const struct pci_device_id pciidlist[] = { /* aka */ INTEL_PCI_IDS, diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 17c4456..2e7a159 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -291,4 +291,33 @@ INTEL_VGA_DEVICE(0x1A84, info), \ INTEL_VGA_DEVICE(0x5A84, info) +#define INTEL_KBL_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ + INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ + INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \ + INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ + INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ + +#define INTEL_KBL_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ + INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ + INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ + INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ + +#define INTEL_KBL_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ + INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ + +#define INTEL_KBL_IDS(info) \ + INTEL_KBL_GT1_IDS(info), \ + INTEL_KBL_GT2_IDS(info), \ + INTEL_KBL_GT3_IDS(info) + #endif /* _I915_PCIIDS_H */ -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH] drm/i915/kbl: Add Kabylake PCI ID 2015-10-27 17:14 ` [PATCH 3/6] drm/i915/kbl: Add Kabylake PCI ID Rodrigo Vivi @ 2015-10-28 19:19 ` Rodrigo Vivi 0 siblings, 0 replies; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-28 19:19 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak S, Jani Nikula, Rodrigo Vivi From: Deepak S <deepak.s@intel.com> v2: separate out device info into different GT (Damien) v3: Add is_kabylake to the KBL gt3 structuer (Damien) Sort the platforms in older -> newer order (Damien) v4: Split platform definition since is_skylake=1 on kabylake structure was Nacked. (Rodrigo) v5: (Rodrigo) Rebase after commit 3cb27f38f ("drm/i915: remove an extra level of indirection in PCI ID list") Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Deepak S <deepak.s@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 3 +++ include/drm/i915_pciids.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 7b29aee..f020daa 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -466,6 +466,9 @@ static const struct pci_device_id pciidlist[] = { INTEL_SKL_GT2_IDS(&intel_skylake_info), INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), INTEL_BXT_IDS(&intel_broxton_info), + INTEL_KBL_GT1_IDS(&intel_kabylake_info), + INTEL_KBL_GT2_IDS(&intel_kabylake_info), + INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), {0, 0, 0} }; diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 17c4456..2e7a159 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -291,4 +291,33 @@ INTEL_VGA_DEVICE(0x1A84, info), \ INTEL_VGA_DEVICE(0x5A84, info) +#define INTEL_KBL_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ + INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ + INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \ + INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ + INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ + +#define INTEL_KBL_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ + INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ + INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ + INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ + +#define INTEL_KBL_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ + INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ + +#define INTEL_KBL_IDS(info) \ + INTEL_KBL_GT1_IDS(info), \ + INTEL_KBL_GT2_IDS(info), \ + INTEL_KBL_GT3_IDS(info) + #endif /* _I915_PCIIDS_H */ -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 4/6] drm/i915/kbl: Add Kabylake GT4 PCI ID 2015-10-27 17:14 [PATCH 0/6] Kabylake patches V2 Rodrigo Vivi ` (2 preceding siblings ...) 2015-10-27 17:14 ` [PATCH 3/6] drm/i915/kbl: Add Kabylake PCI ID Rodrigo Vivi @ 2015-10-27 17:14 ` Rodrigo Vivi 2015-10-28 19:21 ` [PATCH] " Rodrigo Vivi 2015-10-27 17:14 ` [PATCH 5/6] drm/i915/kbl: Use propper ddi buffer translation table for Kabylake ULT and ULX Rodrigo Vivi ` (2 subsequent siblings) 6 siblings, 1 reply; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-27 17:14 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Deepak S, Rodrigo Vivi From: Deepak S <deepak.s@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Deepak S <deepak.s@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 3 ++- include/drm/i915_pciids.h | 9 ++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index a3247e6..fd2f9a2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -468,7 +468,8 @@ static const struct intel_device_info intel_kabylake_gt3_info = { INTEL_BXT_IDS(&intel_broxton_info), \ INTEL_KBL_GT1_IDS(&intel_kabylake_info), \ INTEL_KBL_GT2_IDS(&intel_kabylake_info), \ - INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info) + INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), \ + INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info) static const struct pci_device_id pciidlist[] = { /* aka */ INTEL_PCI_IDS, diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 2e7a159..f1a113e 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -315,9 +315,16 @@ INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ +#define INTEL_KBL_GT4_IDS(info) \ + INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \ + INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \ + INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \ + INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */ + #define INTEL_KBL_IDS(info) \ INTEL_KBL_GT1_IDS(info), \ INTEL_KBL_GT2_IDS(info), \ - INTEL_KBL_GT3_IDS(info) + INTEL_KBL_GT3_IDS(info), \ + INTEL_KBL_GT4_IDS(info) #endif /* _I915_PCIIDS_H */ -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH] drm/i915/kbl: Add Kabylake GT4 PCI ID 2015-10-27 17:14 ` [PATCH 4/6] drm/i915/kbl: Add Kabylake GT4 " Rodrigo Vivi @ 2015-10-28 19:21 ` Rodrigo Vivi 2015-10-28 19:49 ` Jani Nikula 0 siblings, 1 reply; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-28 19:21 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak S, Jani Nikula, Rodrigo Vivi From: Deepak S <deepak.s@intel.com> v2: (Rodrigo) Rebase after commit 3cb27f38f ("drm/i915: remove an extra level of indirection in PCI ID list") Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Deepak S <deepak.s@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 1 + include/drm/i915_pciids.h | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index f020daa..9f55209 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -469,6 +469,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_KBL_GT1_IDS(&intel_kabylake_info), INTEL_KBL_GT2_IDS(&intel_kabylake_info), INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), + INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), {0, 0, 0} }; diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 2e7a159..f1a113e 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -315,9 +315,16 @@ INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ +#define INTEL_KBL_GT4_IDS(info) \ + INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \ + INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \ + INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \ + INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */ + #define INTEL_KBL_IDS(info) \ INTEL_KBL_GT1_IDS(info), \ INTEL_KBL_GT2_IDS(info), \ - INTEL_KBL_GT3_IDS(info) + INTEL_KBL_GT3_IDS(info), \ + INTEL_KBL_GT4_IDS(info) #endif /* _I915_PCIIDS_H */ -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH] drm/i915/kbl: Add Kabylake GT4 PCI ID 2015-10-28 19:21 ` [PATCH] " Rodrigo Vivi @ 2015-10-28 19:49 ` Jani Nikula 0 siblings, 0 replies; 28+ messages in thread From: Jani Nikula @ 2015-10-28 19:49 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak S, Rodrigo Vivi On Wed, 28 Oct 2015, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > From: Deepak S <deepak.s@intel.com> > > v2: (Rodrigo) Rebase after commit 3cb27f38f > ("drm/i915: remove an extra level of indirection in PCI ID list") > > Cc: Jani Nikula <jani.nikula@intel.com> > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> > Signed-off-by: Deepak S <deepak.s@intel.com> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Pushed patches 1-4, thanks. BR, Jani. > --- > drivers/gpu/drm/i915/i915_drv.c | 1 + > include/drm/i915_pciids.h | 9 ++++++++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index f020daa..9f55209 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -469,6 +469,7 @@ static const struct pci_device_id pciidlist[] = { > INTEL_KBL_GT1_IDS(&intel_kabylake_info), > INTEL_KBL_GT2_IDS(&intel_kabylake_info), > INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), > + INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), > {0, 0, 0} > }; > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index 2e7a159..f1a113e 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -315,9 +315,16 @@ > INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ > INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ > > +#define INTEL_KBL_GT4_IDS(info) \ > + INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \ > + INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \ > + INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \ > + INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */ > + > #define INTEL_KBL_IDS(info) \ > INTEL_KBL_GT1_IDS(info), \ > INTEL_KBL_GT2_IDS(info), \ > - INTEL_KBL_GT3_IDS(info) > + INTEL_KBL_GT3_IDS(info), \ > + INTEL_KBL_GT4_IDS(info) > > #endif /* _I915_PCIIDS_H */ > -- > 2.4.3 > -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 5/6] drm/i915/kbl: Use propper ddi buffer translation table for Kabylake ULT and ULX. 2015-10-27 17:14 [PATCH 0/6] Kabylake patches V2 Rodrigo Vivi ` (3 preceding siblings ...) 2015-10-27 17:14 ` [PATCH 4/6] drm/i915/kbl: Add Kabylake GT4 " Rodrigo Vivi @ 2015-10-27 17:14 ` Rodrigo Vivi 2015-11-06 20:26 ` Paulo Zanoni 2015-10-27 17:14 ` [PATCH 6/6] drm/i915/kbl: Fix DMC load on Kabylake Rodrigo Vivi 2015-10-29 17:22 ` [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now " Rodrigo Vivi 6 siblings, 1 reply; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-27 17:14 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Rodrigo Vivi Let's introduce ULT and ULX Kabylake definitions and start using it for a propper DDI buffer translation. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++ drivers/gpu/drm/i915/intel_ddi.c | 10 +++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3982d1a..e0b84c8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2506,6 +2506,14 @@ struct drm_i915_cmd_table { #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ INTEL_DEVID(dev) == 0x1915 || \ INTEL_DEVID(dev) == 0x191E) +#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ + INTEL_DEVID(dev) == 0x5913 || \ + INTEL_DEVID(dev) == 0x5916 || \ + INTEL_DEVID(dev) == 0x5921 || \ + INTEL_DEVID(dev) == 0x5926) +#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ + INTEL_DEVID(dev) == 0x5915 || \ + INTEL_DEVID(dev) == 0x591E) #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ (INTEL_DEVID(dev) & 0x00F0) == 0x0020) #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 8dd9fae..424bccc 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -353,10 +353,10 @@ static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev, { const struct ddi_buf_trans *ddi_translations; - if (IS_SKL_ULX(dev)) { + if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { ddi_translations = skl_y_ddi_translations_dp; *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); - } else if (IS_SKL_ULT(dev)) { + } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { ddi_translations = skl_u_ddi_translations_dp; *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); } else { @@ -373,7 +373,7 @@ static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, struct drm_i915_private *dev_priv = dev->dev_private; const struct ddi_buf_trans *ddi_translations; - if (IS_SKL_ULX(dev)) { + if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { if (dev_priv->edp_low_vswing) { ddi_translations = skl_y_ddi_translations_edp; *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); @@ -381,7 +381,7 @@ static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, ddi_translations = skl_y_ddi_translations_dp; *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); } - } else if (IS_SKL_ULT(dev)) { + } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { if (dev_priv->edp_low_vswing) { ddi_translations = skl_u_ddi_translations_edp; *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); @@ -408,7 +408,7 @@ skl_get_buf_trans_hdmi(struct drm_device *dev, { const struct ddi_buf_trans *ddi_translations; - if (IS_SKL_ULX(dev)) { + if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { ddi_translations = skl_y_ddi_translations_hdmi; *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); } else { -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 5/6] drm/i915/kbl: Use propper ddi buffer translation table for Kabylake ULT and ULX. 2015-10-27 17:14 ` [PATCH 5/6] drm/i915/kbl: Use propper ddi buffer translation table for Kabylake ULT and ULX Rodrigo Vivi @ 2015-11-06 20:26 ` Paulo Zanoni 0 siblings, 0 replies; 28+ messages in thread From: Paulo Zanoni @ 2015-11-06 20:26 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Jani Nikula, Intel Graphics Development 2015-10-27 15:14 GMT-02:00 Rodrigo Vivi <rodrigo.vivi@intel.com>: > Let's introduce ULT and ULX Kabylake definitions and start > using it for a propper DDI buffer translation. > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++ > drivers/gpu/drm/i915/intel_ddi.c | 10 +++++----- > 2 files changed, 13 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 3982d1a..e0b84c8 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2506,6 +2506,14 @@ struct drm_i915_cmd_table { > #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ > INTEL_DEVID(dev) == 0x1915 || \ > INTEL_DEVID(dev) == 0x191E) > +#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ > + INTEL_DEVID(dev) == 0x5913 || \ > + INTEL_DEVID(dev) == 0x5916 || \ > + INTEL_DEVID(dev) == 0x5921 || \ > + INTEL_DEVID(dev) == 0x5926) > +#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ > + INTEL_DEVID(dev) == 0x5915 || \ > + INTEL_DEVID(dev) == 0x591E) (insert bikeshed about checking just the last 4 bits, like we do for IS_BDW_ULT()) > #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ > (INTEL_DEVID(dev) & 0x00F0) == 0x0020) > #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 8dd9fae..424bccc 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -353,10 +353,10 @@ static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev, > { > const struct ddi_buf_trans *ddi_translations; > > - if (IS_SKL_ULX(dev)) { > + if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { > ddi_translations = skl_y_ddi_translations_dp; > *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); > - } else if (IS_SKL_ULT(dev)) { > + } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { > ddi_translations = skl_u_ddi_translations_dp; > *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); > } else { > @@ -373,7 +373,7 @@ static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, > struct drm_i915_private *dev_priv = dev->dev_private; > const struct ddi_buf_trans *ddi_translations; > > - if (IS_SKL_ULX(dev)) { > + if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { There is an extra white space before the "||" chars :) Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > if (dev_priv->edp_low_vswing) { > ddi_translations = skl_y_ddi_translations_edp; > *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); > @@ -381,7 +381,7 @@ static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, > ddi_translations = skl_y_ddi_translations_dp; > *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); > } > - } else if (IS_SKL_ULT(dev)) { > + } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { > if (dev_priv->edp_low_vswing) { > ddi_translations = skl_u_ddi_translations_edp; > *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); > @@ -408,7 +408,7 @@ skl_get_buf_trans_hdmi(struct drm_device *dev, > { > const struct ddi_buf_trans *ddi_translations; > > - if (IS_SKL_ULX(dev)) { > + if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { > ddi_translations = skl_y_ddi_translations_hdmi; > *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); > } else { > -- > 2.4.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 6/6] drm/i915/kbl: Fix DMC load on Kabylake. 2015-10-27 17:14 [PATCH 0/6] Kabylake patches V2 Rodrigo Vivi ` (4 preceding siblings ...) 2015-10-27 17:14 ` [PATCH 5/6] drm/i915/kbl: Use propper ddi buffer translation table for Kabylake ULT and ULX Rodrigo Vivi @ 2015-10-27 17:14 ` Rodrigo Vivi 2015-10-29 17:20 ` [PATCH] " Rodrigo Vivi 2015-10-29 17:22 ` [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now " Rodrigo Vivi 6 siblings, 1 reply; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-27 17:14 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Rodrigo Vivi Kabylake A0 is based on Skylake H0. v2: Don't assume revid+7 and only load the one we are sure about. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 36 ++++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 9e530a7..e4020ae 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -190,9 +190,21 @@ static struct stepping_info bxt_stepping_info[] = { static char intel_get_stepping(struct drm_device *dev) { - if (IS_SKYLAKE(dev) && (dev->pdev->revision < - ARRAY_SIZE(skl_stepping_info))) - return skl_stepping_info[dev->pdev->revision].stepping; + int revid = INTEL_REVID(dev); + + /* + * FIXME: Kabylake derivated from Skylake H0, so SKL H0 + * is the right firmware for KBL A0 (revid 0). + * We have no visibility yet how next KBL steppings will + * be handled by firmware, so let's just add support for + * the only current available KBL. + */ + if (IS_KABYLAKE(dev) && revid == 0) + return skl_stepping_info[7].stepping; + + if (IS_SKYLAKE(dev) && + revid < ARRAY_SIZE(skl_stepping_info)) + return skl_stepping_info[revid].stepping; else if (IS_BROXTON(dev) && (dev->pdev->revision < ARRAY_SIZE(bxt_stepping_info))) return bxt_stepping_info[dev->pdev->revision].stepping; @@ -202,9 +214,21 @@ static char intel_get_stepping(struct drm_device *dev) static char intel_get_substepping(struct drm_device *dev) { - if (IS_SKYLAKE(dev) && (dev->pdev->revision < - ARRAY_SIZE(skl_stepping_info))) - return skl_stepping_info[dev->pdev->revision].substepping; + int revid = INTEL_REVID(dev); + + /* + * FIXME: Kabylake derivated from Skylake H0, so SKL H0 + * is the right firmware for KBL A0 (revid 0). + * We have no visibility yet how next KBL steppings will + * be handled by firmware, so let's just add support for + * the only current available KBL. + */ + if (IS_KABYLAKE(dev) && revid == 0) + return skl_stepping_info[7].substepping; + + if (IS_SKYLAKE(dev) && + revid < ARRAY_SIZE(skl_stepping_info)) + return skl_stepping_info[revid].substepping; else if (IS_BROXTON(dev) && (dev->pdev->revision < ARRAY_SIZE(bxt_stepping_info))) return bxt_stepping_info[dev->pdev->revision].substepping; -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH] drm/i915/kbl: Fix DMC load on Kabylake. 2015-10-27 17:14 ` [PATCH 6/6] drm/i915/kbl: Fix DMC load on Kabylake Rodrigo Vivi @ 2015-10-29 17:20 ` Rodrigo Vivi 2015-10-29 17:58 ` kbuild test robot 2015-10-29 18:05 ` kbuild test robot 0 siblings, 2 replies; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-29 17:20 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Kabylake A0 is based on Skylake H0. v2: Don't assume revid+7 and only load the one we are sure about. v3: Add missing IS_KABYLAKE. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 9e530a7..d4bb90a 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -190,9 +190,21 @@ static struct stepping_info bxt_stepping_info[] = { static char intel_get_stepping(struct drm_device *dev) { - if (IS_SKYLAKE(dev) && (dev->pdev->revision < - ARRAY_SIZE(skl_stepping_info))) - return skl_stepping_info[dev->pdev->revision].stepping; + int revid = INTEL_REVID(dev); + + /* + * FIXME: Kabylake derivated from Skylake H0, so SKL H0 + * is the right firmware for KBL A0 (revid 0). + * We have no visibility yet how next KBL steppings will + * be handled by firmware, so let's just add support for + * the only current available KBL. + */ + if (IS_KABYLAKE(dev) && revid == 0) + return skl_stepping_info[7].stepping; + + if (IS_SKYLAKE(dev) && + revid < ARRAY_SIZE(skl_stepping_info)) + return skl_stepping_info[revid].stepping; else if (IS_BROXTON(dev) && (dev->pdev->revision < ARRAY_SIZE(bxt_stepping_info))) return bxt_stepping_info[dev->pdev->revision].stepping; @@ -202,9 +214,21 @@ static char intel_get_stepping(struct drm_device *dev) static char intel_get_substepping(struct drm_device *dev) { - if (IS_SKYLAKE(dev) && (dev->pdev->revision < - ARRAY_SIZE(skl_stepping_info))) - return skl_stepping_info[dev->pdev->revision].substepping; + int revid = INTEL_REVID(dev); + + /* + * FIXME: Kabylake derivated from Skylake H0, so SKL H0 + * is the right firmware for KBL A0 (revid 0). + * We have no visibility yet how next KBL steppings will + * be handled by firmware, so let's just add support for + * the only current available KBL. + */ + if (IS_KABYLAKE(dev) && revid == 0) + return skl_stepping_info[7].substepping; + + if (IS_SKYLAKE(dev) && + revid < ARRAY_SIZE(skl_stepping_info)) + return skl_stepping_info[revid].substepping; else if (IS_BROXTON(dev) && (dev->pdev->revision < ARRAY_SIZE(bxt_stepping_info))) return bxt_stepping_info[dev->pdev->revision].substepping; @@ -428,7 +452,7 @@ void intel_csr_ucode_init(struct drm_device *dev) if (!HAS_CSR(dev)) return; - if (IS_SKYLAKE(dev)) + if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) csr->fw_path = I915_CSR_SKL; else if (IS_BROXTON(dev_priv)) csr->fw_path = I915_CSR_BXT; -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH] drm/i915/kbl: Fix DMC load on Kabylake. 2015-10-29 17:20 ` [PATCH] " Rodrigo Vivi @ 2015-10-29 17:58 ` kbuild test robot 2015-10-29 18:05 ` kbuild test robot 1 sibling, 0 replies; 28+ messages in thread From: kbuild test robot @ 2015-10-29 17:58 UTC (permalink / raw) Cc: intel-gfx, kbuild-all, Rodrigo Vivi [-- Attachment #1: Type: text/plain, Size: 7310 bytes --] Hi Rodrigo, [auto build test WARNING on drm-intel/for-linux-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-kbl-Fix-DMC-load-on-Kabylake/20151030-012303 config: x86_64-randconfig-x001-10252017 (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All warnings (new ones prefixed by >>): In file included from include/uapi/linux/stddef.h:1:0, from include/linux/stddef.h:4, from include/uapi/linux/posix_types.h:4, from include/uapi/linux/types.h:13, from include/linux/types.h:5, from include/linux/firmware.h:4, from drivers/gpu/drm/i915/intel_csr.c:24: drivers/gpu/drm/i915/intel_csr.c: In function 'intel_get_stepping': drivers/gpu/drm/i915/intel_csr.c:202:6: error: implicit declaration of function 'IS_KABYLAKE' [-Werror=implicit-function-declaration] if (IS_KABYLAKE(dev) && revid == 0) ^ include/linux/compiler.h:147:28: note: in definition of macro '__trace_if' if (__builtin_constant_p((cond)) ? !!(cond) : \ ^ >> drivers/gpu/drm/i915/intel_csr.c:202:2: note: in expansion of macro 'if' if (IS_KABYLAKE(dev) && revid == 0) ^ cc1: some warnings being treated as errors vim +/if +202 drivers/gpu/drm/i915/intel_csr.c 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ > 24 #include <linux/firmware.h> 25 #include "i915_drv.h" 26 #include "i915_reg.h" 27 28 /** 29 * DOC: csr support for dmc 30 * 31 * Display Context Save and Restore (CSR) firmware support added from gen9 32 * onwards to drive newly added DMC (Display microcontroller) in display 33 * engine to save and restore the state of display engine when it enter into 34 * low-power state and comes back to normal. 35 * 36 * Firmware loading status will be one of the below states: FW_UNINITIALIZED, 37 * FW_LOADED, FW_FAILED. 38 * 39 * Once the firmware is written into the registers status will be moved from 40 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will 41 * be moved to FW_FAILED. 42 */ 43 44 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin" 45 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin" 46 47 MODULE_FIRMWARE(I915_CSR_SKL); 48 MODULE_FIRMWARE(I915_CSR_BXT); 49 50 /* 51 * SKL CSR registers for DC5 and DC6 52 */ 53 #define CSR_PROGRAM(i) (0x80000 + (i) * 4) 54 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 55 #define CSR_HTP_ADDR_SKL 0x00500034 56 #define CSR_SSP_BASE 0x8F074 57 #define CSR_HTP_SKL 0x8F004 58 #define CSR_LAST_WRITE 0x8F034 59 #define CSR_LAST_WRITE_VALUE 0xc003b400 60 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 61 #define CSR_MAX_FW_SIZE 0x2FFF 62 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF 63 #define CSR_MMIO_START_RANGE 0x80000 64 #define CSR_MMIO_END_RANGE 0x8FFFF 65 66 struct intel_css_header { 67 /* 0x09 for DMC */ 68 uint32_t module_type; 69 70 /* Includes the DMC specific header in dwords */ 71 uint32_t header_len; 72 73 /* always value would be 0x10000 */ 74 uint32_t header_ver; 75 76 /* Not used */ 77 uint32_t module_id; 78 79 /* Not used */ 80 uint32_t module_vendor; 81 82 /* in YYYYMMDD format */ 83 uint32_t date; 84 85 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 86 uint32_t size; 87 88 /* Not used */ 89 uint32_t key_size; 90 91 /* Not used */ 92 uint32_t modulus_size; 93 94 /* Not used */ 95 uint32_t exponent_size; 96 97 /* Not used */ 98 uint32_t reserved1[12]; 99 100 /* Major Minor */ 101 uint32_t version; 102 103 /* Not used */ 104 uint32_t reserved2[8]; 105 106 /* Not used */ 107 uint32_t kernel_header_info; 108 } __packed; 109 110 struct intel_fw_info { 111 uint16_t reserved1; 112 113 /* Stepping (A, B, C, ..., *). * is a wildcard */ 114 char stepping; 115 116 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 117 char substepping; 118 119 uint32_t offset; 120 uint32_t reserved2; 121 } __packed; 122 123 struct intel_package_header { 124 /* DMC container header length in dwords */ 125 unsigned char header_len; 126 127 /* always value would be 0x01 */ 128 unsigned char header_ver; 129 130 unsigned char reserved[10]; 131 132 /* Number of valid entries in the FWInfo array below */ 133 uint32_t num_entries; 134 135 struct intel_fw_info fw_info[20]; 136 } __packed; 137 138 struct intel_dmc_header { 139 /* always value would be 0x40403E3E */ 140 uint32_t signature; 141 142 /* DMC binary header length */ 143 unsigned char header_len; 144 145 /* 0x01 */ 146 unsigned char header_ver; 147 148 /* Reserved */ 149 uint16_t dmcc_ver; 150 151 /* Major, Minor */ 152 uint32_t project; 153 154 /* Firmware program size (excluding header) in dwords */ 155 uint32_t fw_size; 156 157 /* Major Minor version */ 158 uint32_t fw_version; 159 160 /* Number of valid MMIO cycles present. */ 161 uint32_t mmio_count; 162 163 /* MMIO address */ 164 uint32_t mmioaddr[8]; 165 166 /* MMIO data */ 167 uint32_t mmiodata[8]; 168 169 /* FW filename */ 170 unsigned char dfile[32]; 171 172 uint32_t reserved1[2]; 173 } __packed; 174 175 struct stepping_info { 176 char stepping; 177 char substepping; 178 }; 179 180 static const struct stepping_info skl_stepping_info[] = { 181 {'A', '0'}, {'B', '0'}, {'C', '0'}, 182 {'D', '0'}, {'E', '0'}, {'F', '0'}, 183 {'G', '0'}, {'H', '0'}, {'I', '0'} 184 }; 185 186 static struct stepping_info bxt_stepping_info[] = { 187 {'A', '0'}, {'A', '1'}, {'A', '2'}, 188 {'B', '0'}, {'B', '1'}, {'B', '2'} 189 }; 190 191 static char intel_get_stepping(struct drm_device *dev) 192 { 193 int revid = INTEL_REVID(dev); 194 195 /* 196 * FIXME: Kabylake derivated from Skylake H0, so SKL H0 197 * is the right firmware for KBL A0 (revid 0). 198 * We have no visibility yet how next KBL steppings will 199 * be handled by firmware, so let's just add support for 200 * the only current available KBL. 201 */ > 202 if (IS_KABYLAKE(dev) && revid == 0) 203 return skl_stepping_info[7].stepping; 204 205 if (IS_SKYLAKE(dev) && --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/octet-stream, Size: 27180 bytes --] [-- Attachment #3: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH] drm/i915/kbl: Fix DMC load on Kabylake. 2015-10-29 17:20 ` [PATCH] " Rodrigo Vivi 2015-10-29 17:58 ` kbuild test robot @ 2015-10-29 18:05 ` kbuild test robot 1 sibling, 0 replies; 28+ messages in thread From: kbuild test robot @ 2015-10-29 18:05 UTC (permalink / raw) Cc: intel-gfx, kbuild-all, Rodrigo Vivi [-- Attachment #1: Type: text/plain, Size: 1425 bytes --] Hi Rodrigo, [auto build test ERROR on drm-intel/for-linux-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-kbl-Fix-DMC-load-on-Kabylake/20151030-012303 config: x86_64-randconfig-x008-10252017 (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): drivers/gpu/drm/i915/intel_csr.c: In function 'intel_get_stepping': >> drivers/gpu/drm/i915/intel_csr.c:202:6: error: implicit declaration of function 'IS_KABYLAKE' [-Werror=implicit-function-declaration] if (IS_KABYLAKE(dev) && revid == 0) ^ cc1: some warnings being treated as errors vim +/IS_KABYLAKE +202 drivers/gpu/drm/i915/intel_csr.c 196 * FIXME: Kabylake derivated from Skylake H0, so SKL H0 197 * is the right firmware for KBL A0 (revid 0). 198 * We have no visibility yet how next KBL steppings will 199 * be handled by firmware, so let's just add support for 200 * the only current available KBL. 201 */ > 202 if (IS_KABYLAKE(dev) && revid == 0) 203 return skl_stepping_info[7].stepping; 204 205 if (IS_SKYLAKE(dev) && --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/octet-stream, Size: 32842 bytes --] [-- Attachment #3: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake. 2015-10-27 17:14 [PATCH 0/6] Kabylake patches V2 Rodrigo Vivi ` (5 preceding siblings ...) 2015-10-27 17:14 ` [PATCH 6/6] drm/i915/kbl: Fix DMC load on Kabylake Rodrigo Vivi @ 2015-10-29 17:22 ` Rodrigo Vivi 2015-10-29 17:22 ` [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake Rodrigo Vivi ` (2 more replies) 6 siblings, 3 replies; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-29 17:22 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi GuC has no version for KBL published yet and it is not recommended to load the Skylake one, so let's avoid loading this for now while we don't have the proper GuC firmware for Kabylake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a5ba485..0e971cf 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2616,8 +2616,8 @@ struct drm_i915_cmd_table { #define HAS_CSR(dev) (IS_GEN9(dev)) -#define HAS_GUC_UCODE(dev) (IS_GEN9(dev)) -#define HAS_GUC_SCHED(dev) (IS_GEN9(dev)) +#define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) +#define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ INTEL_INFO(dev)->gen >= 8) -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake 2015-10-29 17:22 ` [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now " Rodrigo Vivi @ 2015-10-29 17:22 ` Rodrigo Vivi 2015-10-29 17:53 ` kbuild test robot 2015-11-04 23:35 ` Rodrigo Vivi 2015-10-29 20:02 ` [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake kbuild test robot 2015-11-06 19:08 ` Yu Dai 2 siblings, 2 replies; 28+ messages in thread From: Rodrigo Vivi @ 2015-10-29 17:22 UTC (permalink / raw) To: intel-gfx; +Cc: Deepak S, Rodrigo Vivi From: Deepak S <deepak.s@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Deepak S <deepak.s@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- arch/x86/kernel/early-quirks.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 9f9cc68..5b85bf0 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -547,6 +547,7 @@ static const struct pci_device_id intel_stolen_ids[] __initconst = { INTEL_CHV_IDS(&chv_stolen_funcs), INTEL_SKL_IDS(&gen9_stolen_funcs), INTEL_BXT_IDS(&gen9_stolen_funcs), + INTEL_KBL_IDS(&gen9_stolen_funcs), }; static void __init intel_graphics_stolen(int num, int slot, int func) -- 2.4.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake 2015-10-29 17:22 ` [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake Rodrigo Vivi @ 2015-10-29 17:53 ` kbuild test robot 2015-11-04 23:35 ` Rodrigo Vivi 1 sibling, 0 replies; 28+ messages in thread From: kbuild test robot @ 2015-10-29 17:53 UTC (permalink / raw) Cc: Deepak S, intel-gfx, kbuild-all, Rodrigo Vivi [-- Attachment #1: Type: text/plain, Size: 3169 bytes --] Hi Deepak, [auto build test ERROR on drm-intel/for-linux-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-kbl-drm-i915-Avoid-GuC-loading-for-now-on-Kabylake/20151030-012505 config: x86_64-randconfig-x008-10252017 (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All error/warnings (new ones prefixed by >>): >> arch/x86/kernel/early-quirks.c:550:2: error: implicit declaration of function 'INTEL_KBL_IDS' [-Werror=implicit-function-declaration] INTEL_KBL_IDS(&gen9_stolen_funcs), ^ >> arch/x86/kernel/early-quirks.c:550:2: error: initializer element is not constant arch/x86/kernel/early-quirks.c:550:2: note: (near initialization for 'intel_stolen_ids[156].vendor') >> arch/x86/kernel/early-quirks.c:520:68: warning: missing braces around initializer [-Wmissing-braces] static const struct pci_device_id intel_stolen_ids[] __initconst = { ^ arch/x86/kernel/early-quirks.c:520:68: note: (near initialization for 'intel_stolen_ids') cc1: some warnings being treated as errors vim +/INTEL_KBL_IDS +550 arch/x86/kernel/early-quirks.c 514 515 static const struct intel_stolen_funcs chv_stolen_funcs __initconst = { 516 .base = intel_stolen_base, 517 .size = chv_stolen_size, 518 }; 519 > 520 static const struct pci_device_id intel_stolen_ids[] __initconst = { 521 INTEL_I830_IDS(&i830_stolen_funcs), 522 INTEL_I845G_IDS(&i845_stolen_funcs), 523 INTEL_I85X_IDS(&i85x_stolen_funcs), 524 INTEL_I865G_IDS(&i865_stolen_funcs), 525 INTEL_I915G_IDS(&gen3_stolen_funcs), 526 INTEL_I915GM_IDS(&gen3_stolen_funcs), 527 INTEL_I945G_IDS(&gen3_stolen_funcs), 528 INTEL_I945GM_IDS(&gen3_stolen_funcs), 529 INTEL_VLV_M_IDS(&gen6_stolen_funcs), 530 INTEL_VLV_D_IDS(&gen6_stolen_funcs), 531 INTEL_PINEVIEW_IDS(&gen3_stolen_funcs), 532 INTEL_I965G_IDS(&gen3_stolen_funcs), 533 INTEL_G33_IDS(&gen3_stolen_funcs), 534 INTEL_I965GM_IDS(&gen3_stolen_funcs), 535 INTEL_GM45_IDS(&gen3_stolen_funcs), 536 INTEL_G45_IDS(&gen3_stolen_funcs), 537 INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs), 538 INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs), 539 INTEL_SNB_D_IDS(&gen6_stolen_funcs), 540 INTEL_SNB_M_IDS(&gen6_stolen_funcs), 541 INTEL_IVB_M_IDS(&gen6_stolen_funcs), 542 INTEL_IVB_D_IDS(&gen6_stolen_funcs), 543 INTEL_HSW_D_IDS(&gen6_stolen_funcs), 544 INTEL_HSW_M_IDS(&gen6_stolen_funcs), 545 INTEL_BDW_M_IDS(&gen8_stolen_funcs), 546 INTEL_BDW_D_IDS(&gen8_stolen_funcs), 547 INTEL_CHV_IDS(&chv_stolen_funcs), 548 INTEL_SKL_IDS(&gen9_stolen_funcs), 549 INTEL_BXT_IDS(&gen9_stolen_funcs), > 550 INTEL_KBL_IDS(&gen9_stolen_funcs), 551 }; 552 553 static void __init intel_graphics_stolen(int num, int slot, int func) --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/octet-stream, Size: 32842 bytes --] [-- Attachment #3: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake 2015-10-29 17:22 ` [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake Rodrigo Vivi 2015-10-29 17:53 ` kbuild test robot @ 2015-11-04 23:35 ` Rodrigo Vivi 2015-11-05 13:17 ` Jani Nikula 1 sibling, 1 reply; 28+ messages in thread From: Rodrigo Vivi @ 2015-11-04 23:35 UTC (permalink / raw) To: Rodrigo Vivi, intel-gfx, Jani Nikula; +Cc: Deepak S [-- Attachment #1.1: Type: text/plain, Size: 1240 bytes --] Hi Jani, could you please consider to merge this already reviewed patch. Thanks, Rodrigo. On Thu, Oct 29, 2015 at 10:22 AM Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > From: Deepak S <deepak.s@intel.com> > > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> > Signed-off-by: Deepak S <deepak.s@intel.com> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > arch/x86/kernel/early-quirks.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/kernel/early-quirks.c > b/arch/x86/kernel/early-quirks.c > index 9f9cc68..5b85bf0 100644 > --- a/arch/x86/kernel/early-quirks.c > +++ b/arch/x86/kernel/early-quirks.c > @@ -547,6 +547,7 @@ static const struct pci_device_id intel_stolen_ids[] > __initconst = { > INTEL_CHV_IDS(&chv_stolen_funcs), > INTEL_SKL_IDS(&gen9_stolen_funcs), > INTEL_BXT_IDS(&gen9_stolen_funcs), > + INTEL_KBL_IDS(&gen9_stolen_funcs), > }; > > static void __init intel_graphics_stolen(int num, int slot, int func) > -- > 2.4.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > [-- Attachment #1.2: Type: text/html, Size: 2165 bytes --] [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake 2015-11-04 23:35 ` Rodrigo Vivi @ 2015-11-05 13:17 ` Jani Nikula 0 siblings, 0 replies; 28+ messages in thread From: Jani Nikula @ 2015-11-05 13:17 UTC (permalink / raw) To: Rodrigo Vivi, Rodrigo Vivi, intel-gfx; +Cc: Deepak S On Thu, 05 Nov 2015, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote: > Hi Jani, > > could you please consider to merge this already reviewed patch. Pushed to drm-intel-next-queued, thanks for the patch and review. BR, Jani. > > Thanks, > Rodrigo. > > On Thu, Oct 29, 2015 at 10:22 AM Rodrigo Vivi <rodrigo.vivi@intel.com> > wrote: > >> From: Deepak S <deepak.s@intel.com> >> >> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> >> Signed-off-by: Deepak S <deepak.s@intel.com> >> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> >> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> >> --- >> arch/x86/kernel/early-quirks.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/x86/kernel/early-quirks.c >> b/arch/x86/kernel/early-quirks.c >> index 9f9cc68..5b85bf0 100644 >> --- a/arch/x86/kernel/early-quirks.c >> +++ b/arch/x86/kernel/early-quirks.c >> @@ -547,6 +547,7 @@ static const struct pci_device_id intel_stolen_ids[] >> __initconst = { >> INTEL_CHV_IDS(&chv_stolen_funcs), >> INTEL_SKL_IDS(&gen9_stolen_funcs), >> INTEL_BXT_IDS(&gen9_stolen_funcs), >> + INTEL_KBL_IDS(&gen9_stolen_funcs), >> }; >> >> static void __init intel_graphics_stolen(int num, int slot, int func) >> -- >> 2.4.3 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx >> -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake. 2015-10-29 17:22 ` [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now " Rodrigo Vivi 2015-10-29 17:22 ` [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake Rodrigo Vivi @ 2015-10-29 20:02 ` kbuild test robot 2015-11-06 19:08 ` Yu Dai 2 siblings, 0 replies; 28+ messages in thread From: kbuild test robot @ 2015-10-29 20:02 UTC (permalink / raw) Cc: intel-gfx, kbuild-all, Rodrigo Vivi [-- Attachment #1: Type: text/plain, Size: 3506 bytes --] Hi Rodrigo, [auto build test ERROR on drm-intel/for-linux-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-kbl-drm-i915-Avoid-GuC-loading-for-now-on-Kabylake/20151030-012505 config: i386-defconfig (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=i386 All error/warnings (new ones prefixed by >>): In file included from drivers/gpu/drm/i915/intel_pm.c:29:0: drivers/gpu/drm/i915/intel_pm.c: In function 'gen9_enable_rc6': >> drivers/gpu/drm/i915/i915_drv.h:2587:46: error: implicit declaration of function 'IS_KABYLAKE' [-Werror=implicit-function-declaration] #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) ^ >> drivers/gpu/drm/i915/intel_pm.c:4790:6: note: in expansion of macro 'HAS_GUC_UCODE' if (HAS_GUC_UCODE(dev)) ^ cc1: some warnings being treated as errors -- In file included from drivers/gpu/drm/i915/intel_drv.h:32:0, from drivers/gpu/drm/i915/i915_debugfs.c:38: drivers/gpu/drm/i915/i915_debugfs.c: In function 'i915_guc_load_status_info': >> drivers/gpu/drm/i915/i915_drv.h:2587:46: error: implicit declaration of function 'IS_KABYLAKE' [-Werror=implicit-function-declaration] #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) ^ >> drivers/gpu/drm/i915/i915_debugfs.c:2392:7: note: in expansion of macro 'HAS_GUC_UCODE' if (!HAS_GUC_UCODE(dev_priv->dev)) ^ cc1: some warnings being treated as errors -- In file included from drivers/gpu/drm/i915/i915_gem.c:31:0: drivers/gpu/drm/i915/i915_gem.c: In function 'i915_gem_init_hw': >> drivers/gpu/drm/i915/i915_drv.h:2587:46: error: implicit declaration of function 'IS_KABYLAKE' [-Werror=implicit-function-declaration] #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) ^ >> drivers/gpu/drm/i915/i915_gem.c:4750:6: note: in expansion of macro 'HAS_GUC_UCODE' if (HAS_GUC_UCODE(dev)) { ^ cc1: some warnings being treated as errors -- In file included from drivers/gpu/drm/i915/intel_guc_loader.c:30:0: drivers/gpu/drm/i915/intel_guc_loader.c: In function 'intel_guc_ucode_init': drivers/gpu/drm/i915/i915_drv.h:2588:46: error: implicit declaration of function 'IS_KABYLAKE' [-Werror=implicit-function-declaration] #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) ^ >> drivers/gpu/drm/i915/intel_guc_loader.c:555:7: note: in expansion of macro 'HAS_GUC_SCHED' if (!HAS_GUC_SCHED(dev)) ^ cc1: some warnings being treated as errors vim +/IS_KABYLAKE +2587 drivers/gpu/drm/i915/i915_drv.h 2581 IS_SKYLAKE(dev)) 2582 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) 2583 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) 2584 2585 #define HAS_CSR(dev) (IS_GEN9(dev)) 2586 > 2587 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) 2588 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) 2589 2590 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/octet-stream, Size: 23761 bytes --] [-- Attachment #3: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake. 2015-10-29 17:22 ` [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now " Rodrigo Vivi 2015-10-29 17:22 ` [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake Rodrigo Vivi 2015-10-29 20:02 ` [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake kbuild test robot @ 2015-11-06 19:08 ` Yu Dai 2 siblings, 0 replies; 28+ messages in thread From: Yu Dai @ 2015-11-06 19:08 UTC (permalink / raw) To: intel-gfx On 10/29/2015 10:22 AM, Rodrigo Vivi wrote: > GuC has no version for KBL published yet and it is not recommended > to load the Skylake one, so let's avoid loading this for now while > we don't have the proper GuC firmware for Kabylake. > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index a5ba485..0e971cf 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2616,8 +2616,8 @@ struct drm_i915_cmd_table { > > #define HAS_CSR(dev) (IS_GEN9(dev)) > > -#define HAS_GUC_UCODE(dev) (IS_GEN9(dev)) > -#define HAS_GUC_SCHED(dev) (IS_GEN9(dev)) > +#define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) > +#define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) > > #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ > INTEL_INFO(dev)->gen >= 8) Looks good to me. Reviewed-by: Alex Dai <yu.dai@intel.com> Alex _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2015-11-06 20:26 UTC | newest] Thread overview: 28+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-10-27 17:14 [PATCH 0/6] Kabylake patches V2 Rodrigo Vivi 2015-10-27 17:14 ` [PATCH 1/6] drm/i915: Define IS_BROXTON properly Rodrigo Vivi 2015-10-28 9:27 ` Jani Nikula 2015-10-27 17:14 ` [PATCH 2/6] drm/i915/kbl: Introduce Kabylake platform defition Rodrigo Vivi 2015-10-28 11:39 ` Jani Nikula 2015-10-28 11:16 ` [PATCH] " Rodrigo Vivi 2015-10-28 19:18 ` Jani Nikula 2015-10-28 19:31 ` Chris Wilson 2015-10-28 19:44 ` Rodrigo Vivi 2015-10-28 20:01 ` Chris Wilson 2015-10-27 17:14 ` [PATCH 3/6] drm/i915/kbl: Add Kabylake PCI ID Rodrigo Vivi 2015-10-28 19:19 ` [PATCH] " Rodrigo Vivi 2015-10-27 17:14 ` [PATCH 4/6] drm/i915/kbl: Add Kabylake GT4 " Rodrigo Vivi 2015-10-28 19:21 ` [PATCH] " Rodrigo Vivi 2015-10-28 19:49 ` Jani Nikula 2015-10-27 17:14 ` [PATCH 5/6] drm/i915/kbl: Use propper ddi buffer translation table for Kabylake ULT and ULX Rodrigo Vivi 2015-11-06 20:26 ` Paulo Zanoni 2015-10-27 17:14 ` [PATCH 6/6] drm/i915/kbl: Fix DMC load on Kabylake Rodrigo Vivi 2015-10-29 17:20 ` [PATCH] " Rodrigo Vivi 2015-10-29 17:58 ` kbuild test robot 2015-10-29 18:05 ` kbuild test robot 2015-10-29 17:22 ` [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now " Rodrigo Vivi 2015-10-29 17:22 ` [PATCH 2/2] drm/i915/kbl: Kabylake uses the same GMS values as Skylake Rodrigo Vivi 2015-10-29 17:53 ` kbuild test robot 2015-11-04 23:35 ` Rodrigo Vivi 2015-11-05 13:17 ` Jani Nikula 2015-10-29 20:02 ` [PATCH 1/2] drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake kbuild test robot 2015-11-06 19:08 ` Yu Dai
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