[PATCH 1/2] drm/i915: Apply broader WaRsDisableCoarsePowerGating for guc also

[PATCH 1/2] drm/i915: Apply broader WaRsDisableCoarsePowerGating for guc also

[Mika Kuoppala]

commit 344df9809f45 ("drm/i915/skl: Disable coarse power gating up until F0")
failed to take into account that the same workaround is used in guc
when forcewake is sampled.

Wrap the condition check inside a macro and use it in both places
to fix the guc side scope.

Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            | 5 +++++
 drivers/gpu/drm/i915/i915_guc_submission.c | 6 ++----
 drivers/gpu/drm/i915/intel_pm.c            | 4 +---
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18be127f5678..bd667a17ad96 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2564,6 +2564,11 @@ struct drm_i915_cmd_table {
 
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
+
+/* WaRsDisableCoarsePowerGating:skl,bxt */
+#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
+						 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
+						  IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
 /*
  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
  * even when in MSI mode. This results in spurious interrupt warnings if the
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 05aa7e61cbe0..9cc3b8474dae 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -158,10 +158,8 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
 
 	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
 	/* WaRsDisableCoarsePowerGating:skl,bxt */
-	if (!intel_enable_rc6(dev_priv->dev) ||
-	    IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
-	    (IS_SKL_GT3(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)) ||
-	    (IS_SKL_GT4(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
+	if (!intel_enable_rc6(dev) ||
+	    NEEDS_WaRsDisableCoarsePowerGating(dev))
 		data[1] = 0;
 	else
 		/* bit 0 and 1 are for Render and Media domain separately */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d385d9991eed..e1de96099924 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4713,9 +4713,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
 	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
 	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
 	 */
-	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
-	    ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
-	     IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
+	if (NEEDS_WaRsDisableCoarsePowerGating(dev))
 		I915_WRITE(GEN9_PG_ENABLE, 0);
 	else
 		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
-- 
2.5.0

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[PATCH 2/2] drm/i915: Enable coarse power gating only if rc6 is enabled

[Mika Kuoppala]

Do what the comment says and don't enable coarse power gating
is rc6 is disabled. With this the check then becomes identical
with the guc side check for forcewake sampling with same
workaround.

Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e1de96099924..4939a021990f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4713,7 +4713,8 @@ static void gen9_enable_rc6(struct drm_device *dev)
 	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
 	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
 	 */
-	if (NEEDS_WaRsDisableCoarsePowerGating(dev))
+	if (!intel_enable_rc6(dev) ||
+	    NEEDS_WaRsDisableCoarsePowerGating(dev))
 		I915_WRITE(GEN9_PG_ENABLE, 0);
 	else
 		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
-- 
2.5.0

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Re: [PATCH 1/2] drm/i915: Apply broader WaRsDisableCoarsePowerGating for guc also

[Kamble, Sagar A]

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

On 12/16/2015 10:48 PM, Mika Kuoppala wrote:
> commit 344df9809f45 ("drm/i915/skl: Disable coarse power gating up until F0")
> failed to take into account that the same workaround is used in guc
> when forcewake is sampled.
>
> Wrap the condition check inside a macro and use it in both places
> to fix the guc side scope.
>
> Cc: Dave Gordon <david.s.gordon@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h            | 5 +++++
>   drivers/gpu/drm/i915/i915_guc_submission.c | 6 ++----
>   drivers/gpu/drm/i915/intel_pm.c            | 4 +---
>   3 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 18be127f5678..bd667a17ad96 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2564,6 +2564,11 @@ struct drm_i915_cmd_table {
>   
>   /* Early gen2 have a totally busted CS tlb and require pinned batches. */
>   #define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
> +
> +/* WaRsDisableCoarsePowerGating:skl,bxt */
> +#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
> +						 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
> +						  IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
>   /*
>    * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
>    * even when in MSI mode. This results in spurious interrupt warnings if the
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 05aa7e61cbe0..9cc3b8474dae 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -158,10 +158,8 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
>   
>   	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
>   	/* WaRsDisableCoarsePowerGating:skl,bxt */
> -	if (!intel_enable_rc6(dev_priv->dev) ||
> -	    IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
> -	    (IS_SKL_GT3(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)) ||
> -	    (IS_SKL_GT4(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
> +	if (!intel_enable_rc6(dev) ||
> +	    NEEDS_WaRsDisableCoarsePowerGating(dev))
>   		data[1] = 0;
>   	else
>   		/* bit 0 and 1 are for Render and Media domain separately */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d385d9991eed..e1de96099924 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4713,9 +4713,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
>   	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
>   	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
>   	 */
> -	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
> -	    ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
> -	     IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
> +	if (NEEDS_WaRsDisableCoarsePowerGating(dev))
>   		I915_WRITE(GEN9_PG_ENABLE, 0);
>   	else
>   		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?

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