[PATCH 0/2] DPCD Backlight Control

[PATCH 0/2] DPCD Backlight Control

[Yetunde Adebisi]

These patches add support for Backlight Control using DPCD registers on eDP 
displays.

- Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h
A copy of this patch has also been sent to dri-devel list.

- Patch 2 Implements functionaly for DPCD Backlight Control 


Yetunde Adebisi (2):
  drm/dp: Add definition for Display Control DPCD Registers capability
    size
  drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/intel_dp.c               |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |   6 +
 drivers/gpu/drm/i915/intel_panel.c            |   4 +
 include/drm/drm_dp_helper.h                   |   1 +
 6 files changed, 193 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

-- 
1.9.3

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[PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size

[Yetunde Adebisi]

This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
 #define DP_RECEIVER_CAP_SIZE		0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
+#define EDP_DISPLAY_CTL_CAP_SIZE	3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.3

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[PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)

[Yetunde Adebisi]

This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.

It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.

v2: Moved backlight functions from intel_dp.c into a new file
intel_dp_aux_backlight.c. Also moved reading of eDP display control
registers to intel_dp_get_dpcd

v3: Correct some formatting mistakes

v4: Updated to use AUX backlight control if PWM control is not possible
	(Jani)
v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra

This patch depends on http://patchwork.freedesktop.org/patch/64253/

Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/intel_dp.c               |  17 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h              |   6 +
 drivers/gpu/drm/i915/intel_panel.c            |   4 +
 5 files changed, 192 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..41250cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
 	  dvo_tfp410.o \
 	  intel_crt.o \
 	  intel_ddi.o \
+	  intel_dp_aux_backlight.o \
 	  intel_dp_link_training.o \
 	  intel_dp_mst.o \
 	  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a073f04..9f8672e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3183,7 +3183,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
  * supposed to retry 3 times per the spec.
  */
-static ssize_t
+ssize_t
 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
 			void *buffer, size_t size)
 {
@@ -3850,7 +3850,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint8_t rev;
 
 	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
 				    sizeof(intel_dp->dpcd)) < 0)
@@ -3886,6 +3885,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 			DRM_DEBUG_KMS("PSR2 %s on sink",
 				dev_priv->psr.psr2_support ? "supported" : "not supported");
 		}
+
+		/* Read the eDP Display control capabilities registers */
+		memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
+		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+				(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
+						intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
+								sizeof(intel_dp->edp_dpcd)))
+			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
+					intel_dp->edp_dpcd);
 	}
 
 	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
@@ -3893,10 +3901,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
 
 	/* Intermediate frequency support */
-	if (is_edp(intel_dp) &&
-	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
-	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
-	    (rev >= 0x03)) { /* eDp v1.4 or higher */
+	if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
 		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 		int i;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
new file mode 100644
index 0000000..a5361d6
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
+{
+	uint8_t reg_val = 0;
+
+	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+			&reg_val, sizeof(reg_val)) < 0) {
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+				DP_EDP_DISPLAY_CONTROL_REGISTER);
+		return;
+	}
+	if (enable)
+		reg_val |= DP_EDP_BACKLIGHT_ENABLE;
+	else
+		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+
+	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+			reg_val) < 0) {
+		DRM_DEBUG_KMS("Failed to %s aux backlight\n",
+				enable ? "enable" : "disable");
+	}
+}
+
+/*
+ * Read the current backlight value from DPCD register(s) based
+ * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
+ */
+static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	uint8_t read_val[2] = { 0x0 };
+	uint16_t level = 0;
+
+	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+			&read_val, sizeof(read_val)) < 0) {
+		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
+				DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
+		return 0;
+	}
+	level = read_val[0];
+	if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+		level = (read_val[0] << 8 | read_val[1]);
+
+	return level;
+}
+
+/*
+ * Sends the current backlight level over the aux channel, checking if its using
+ * 8-bit or 16 bit value (MSB and LSB)
+ */
+static void
+intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	uint8_t vals[2] = { 0x0 };
+
+	vals[0] = level;
+
+	/* Write the MSB and/or LSB */
+	 if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
+		vals[0] = (level & 0xFF00) >> 8;
+		vals[1] = (level & 0xFF);
+	}
+	if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
+			vals, sizeof(vals)) < 0) {
+		DRM_DEBUG_KMS("Failed to write aux backlight level\n");
+		return;
+	}
+}
+
+static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	uint8_t dpcd_buf = 0;
+
+	set_aux_backlight_enable(intel_dp, true);
+
+	if ((intel_dp_dpcd_read_wake(&intel_dp->aux,
+			DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf, 1) == 1) &&
+			((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
+					DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET))
+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+				(dpcd_buf | DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD));
+}
+
+static void intel_dp_aux_disable_backlight(struct intel_connector *connector)
+{
+	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base), false);
+}
+
+static int intel_dp_aux_setup_backlight(struct intel_connector *connector,
+			enum pipe pipe)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+	struct intel_panel *panel = &connector->panel;
+
+	intel_dp_aux_enable_backlight(connector);
+
+	if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+		panel->backlight.max = 0xFFFF;
+	else
+		panel->backlight.max = 0xFF;
+
+	panel->backlight.min = 0;
+	panel->backlight.level = intel_dp_aux_get_backlight(connector);
+
+	panel->backlight.enabled = panel->backlight.level != 0;
+
+	return 0;
+}
+
+static bool
+intel_dp_aux_display_control_capable(struct intel_connector *connector)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+
+	/* Check the  eDP Display control capabilities registers to determine if
+	 * the panel can support backlight control over the aux channel
+	 */
+	if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
+			(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
+			!((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
+					(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
+
+		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
+		return true;
+	}
+	return false;
+}
+
+int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
+{
+	struct intel_panel *panel = &intel_connector->panel;
+
+	if (!intel_dp_aux_display_control_capable(intel_connector))
+		return -ENODEV;
+
+	panel->backlight.setup = intel_dp_aux_setup_backlight;
+	panel->backlight.enable = intel_dp_aux_enable_backlight;
+	panel->backlight.disable = intel_dp_aux_disable_backlight;
+	panel->backlight.set = intel_dp_aux_set_backlight;
+	panel->backlight.get = intel_dp_aux_get_backlight;
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 93ba14a..e19ee22 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -761,6 +761,7 @@ struct intel_dp {
 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 	uint8_t num_sink_rates;
 	int sink_rates[DP_MAX_SUPPORTED_RATES];
@@ -1287,6 +1288,11 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
 bool
 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
+ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
+		void *buffer, size_t size);
+
+/* intel_dp_aux_backlight.c */
+int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
 
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 21ee647..941c6fe 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1720,6 +1720,10 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
 		container_of(panel, struct intel_connector, panel);
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 
+	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
+			intel_dp_aux_init_backlight_funcs(connector) == 0)
+		return;
+
 	if (IS_BROXTON(dev_priv)) {
 		panel->backlight.setup = bxt_setup_backlight;
 		panel->backlight.enable = bxt_enable_backlight;
-- 
1.9.3

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Re: [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)

[Thulasimani, Sivakumar]

On 2/5/2016 5:48 PM, Yetunde Adebisi wrote:
> This patch adds support for eDP backlight control using DPCD registers to
> backlight hooks in intel_panel.
>
> It checks for backlight control over AUX channel capability and sets up
> function pointers to get and set the backlight brightness level if
> supported.
>
> v2: Moved backlight functions from intel_dp.c into a new file
> intel_dp_aux_backlight.c. Also moved reading of eDP display control
> registers to intel_dp_get_dpcd
>
> v3: Correct some formatting mistakes
>
> v4: Updated to use AUX backlight control if PWM control is not possible
> 	(Jani)
> v5: Moved call to initialize backlight registers to dp_aux_setup_backlight
> v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before setting up AUX
> backlight control. To fix BLM_PWM_ENABLE igt test warnings on bdw_ultra
>
> This patch depends on http://patchwork.freedesktop.org/patch/64253/
>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile                 |   1 +
>   drivers/gpu/drm/i915/intel_dp.c               |  17 ++-
>   drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170 ++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_drv.h              |   6 +
>   drivers/gpu/drm/i915/intel_panel.c            |   4 +
>   5 files changed, 192 insertions(+), 6 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 0851de07..41250cc 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
>   	  dvo_tfp410.o \
>   	  intel_crt.o \
>   	  intel_ddi.o \
> +	  intel_dp_aux_backlight.o \
>   	  intel_dp_link_training.o \
>   	  intel_dp_mst.o \
>   	  intel_dp.o \
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a073f04..9f8672e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3183,7 +3183,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
>    * Sinks are *supposed* to come up within 1ms from an off state, but we're also
>    * supposed to retry 3 times per the spec.
>    */
> -static ssize_t
> +ssize_t
>   intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
>   			void *buffer, size_t size)
>   {
> @@ -3850,7 +3850,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>   	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>   	struct drm_device *dev = dig_port->base.base.dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> -	uint8_t rev;
>   
>   	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
>   				    sizeof(intel_dp->dpcd)) < 0)
> @@ -3886,6 +3885,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>   			DRM_DEBUG_KMS("PSR2 %s on sink",
>   				dev_priv->psr.psr2_support ? "supported" : "not supported");
>   		}
> +
> +		/* Read the eDP Display control capabilities registers */
> +		memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
> +		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> +				(intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
> +						intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
> +								sizeof(intel_dp->edp_dpcd)))
> +			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
> +					intel_dp->edp_dpcd);
>   	}
>   
>   	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
> @@ -3893,10 +3901,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>   		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
>   
>   	/* Intermediate frequency support */
> -	if (is_edp(intel_dp) &&
> -	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> -	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
> -	    (rev >= 0x03)) { /* eDp v1.4 or higher */
> +	if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
>   		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
>   		int i;
>   
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> new file mode 100644
> index 0000000..a5361d6
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -0,0 +1,170 @@
> +/*
> + * Copyright © 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "intel_drv.h"
> +
> +static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
> +{
> +	uint8_t reg_val = 0;
> +
> +	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
> +			&reg_val, sizeof(reg_val)) < 0) {
> +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> +				DP_EDP_DISPLAY_CONTROL_REGISTER);
> +		return;
> +	}
> +	if (enable)
> +		reg_val |= DP_EDP_BACKLIGHT_ENABLE;
> +	else
> +		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> +
> +	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
> +			reg_val) < 0) {
> +		DRM_DEBUG_KMS("Failed to %s aux backlight\n",
> +				enable ? "enable" : "disable");
> +	}
> +}
> +
> +/*
> + * Read the current backlight value from DPCD register(s) based
> + * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
> + */
> +static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	uint8_t read_val[2] = { 0x0 };
> +	uint16_t level = 0;
> +
> +	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
> +			&read_val, sizeof(read_val)) < 0) {
> +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> +				DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
> +		return 0;
> +	}
> +	level = read_val[0];
> +	if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> +		level = (read_val[0] << 8 | read_val[1]);
> +
> +	return level;
> +}
> +
> +/*
> + * Sends the current backlight level over the aux channel, checking if its using
> + * 8-bit or 16 bit value (MSB and LSB)
> + */
> +static void
> +intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	uint8_t vals[2] = { 0x0 };
> +
> +	vals[0] = level;
> +
> +	/* Write the MSB and/or LSB */
> +	 if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
> +		vals[0] = (level & 0xFF00) >> 8;
> +		vals[1] = (level & 0xFF);
> +	}
> +	if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
> +			vals, sizeof(vals)) < 0) {
> +		DRM_DEBUG_KMS("Failed to write aux backlight level\n");
> +		return;
> +	}
> +}
> +
> +static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	uint8_t dpcd_buf = 0;
> +
> +	set_aux_backlight_enable(intel_dp, true);
> +
> +	if ((intel_dp_dpcd_read_wake(&intel_dp->aux,
> +			DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf, 1) == 1) &&
> +			((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
> +					DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET))
> +		drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
> +				(dpcd_buf | DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD));
> +}
> +
> +static void intel_dp_aux_disable_backlight(struct intel_connector *connector)
> +{
> +	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base), false);
> +}
> +
> +static int intel_dp_aux_setup_backlight(struct intel_connector *connector,
> +			enum pipe pipe)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +	struct intel_panel *panel = &connector->panel;
> +
> +	intel_dp_aux_enable_backlight(connector);
> +
> +	if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> +		panel->backlight.max = 0xFFFF;
> +	else
> +		panel->backlight.max = 0xFF;
> +
> +	panel->backlight.min = 0;
> +	panel->backlight.level = intel_dp_aux_get_backlight(connector);
> +
> +	panel->backlight.enabled = panel->backlight.level != 0;
> +
> +	return 0;
> +}
> +
> +static bool
> +intel_dp_aux_display_control_capable(struct intel_connector *connector)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> +
> +	/* Check the  eDP Display control capabilities registers to determine if
> +	 * the panel can support backlight control over the aux channel
> +	 */
> +	if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> +			(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> +			!((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
> +					(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
> +
> +		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
> +		return true;
> +	}
> +	return false;
> +}
> +
> +int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
> +{
> +	struct intel_panel *panel = &intel_connector->panel;
> +
> +	if (!intel_dp_aux_display_control_capable(intel_connector))
> +		return -ENODEV;
> +
> +	panel->backlight.setup = intel_dp_aux_setup_backlight;
> +	panel->backlight.enable = intel_dp_aux_enable_backlight;
> +	panel->backlight.disable = intel_dp_aux_disable_backlight;
> +	panel->backlight.set = intel_dp_aux_set_backlight;
> +	panel->backlight.get = intel_dp_aux_get_backlight;
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 93ba14a..e19ee22 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -761,6 +761,7 @@ struct intel_dp {
>   	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
>   	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>   	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> +	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
>   	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
>   	uint8_t num_sink_rates;
>   	int sink_rates[DP_MAX_SUPPORTED_RATES];
> @@ -1287,6 +1288,11 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
>   bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
>   bool
>   intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
> +ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
> +		void *buffer, size_t size);
> +
> +/* intel_dp_aux_backlight.c */
> +int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
>   
>   /* intel_dp_mst.c */
>   int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 21ee647..941c6fe 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1720,6 +1720,10 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
>   		container_of(panel, struct intel_connector, panel);
>   	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>   
> +	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
> +			intel_dp_aux_init_backlight_funcs(connector) == 0)
> +		return;
> +
can we make this feature to be enabled explicitly rather than if the panel
supports it ? we have never checked for these dpcd registers till now 
and it is
quite possible for any one panel to pass this even though we
are using it with PWM based control at present. i.e we keep PSR disabled
still since it is not working always, why should we enable this by 
default :).

i understand i am late to this thread, but good to check late at-least.
did you test with DPST disabled or does this affect the panel usability
with dpst enabled or disabled ?
Sivakumar
>   	if (IS_BROXTON(dev_priv)) {
>   		panel->backlight.setup = bxt_setup_backlight;
>   		panel->backlight.enable = bxt_enable_backlight;

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Re: [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)

[Adebisi, YetundeX]

> -----Original Message-----
> From: Thulasimani, Sivakumar
> Sent: Monday, February 08, 2016 8:57 AM
> To: Adebisi, YetundeX; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using
> DPCD for eDP connectors (v6)
> 
> 
> 
> On 2/5/2016 5:48 PM, Yetunde Adebisi wrote:
> > This patch adds support for eDP backlight control using DPCD registers
> > to backlight hooks in intel_panel.
> >
> > It checks for backlight control over AUX channel capability and sets
> > up function pointers to get and set the backlight brightness level if
> > supported.
> >
> > v2: Moved backlight functions from intel_dp.c into a new file
> > intel_dp_aux_backlight.c. Also moved reading of eDP display control
> > registers to intel_dp_get_dpcd
> >
> > v3: Correct some formatting mistakes
> >
> > v4: Updated to use AUX backlight control if PWM control is not possible
> > 	(Jani)
> > v5: Moved call to initialize backlight registers to
> > dp_aux_setup_backlight
> > v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before
> setting
> > up AUX backlight control. To fix BLM_PWM_ENABLE igt test warnings on
> > bdw_ultra
> >
> > This patch depends on http://patchwork.freedesktop.org/patch/64253/
> >
> > Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
> > ---
> >   drivers/gpu/drm/i915/Makefile                 |   1 +
> >   drivers/gpu/drm/i915/intel_dp.c               |  17 ++-
> >   drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170
> ++++++++++++++++++++++++++
> >   drivers/gpu/drm/i915/intel_drv.h              |   6 +
> >   drivers/gpu/drm/i915/intel_panel.c            |   4 +
> >   5 files changed, 192 insertions(+), 6 deletions(-)
> >   create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index 0851de07..41250cc 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
> >   	  dvo_tfp410.o \
> >   	  intel_crt.o \
> >   	  intel_ddi.o \
> > +	  intel_dp_aux_backlight.o \
> >   	  intel_dp_link_training.o \
> >   	  intel_dp_mst.o \
> >   	  intel_dp.o \
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c index a073f04..9f8672e 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3183,7 +3183,7 @@ static void chv_dp_post_pll_disable(struct
> intel_encoder *encoder)
> >    * Sinks are *supposed* to come up within 1ms from an off state, but
> we're also
> >    * supposed to retry 3 times per the spec.
> >    */
> > -static ssize_t
> > +ssize_t
> >   intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
> >   			void *buffer, size_t size)
> >   {
> > @@ -3850,7 +3850,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> >   	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >   	struct drm_device *dev = dig_port->base.base.dev;
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	uint8_t rev;
> >
> >   	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp-
> >dpcd,
> >   				    sizeof(intel_dp->dpcd)) < 0) @@ -3886,6
> +3885,15 @@
> > intel_dp_get_dpcd(struct intel_dp *intel_dp)
> >   			DRM_DEBUG_KMS("PSR2 %s on sink",
> >   				dev_priv->psr.psr2_support ? "supported" :
> "not supported");
> >   		}
> > +
> > +		/* Read the eDP Display control capabilities registers */
> > +		memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp-
> >edp_dpcd));
> > +		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &
> DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> > +				(intel_dp_dpcd_read_wake(&intel_dp->aux,
> DP_EDP_DPCD_REV,
> > +						intel_dp->edp_dpcd,
> sizeof(intel_dp->edp_dpcd)) ==
> > +
> 	sizeof(intel_dp->edp_dpcd)))
> > +			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int)
> sizeof(intel_dp->edp_dpcd),
> > +					intel_dp->edp_dpcd);
> >   	}
> >
> >   	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink
> %s\n", @@
> > -3893,10 +3901,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> >   		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
> >
> >   	/* Intermediate frequency support */
> > -	if (is_edp(intel_dp) &&
> > -	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &
> 	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> > -	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
> &rev, 1) == 1) &&
> > -	    (rev >= 0x03)) { /* eDp v1.4 or higher */
> > +	if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp
> > +v1.4 or higher */
> >   		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
> >   		int i;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > new file mode 100644
> > index 0000000..a5361d6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > @@ -0,0 +1,170 @@
> > +/*
> > + * Copyright © 2015 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN
> NO EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> > +OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#include "intel_drv.h"
> > +
> > +static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool
> > +enable) {
> > +	uint8_t reg_val = 0;
> > +
> > +	if (intel_dp_dpcd_read_wake(&intel_dp->aux,
> DP_EDP_DISPLAY_CONTROL_REGISTER,
> > +			&reg_val, sizeof(reg_val)) < 0) {
> > +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> > +				DP_EDP_DISPLAY_CONTROL_REGISTER);
> > +		return;
> > +	}
> > +	if (enable)
> > +		reg_val |= DP_EDP_BACKLIGHT_ENABLE;
> > +	else
> > +		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> > +
> > +	if (drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_EDP_DISPLAY_CONTROL_REGISTER,
> > +			reg_val) < 0) {
> > +		DRM_DEBUG_KMS("Failed to %s aux backlight\n",
> > +				enable ? "enable" : "disable");
> > +	}
> > +}
> > +
> > +/*
> > + * Read the current backlight value from DPCD register(s) based
> > + * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported  */
> > +static uint32_t intel_dp_aux_get_backlight(struct intel_connector
> > +*connector) {
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-
> >base);
> > +	uint8_t read_val[2] = { 0x0 };
> > +	uint16_t level = 0;
> > +
> > +	if (intel_dp_dpcd_read_wake(&intel_dp->aux,
> DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
> > +			&read_val, sizeof(read_val)) < 0) {
> > +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> > +				DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
> > +		return 0;
> > +	}
> > +	level = read_val[0];
> > +	if (intel_dp->edp_dpcd[2] &
> DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> > +		level = (read_val[0] << 8 | read_val[1]);
> > +
> > +	return level;
> > +}
> > +
> > +/*
> > + * Sends the current backlight level over the aux channel, checking
> > +if its using
> > + * 8-bit or 16 bit value (MSB and LSB)  */ static void
> > +intel_dp_aux_set_backlight(struct intel_connector *connector, u32
> > +level) {
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-
> >base);
> > +	uint8_t vals[2] = { 0x0 };
> > +
> > +	vals[0] = level;
> > +
> > +	/* Write the MSB and/or LSB */
> > +	 if (intel_dp->edp_dpcd[2] &
> DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
> > +		vals[0] = (level & 0xFF00) >> 8;
> > +		vals[1] = (level & 0xFF);
> > +	}
> > +	if (drm_dp_dpcd_write(&intel_dp->aux,
> DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
> > +			vals, sizeof(vals)) < 0) {
> > +		DRM_DEBUG_KMS("Failed to write aux backlight level\n");
> > +		return;
> > +	}
> > +}
> > +
> > +static void intel_dp_aux_enable_backlight(struct intel_connector
> > +*connector) {
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-
> >base);
> > +	uint8_t dpcd_buf = 0;
> > +
> > +	set_aux_backlight_enable(intel_dp, true);
> > +
> > +	if ((intel_dp_dpcd_read_wake(&intel_dp->aux,
> > +			DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
> &dpcd_buf, 1) == 1) &&
> > +			((dpcd_buf &
> DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
> > +
> 	DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET))
> > +		drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
> > +				(dpcd_buf |
> DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD));
> > +}
> > +
> > +static void intel_dp_aux_disable_backlight(struct intel_connector
> > +*connector) {
> > +	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder-
> >base),
> > +false); }
> > +
> > +static int intel_dp_aux_setup_backlight(struct intel_connector
> *connector,
> > +			enum pipe pipe)
> > +{
> > +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-
> >base);
> > +	struct intel_panel *panel = &connector->panel;
> > +
> > +	intel_dp_aux_enable_backlight(connector);
> > +
> > +	if (intel_dp->edp_dpcd[2] &
> DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> > +		panel->backlight.max = 0xFFFF;
> > +	else
> > +		panel->backlight.max = 0xFF;
> > +
> > +	panel->backlight.min = 0;
> > +	panel->backlight.level = intel_dp_aux_get_backlight(connector);
> > +
> > +	panel->backlight.enabled = panel->backlight.level != 0;
> > +
> > +	return 0;
> > +}
> > +
> > +static bool
> > +intel_dp_aux_display_control_capable(struct intel_connector
> > +*connector) {
> > +	struct intel_dp *intel_dp =
> > +enc_to_intel_dp(&connector->encoder->base);
> > +
> > +	/* Check the  eDP Display control capabilities registers to determine if
> > +	 * the panel can support backlight control over the aux channel
> > +	 */
> > +	if (intel_dp->edp_dpcd[1] &
> DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> > +			(intel_dp->edp_dpcd[1] &
> DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> > +			!((intel_dp->edp_dpcd[1] &
> DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
> > +					(intel_dp->edp_dpcd[2] &
> > +DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
> > +
> > +		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
> > +		return true;
> > +	}
> > +	return false;
> > +}
> > +
> > +int intel_dp_aux_init_backlight_funcs(struct intel_connector
> > +*intel_connector) {
> > +	struct intel_panel *panel = &intel_connector->panel;
> > +
> > +	if (!intel_dp_aux_display_control_capable(intel_connector))
> > +		return -ENODEV;
> > +
> > +	panel->backlight.setup = intel_dp_aux_setup_backlight;
> > +	panel->backlight.enable = intel_dp_aux_enable_backlight;
> > +	panel->backlight.disable = intel_dp_aux_disable_backlight;
> > +	panel->backlight.set = intel_dp_aux_set_backlight;
> > +	panel->backlight.get = intel_dp_aux_get_backlight;
> > +
> > +	return 0;
> > +}
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 93ba14a..e19ee22 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -761,6 +761,7 @@ struct intel_dp {
> >   	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
> >   	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> >   	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> > +	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> >   	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
> >   	uint8_t num_sink_rates;
> >   	int sink_rates[DP_MAX_SUPPORTED_RATES];
> > @@ -1287,6 +1288,11 @@ void intel_dp_compute_rate(struct intel_dp
> *intel_dp, int port_clock,
> >   bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> >   bool
> >   intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t
> > link_status[DP_LINK_STATUS_SIZE]);
> > +ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int
> offset,
> > +		void *buffer, size_t size);
> > +
> > +/* intel_dp_aux_backlight.c */
> > +int intel_dp_aux_init_backlight_funcs(struct intel_connector
> > +*intel_connector);
> >
> >   /* intel_dp_mst.c */
> >   int intel_dp_mst_encoder_init(struct intel_digital_port
> > *intel_dig_port, int conn_id); diff --git
> > a/drivers/gpu/drm/i915/intel_panel.c
> > b/drivers/gpu/drm/i915/intel_panel.c
> > index 21ee647..941c6fe 100644
> > --- a/drivers/gpu/drm/i915/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > @@ -1720,6 +1720,10 @@ intel_panel_init_backlight_funcs(struct
> intel_panel *panel)
> >   		container_of(panel, struct intel_connector, panel);
> >   	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> >
> > +	if (connector->base.connector_type ==
> DRM_MODE_CONNECTOR_eDP &&
> > +			intel_dp_aux_init_backlight_funcs(connector) == 0)
> > +		return;
> > +
> can we make this feature to be enabled explicitly rather than if the panel
> supports it ? we have never checked for these dpcd registers till now and it is
> quite possible for any one panel to pass this even though we are using it with
> PWM based control at present. i.e we keep PSR disabled still since it is not
> working always, why should we enable this by default :).

I can do that if there is no objection. Something like enable_dcpd_backlight parameter?

> 
> i understand i am late to this thread, but good to check late at-least.
> did you test with DPST disabled or does this affect the panel usability with
> dpst enabled or disabled ?
> Sivakumar

I have not tested it with DPST, how do I enable DPST? 

> >   	if (IS_BROXTON(dev_priv)) {
> >   		panel->backlight.setup = bxt_setup_backlight;
> >   		panel->backlight.enable = bxt_enable_backlight;

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Re: [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)

[Thulasimani, Sivakumar]

On 2/9/2016 6:41 PM, Adebisi, YetundeX wrote:
>
>> -----Original Message-----
>> From: Thulasimani, Sivakumar
>> Sent: Monday, February 08, 2016 8:57 AM
>> To: Adebisi, YetundeX; intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani
>> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using
>> DPCD for eDP connectors (v6)
>>
>>
>>
>> On 2/5/2016 5:48 PM, Yetunde Adebisi wrote:
>>> This patch adds support for eDP backlight control using DPCD registers
>>> to backlight hooks in intel_panel.
>>>
>>> It checks for backlight control over AUX channel capability and sets
>>> up function pointers to get and set the backlight brightness level if
>>> supported.
>>>
>>> v2: Moved backlight functions from intel_dp.c into a new file
>>> intel_dp_aux_backlight.c. Also moved reading of eDP display control
>>> registers to intel_dp_get_dpcd
>>>
>>> v3: Correct some formatting mistakes
>>>
>>> v4: Updated to use AUX backlight control if PWM control is not possible
>>> 	(Jani)
>>> v5: Moved call to initialize backlight registers to
>>> dp_aux_setup_backlight
>>> v6: Check DP_EDP_BACKLIGHT_PIN_ENABLE_CAP is disabled before
>> setting
>>> up AUX backlight control. To fix BLM_PWM_ENABLE igt test warnings on
>>> bdw_ultra
>>>
>>> This patch depends on http://patchwork.freedesktop.org/patch/64253/
>>>
>>> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>>> Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/Makefile                 |   1 +
>>>    drivers/gpu/drm/i915/intel_dp.c               |  17 ++-
>>>    drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 170
>> ++++++++++++++++++++++++++
>>>    drivers/gpu/drm/i915/intel_drv.h              |   6 +
>>>    drivers/gpu/drm/i915/intel_panel.c            |   4 +
>>>    5 files changed, 192 insertions(+), 6 deletions(-)
>>>    create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c
>>>
>>> diff --git a/drivers/gpu/drm/i915/Makefile
>>> b/drivers/gpu/drm/i915/Makefile index 0851de07..41250cc 100644
>>> --- a/drivers/gpu/drm/i915/Makefile
>>> +++ b/drivers/gpu/drm/i915/Makefile
>>> @@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \
>>>    	  dvo_tfp410.o \
>>>    	  intel_crt.o \
>>>    	  intel_ddi.o \
>>> +	  intel_dp_aux_backlight.o \
>>>    	  intel_dp_link_training.o \
>>>    	  intel_dp_mst.o \
>>>    	  intel_dp.o \
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>>> b/drivers/gpu/drm/i915/intel_dp.c index a073f04..9f8672e 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -3183,7 +3183,7 @@ static void chv_dp_post_pll_disable(struct
>> intel_encoder *encoder)
>>>     * Sinks are *supposed* to come up within 1ms from an off state, but
>> we're also
>>>     * supposed to retry 3 times per the spec.
>>>     */
>>> -static ssize_t
>>> +ssize_t
>>>    intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
>>>    			void *buffer, size_t size)
>>>    {
>>> @@ -3850,7 +3850,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>>>    	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>>    	struct drm_device *dev = dig_port->base.base.dev;
>>>    	struct drm_i915_private *dev_priv = dev->dev_private;
>>> -	uint8_t rev;
>>>
>>>    	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp-
>>> dpcd,
>>>    				    sizeof(intel_dp->dpcd)) < 0) @@ -3886,6
>> +3885,15 @@
>>> intel_dp_get_dpcd(struct intel_dp *intel_dp)
>>>    			DRM_DEBUG_KMS("PSR2 %s on sink",
>>>    				dev_priv->psr.psr2_support ? "supported" :
>> "not supported");
>>>    		}
>>> +
>>> +		/* Read the eDP Display control capabilities registers */
>>> +		memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp-
>>> edp_dpcd));
>>> +		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &
>> DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
>>> +				(intel_dp_dpcd_read_wake(&intel_dp->aux,
>> DP_EDP_DPCD_REV,
>>> +						intel_dp->edp_dpcd,
>> sizeof(intel_dp->edp_dpcd)) ==
>>> +
>> 	sizeof(intel_dp->edp_dpcd)))
>>> +			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int)
>> sizeof(intel_dp->edp_dpcd),
>>> +					intel_dp->edp_dpcd);
>>>    	}
>>>
>>>    	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink
>> %s\n", @@
>>> -3893,10 +3901,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>>>    		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
>>>
>>>    	/* Intermediate frequency support */
>>> -	if (is_edp(intel_dp) &&
>>> -	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &
>> 	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
>>> -	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
>> &rev, 1) == 1) &&
>>> -	    (rev >= 0x03)) { /* eDp v1.4 or higher */
>>> +	if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp
>>> +v1.4 or higher */
>>>    		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
>>>    		int i;
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
>>> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
>>> new file mode 100644
>>> index 0000000..a5361d6
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
>>> @@ -0,0 +1,170 @@
>>> +/*
>>> + * Copyright © 2015 Intel Corporation
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person
>>> +obtaining a
>>> + * copy of this software and associated documentation files (the
>>> +"Software"),
>>> + * to deal in the Software without restriction, including without
>>> +limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>> +sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom
>>> +the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including
>>> +the next
>>> + * paragraph) shall be included in all copies or substantial portions
>>> +of the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
>> KIND,
>>> +EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>> +MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN
>> NO EVENT
>>> +SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
>> DAMAGES
>>> +OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>> OTHERWISE,
>>> +ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
>> OR
>>> +OTHER DEALINGS
>>> + * IN THE SOFTWARE.
>>> + *
>>> + */
>>> +
>>> +#include "intel_drv.h"
>>> +
>>> +static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool
>>> +enable) {
>>> +	uint8_t reg_val = 0;
>>> +
>>> +	if (intel_dp_dpcd_read_wake(&intel_dp->aux,
>> DP_EDP_DISPLAY_CONTROL_REGISTER,
>>> +			&reg_val, sizeof(reg_val)) < 0) {
>>> +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
>>> +				DP_EDP_DISPLAY_CONTROL_REGISTER);
>>> +		return;
>>> +	}
>>> +	if (enable)
>>> +		reg_val |= DP_EDP_BACKLIGHT_ENABLE;
>>> +	else
>>> +		reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
>>> +
>>> +	if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> DP_EDP_DISPLAY_CONTROL_REGISTER,
>>> +			reg_val) < 0) {
>>> +		DRM_DEBUG_KMS("Failed to %s aux backlight\n",
>>> +				enable ? "enable" : "disable");
>>> +	}
>>> +}
>>> +
>>> +/*
>>> + * Read the current backlight value from DPCD register(s) based
>>> + * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported  */
>>> +static uint32_t intel_dp_aux_get_backlight(struct intel_connector
>>> +*connector) {
>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-
>>> base);
>>> +	uint8_t read_val[2] = { 0x0 };
>>> +	uint16_t level = 0;
>>> +
>>> +	if (intel_dp_dpcd_read_wake(&intel_dp->aux,
>> DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
>>> +			&read_val, sizeof(read_val)) < 0) {
>>> +		DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
>>> +				DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
>>> +		return 0;
>>> +	}
>>> +	level = read_val[0];
>>> +	if (intel_dp->edp_dpcd[2] &
>> DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
>>> +		level = (read_val[0] << 8 | read_val[1]);
>>> +
>>> +	return level;
>>> +}
>>> +
>>> +/*
>>> + * Sends the current backlight level over the aux channel, checking
>>> +if its using
>>> + * 8-bit or 16 bit value (MSB and LSB)  */ static void
>>> +intel_dp_aux_set_backlight(struct intel_connector *connector, u32
>>> +level) {
>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-
>>> base);
>>> +	uint8_t vals[2] = { 0x0 };
>>> +
>>> +	vals[0] = level;
>>> +
>>> +	/* Write the MSB and/or LSB */
>>> +	 if (intel_dp->edp_dpcd[2] &
>> DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
>>> +		vals[0] = (level & 0xFF00) >> 8;
>>> +		vals[1] = (level & 0xFF);
>>> +	}
>>> +	if (drm_dp_dpcd_write(&intel_dp->aux,
>> DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
>>> +			vals, sizeof(vals)) < 0) {
>>> +		DRM_DEBUG_KMS("Failed to write aux backlight level\n");
>>> +		return;
>>> +	}
>>> +}
>>> +
>>> +static void intel_dp_aux_enable_backlight(struct intel_connector
>>> +*connector) {
>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-
>>> base);
>>> +	uint8_t dpcd_buf = 0;
>>> +
>>> +	set_aux_backlight_enable(intel_dp, true);
>>> +
>>> +	if ((intel_dp_dpcd_read_wake(&intel_dp->aux,
>>> +			DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
>> &dpcd_buf, 1) == 1) &&
>>> +			((dpcd_buf &
>> DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
>>> +
>> 	DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET))
>>> +		drm_dp_dpcd_writeb(&intel_dp->aux,
>> DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
>>> +				(dpcd_buf |
>> DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD));
>>> +}
>>> +
>>> +static void intel_dp_aux_disable_backlight(struct intel_connector
>>> +*connector) {
>>> +	set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder-
>>> base),
>>> +false); }
>>> +
>>> +static int intel_dp_aux_setup_backlight(struct intel_connector
>> *connector,
>>> +			enum pipe pipe)
>>> +{
>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder-
>>> base);
>>> +	struct intel_panel *panel = &connector->panel;
>>> +
>>> +	intel_dp_aux_enable_backlight(connector);
>>> +
>>> +	if (intel_dp->edp_dpcd[2] &
>> DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
>>> +		panel->backlight.max = 0xFFFF;
>>> +	else
>>> +		panel->backlight.max = 0xFF;
>>> +
>>> +	panel->backlight.min = 0;
>>> +	panel->backlight.level = intel_dp_aux_get_backlight(connector);
>>> +
>>> +	panel->backlight.enabled = panel->backlight.level != 0;
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static bool
>>> +intel_dp_aux_display_control_capable(struct intel_connector
>>> +*connector) {
>>> +	struct intel_dp *intel_dp =
>>> +enc_to_intel_dp(&connector->encoder->base);
>>> +
>>> +	/* Check the  eDP Display control capabilities registers to determine if
>>> +	 * the panel can support backlight control over the aux channel
>>> +	 */
>>> +	if (intel_dp->edp_dpcd[1] &
>> DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
>>> +			(intel_dp->edp_dpcd[1] &
>> DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
>>> +			!((intel_dp->edp_dpcd[1] &
>> DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
>>> +					(intel_dp->edp_dpcd[2] &
>>> +DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
>>> +
>>> +		DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
>>> +		return true;
>>> +	}
>>> +	return false;
>>> +}
>>> +
>>> +int intel_dp_aux_init_backlight_funcs(struct intel_connector
>>> +*intel_connector) {
>>> +	struct intel_panel *panel = &intel_connector->panel;
>>> +
>>> +	if (!intel_dp_aux_display_control_capable(intel_connector))
>>> +		return -ENODEV;
>>> +
>>> +	panel->backlight.setup = intel_dp_aux_setup_backlight;
>>> +	panel->backlight.enable = intel_dp_aux_enable_backlight;
>>> +	panel->backlight.disable = intel_dp_aux_disable_backlight;
>>> +	panel->backlight.set = intel_dp_aux_set_backlight;
>>> +	panel->backlight.get = intel_dp_aux_get_backlight;
>>> +
>>> +	return 0;
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>>> b/drivers/gpu/drm/i915/intel_drv.h
>>> index 93ba14a..e19ee22 100644
>>> --- a/drivers/gpu/drm/i915/intel_drv.h
>>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>>> @@ -761,6 +761,7 @@ struct intel_dp {
>>>    	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
>>>    	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>>>    	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>>> +	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
>>>    	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
>>>    	uint8_t num_sink_rates;
>>>    	int sink_rates[DP_MAX_SUPPORTED_RATES];
>>> @@ -1287,6 +1288,11 @@ void intel_dp_compute_rate(struct intel_dp
>> *intel_dp, int port_clock,
>>>    bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
>>>    bool
>>>    intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t
>>> link_status[DP_LINK_STATUS_SIZE]);
>>> +ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int
>> offset,
>>> +		void *buffer, size_t size);
>>> +
>>> +/* intel_dp_aux_backlight.c */
>>> +int intel_dp_aux_init_backlight_funcs(struct intel_connector
>>> +*intel_connector);
>>>
>>>    /* intel_dp_mst.c */
>>>    int intel_dp_mst_encoder_init(struct intel_digital_port
>>> *intel_dig_port, int conn_id); diff --git
>>> a/drivers/gpu/drm/i915/intel_panel.c
>>> b/drivers/gpu/drm/i915/intel_panel.c
>>> index 21ee647..941c6fe 100644
>>> --- a/drivers/gpu/drm/i915/intel_panel.c
>>> +++ b/drivers/gpu/drm/i915/intel_panel.c
>>> @@ -1720,6 +1720,10 @@ intel_panel_init_backlight_funcs(struct
>> intel_panel *panel)
>>>    		container_of(panel, struct intel_connector, panel);
>>>    	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>>>
>>> +	if (connector->base.connector_type ==
>> DRM_MODE_CONNECTOR_eDP &&
>>> +			intel_dp_aux_init_backlight_funcs(connector) == 0)
>>> +		return;
>>> +
>> can we make this feature to be enabled explicitly rather than if the panel
>> supports it ? we have never checked for these dpcd registers till now and it is
>> quite possible for any one panel to pass this even though we are using it with
>> PWM based control at present. i.e we keep PSR disabled still since it is not
>> working always, why should we enable this by default :).
> I can do that if there is no objection. Something like enable_dcpd_backlight parameter?
yes,that should make this better. anything that can avoid a regression 
is good :).
>> i understand i am late to this thread, but good to check late at-least.
>> did you test with DPST disabled or does this affect the panel usability with
>> dpst enabled or disabled ?
>> Sivakumar
> I have not tested it with DPST, how do I enable DPST?
DPST should be on by default. in case you have not observed any
flickering or brightness changes during various contents then
it should be fine.

Sivakumar
>>>    	if (IS_BROXTON(dev_priv)) {
>>>    		panel->backlight.setup = bxt_setup_backlight;
>>>    		panel->backlight.enable = bxt_enable_backlight;

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✓ Fi.CI.BAT: success for DPCD Backlight Control (rev3)

[Patchwork]

== Summary ==

Series 1864v3 DPCD Backlight Control
http://patchwork.freedesktop.org/api/1.0/series/1864/revisions/3/mbox/

Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                pass       -> DMESG-WARN (ilk-hp8440p) UNSTABLE

bdw-nuci7        total:161  pass:152  dwarn:0   dfail:0   fail:0   skip:9  
bdw-ultra        total:164  pass:152  dwarn:0   dfail:0   fail:0   skip:12 
bsw-nuc-2        total:164  pass:136  dwarn:0   dfail:0   fail:0   skip:28 
byt-nuc          total:164  pass:141  dwarn:0   dfail:0   fail:0   skip:23 
hsw-brixbox      total:164  pass:151  dwarn:0   dfail:0   fail:0   skip:13 
hsw-gt2          total:164  pass:154  dwarn:0   dfail:0   fail:0   skip:10 
ilk-hp8440p      total:164  pass:114  dwarn:2   dfail:0   fail:0   skip:48 
skl-i7k-2        total:164  pass:149  dwarn:1   dfail:0   fail:0   skip:14 
snb-dellxps      total:164  pass:142  dwarn:0   dfail:0   fail:0   skip:22 
snb-x220t        total:164  pass:142  dwarn:0   dfail:0   fail:1   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1370/

57e229193395068adcb34c5266d54194e652869f drm-intel-nightly: 2016y-02m-04d-18h-38m-55s UTC integration manifest
d492a5ab6749af90c6cab465184a10ba751fa63a drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)
b1ff81d3779295705ac8b86088e616c5a43e1d85 drm/dp: Add definition for Display Control DPCD Registers capability size

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