From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arun Siluvery Subject: Re: [PATCH] drm/i915/lrc: Only set RS ctx enable in ctx control reg if there is a RS Date: Tue, 23 Feb 2016 14:48:39 +0000 Message-ID: <56CC7147.7050105@linux.intel.com> References: <1456235803-23886-1-git-send-email-michel.thierry@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id E979F6E5DC for ; Tue, 23 Feb 2016 14:48:43 +0000 (UTC) In-Reply-To: <1456235803-23886-1-git-send-email-michel.thierry@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Michel Thierry , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org T24gMjMvMDIvMjAxNiAxMzo1NiwgTWljaGVsIFRoaWVycnkgd3JvdGU6Cj4gVGhlIGRyaXZlciBz aG91bGQgb25seSBzZXQgdGhlICJSUyBjb250ZXh0IGVuYWJsZSIgYml0IGluIHRoZSBjb250ZXh0 Cj4gaW1hZ2UgaWYgd2UgcGxhbiB0byB1c2UgdGhlIHJlc291cmNlIHN0cmVhbWVyLgo+Cj4gU2ln bmVkLW9mZi1ieTogTWljaGVsIFRoaWVycnkgPG1pY2hlbC50aGllcnJ5QGludGVsLmNvbT4KPiAt LS0KPiAgIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2xyYy5jIHwgMyArKy0KPiAgIDEgZmls ZSBjaGFuZ2VkLCAyIGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKPgo+IGRpZmYgLS1naXQg YS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9scmMuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX2xyYy5jCj4gaW5kZXggZTEyZmNhYi4uYzM3NzliOSAxMDA2NDQKPiAtLS0gYS9kcml2 ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9scmMuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX2xyYy5jCj4gQEAgLTIzODIsNyArMjM4Miw4IEBAIHBvcHVsYXRlX2xyX2NvbnRleHQo c3RydWN0IGludGVsX2NvbnRleHQgKmN0eCwgc3RydWN0IGRybV9pOTE1X2dlbV9vYmplY3QgKmN0 eF9vCj4gICAJQVNTSUdOX0NUWF9SRUcocmVnX3N0YXRlLCBDVFhfQ09OVEVYVF9DT05UUk9MLCBS SU5HX0NPTlRFWFRfQ09OVFJPTChyaW5nKSwKPiAgIAkJICAgICAgIF9NQVNLRURfQklUX0VOQUJM RShDVFhfQ1RSTF9JTkhJQklUX1NZTl9DVFhfU1dJVENIIHwKPiAgIAkJCQkJICBDVFhfQ1RSTF9F TkdJTkVfQ1RYX1JFU1RPUkVfSU5ISUJJVCB8Cj4gLQkJCQkJICBDVFhfQ1RSTF9SU19DVFhfRU5B QkxFKSk7Cj4gKwkJCQkJICAoSEFTX1JFU09VUkNFX1NUUkVBTUVSKGRldikgPwo+ICsJCQkJCSAg ICBDVFhfQ1RSTF9SU19DVFhfRU5BQkxFIDogMCkpKTsKPiAgIAlBU1NJR05fQ1RYX1JFRyhyZWdf c3RhdGUsIENUWF9SSU5HX0hFQUQsIFJJTkdfSEVBRChyaW5nLT5tbWlvX2Jhc2UpLCAwKTsKPiAg IAlBU1NJR05fQ1RYX1JFRyhyZWdfc3RhdGUsIENUWF9SSU5HX1RBSUwsIFJJTkdfVEFJTChyaW5n LT5tbWlvX2Jhc2UpLCAwKTsKPiAgIAkvKiBSaW5nIGJ1ZmZlciBzdGFydCBhZGRyZXNzIGlzIG5v dCBrbm93biB1bnRpbCB0aGUgYnVmZmVyIGlzIHBpbm5lZC4KPgoKbG9va3MgZ29vZCB0byBtZSwK UmV2aWV3ZWQtYnk6IEFydW4gU2lsdXZlcnkgPGFydW4uc2lsdXZlcnlAbGludXguaW50ZWwuY29t PgoKcmVnYXJkcwpBcnVuCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0 b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50 ZWwtZ2Z4Cg==