* [PATCH 1/2] drm/i915: Split execlists hardware status page initialisation from setup @ 2016-04-12 14:40 Tvrtko Ursulin 2016-04-12 14:40 ` [PATCH 2/2] drm/i915: Use new i915_gem_object_pin_map for LRC Tvrtko Ursulin 2016-04-12 16:54 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Split execlists hardware status page initialisation from setup Patchwork 0 siblings, 2 replies; 5+ messages in thread From: Tvrtko Ursulin @ 2016-04-12 14:40 UTC (permalink / raw) To: Intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Split the hardware status page into setup and initialisation, where setup means setting up the driver state to support the engine, and initialization means programming the hardware with the before set up state. This way the design matches the design of the engine setup/init code which is split in the same fashion and it enables the stages to be used in a balanced fashion (engine setup - hws setup, engine init - hws init). This will enable the upcoming improvements to slot in without any kludges on the GPU reset path. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_lrc.c | 50 ++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index e6e69c2f2386..3fd2ae6ce8e7 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -229,9 +229,6 @@ enum { static int intel_lr_context_pin(struct intel_context *ctx, struct intel_engine_cs *engine); -static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine, - struct drm_i915_gem_object *default_ctx_obj); - /** * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists @@ -1580,14 +1577,22 @@ out: return ret; } +static void lrc_init_hws(struct intel_engine_cs *engine) +{ + struct drm_i915_private *dev_priv = engine->dev->dev_private; + + I915_WRITE(RING_HWS_PGA(engine->mmio_base), + (u32)engine->status_page.gfx_addr); + POSTING_READ(RING_HWS_PGA(engine->mmio_base)); +} + static int gen8_init_common_ring(struct intel_engine_cs *engine) { struct drm_device *dev = engine->dev; struct drm_i915_private *dev_priv = dev->dev_private; unsigned int next_context_status_buffer_hw; - lrc_setup_hardware_status_page(engine, - dev_priv->kernel_context->engine[engine->id].state); + lrc_init_hws(engine); I915_WRITE_IMR(engine, ~(engine->irq_enable_mask | engine->irq_keep_mask)); @@ -2087,6 +2092,20 @@ logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift) engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; } +static void +lrc_setup_hws(struct intel_engine_cs *engine, + struct drm_i915_gem_object *dctx_obj) +{ + struct page *page; + + /* The HWSP is part of the default context object in LRC mode. */ + engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) + + LRC_PPHWSP_PN * PAGE_SIZE; + page = i915_gem_object_get_page(dctx_obj, LRC_PPHWSP_PN); + engine->status_page.page_addr = kmap(page); + engine->status_page.obj = dctx_obj; +} + static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) { @@ -2145,6 +2164,9 @@ logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) goto error; } + /* And setup the hardware status page. */ + lrc_setup_hws(engine, dctx->engine[engine->id].state); + return 0; error: @@ -2605,24 +2627,6 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) return ret; } -static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine, - struct drm_i915_gem_object *default_ctx_obj) -{ - struct drm_i915_private *dev_priv = engine->dev->dev_private; - struct page *page; - - /* The HWSP is part of the default context object in LRC mode. */ - engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj) - + LRC_PPHWSP_PN * PAGE_SIZE; - page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN); - engine->status_page.page_addr = kmap(page); - engine->status_page.obj = default_ctx_obj; - - I915_WRITE(RING_HWS_PGA(engine->mmio_base), - (u32)engine->status_page.gfx_addr); - POSTING_READ(RING_HWS_PGA(engine->mmio_base)); -} - /** * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context * @ctx: LR context to create. -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/i915: Use new i915_gem_object_pin_map for LRC 2016-04-12 14:40 [PATCH 1/2] drm/i915: Split execlists hardware status page initialisation from setup Tvrtko Ursulin @ 2016-04-12 14:40 ` Tvrtko Ursulin 2016-04-12 15:09 ` Chris Wilson 2016-04-12 16:54 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Split execlists hardware status page initialisation from setup Patchwork 1 sibling, 1 reply; 5+ messages in thread From: Tvrtko Ursulin @ 2016-04-12 14:40 UTC (permalink / raw) To: Intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> We can use the new pin/lazy unpin API for simplicity and more performance in the execlist submission paths. v2: * Fix error handling and convert more users. * Compact some names for readability. v3: * intel_lr_context_free was not unpinning. * Special case for GPU reset which otherwise unbalances the HWS object pages pin count by running the engine initialization only (not destructors). v4: * Rebased on top of hws setup/init split. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 82 ++++++++++++++++++--------------- drivers/gpu/drm/i915/intel_lrc.h | 7 ++- 3 files changed, 52 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index fe580cb9501a..91028d9c6269 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -342,7 +342,7 @@ void i915_gem_context_reset(struct drm_device *dev) struct intel_context *ctx; list_for_each_entry(ctx, &dev_priv->context_list, link) - intel_lr_context_reset(dev, ctx); + intel_lr_context_reset(dev_priv, ctx); } for (i = 0; i < I915_NUM_ENGINES; i++) { diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3fd2ae6ce8e7..b61f8da5d6f3 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1091,8 +1091,8 @@ static int intel_lr_context_do_pin(struct intel_context *ctx, struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf; - struct page *lrc_state_page; - uint32_t *lrc_reg_state; + void *obj_addr; + u32 *lrc_reg_state; int ret; WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex)); @@ -1102,19 +1102,20 @@ static int intel_lr_context_do_pin(struct intel_context *ctx, if (ret) return ret; - lrc_state_page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); - if (WARN_ON(!lrc_state_page)) { - ret = -ENODEV; + obj_addr = i915_gem_object_pin_map(ctx_obj); + if (IS_ERR(obj_addr)) { + ret = PTR_ERR(obj_addr); goto unpin_ctx_obj; } + lrc_reg_state = obj_addr + LRC_STATE_PN * PAGE_SIZE; + ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf); if (ret) - goto unpin_ctx_obj; + goto unpin_map; ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj); intel_lr_context_descriptor_update(ctx, engine); - lrc_reg_state = kmap(lrc_state_page); lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start; ctx->engine[engine->id].lrc_reg_state = lrc_reg_state; ctx_obj->dirty = true; @@ -1125,6 +1126,8 @@ static int intel_lr_context_do_pin(struct intel_context *ctx, return ret; +unpin_map: + i915_gem_object_unpin_map(ctx_obj); unpin_ctx_obj: i915_gem_object_ggtt_unpin(ctx_obj); @@ -1157,7 +1160,7 @@ void intel_lr_context_unpin(struct intel_context *ctx, WARN_ON(!mutex_is_locked(&ctx->i915->dev->struct_mutex)); if (--ctx->engine[engine->id].pin_count == 0) { - kunmap(kmap_to_page(ctx->engine[engine->id].lrc_reg_state)); + i915_gem_object_unpin_map(ctx_obj); intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf); i915_gem_object_ggtt_unpin(ctx_obj); ctx->engine[engine->id].lrc_vma = NULL; @@ -2054,7 +2057,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine) i915_gem_batch_pool_fini(&engine->batch_pool); if (engine->status_page.obj) { - kunmap(sg_page(engine->status_page.obj->pages->sgl)); + i915_gem_object_unpin_map(engine->status_page.obj); engine->status_page.obj = NULL; } @@ -2092,18 +2095,22 @@ logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift) engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; } -static void +static int lrc_setup_hws(struct intel_engine_cs *engine, struct drm_i915_gem_object *dctx_obj) { - struct page *page; + void *hws; /* The HWSP is part of the default context object in LRC mode. */ engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) + LRC_PPHWSP_PN * PAGE_SIZE; - page = i915_gem_object_get_page(dctx_obj, LRC_PPHWSP_PN); - engine->status_page.page_addr = kmap(page); + hws = i915_gem_object_pin_map(dctx_obj); + if (IS_ERR(hws)) + return PTR_ERR(hws); + engine->status_page.page_addr = hws + LRC_PPHWSP_PN * PAGE_SIZE; engine->status_page.obj = dctx_obj; + + return 0; } static int @@ -2165,7 +2172,11 @@ logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) } /* And setup the hardware status page. */ - lrc_setup_hws(engine, dctx->engine[engine->id].state); + ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); + if (ret) { + DRM_ERROR("Failed to set up hwd %s: %d\n", engine->name, ret); + goto error; + } return 0; @@ -2417,15 +2428,16 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) } static int -populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, +populate_lr_context(struct intel_context *ctx, + struct drm_i915_gem_object *ctx_obj, struct intel_engine_cs *engine, struct intel_ringbuffer *ringbuf) { struct drm_device *dev = engine->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; - struct page *page; - uint32_t *reg_state; + void *obj_addr; + u32 *reg_state; int ret; if (!ppgtt) @@ -2437,18 +2449,17 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o return ret; } - ret = i915_gem_object_get_pages(ctx_obj); - if (ret) { - DRM_DEBUG_DRIVER("Could not get object pages\n"); + obj_addr = i915_gem_object_pin_map(ctx_obj); + if (IS_ERR(obj_addr)) { + ret = PTR_ERR(obj_addr); + DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); return ret; } - - i915_gem_object_pin_pages(ctx_obj); + ctx_obj->dirty = true; /* The second page of the context object contains some fields which must * be set up prior to the first execution. */ - page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); - reg_state = kmap_atomic(page); + reg_state = obj_addr + LRC_STATE_PN * PAGE_SIZE; /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM * commands followed by (reg, value) pairs. The values we are setting here are @@ -2553,8 +2564,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o make_rpcs(dev)); } - kunmap_atomic(reg_state); - i915_gem_object_unpin_pages(ctx_obj); + i915_gem_object_unpin_map(ctx_obj); return 0; } @@ -2581,6 +2591,7 @@ void intel_lr_context_free(struct intel_context *ctx) if (ctx == ctx->i915->kernel_context) { intel_unpin_ringbuffer_obj(ringbuf); i915_gem_object_ggtt_unpin(ctx_obj); + i915_gem_object_unpin_map(ctx_obj); } WARN_ON(ctx->engine[i].pin_count); @@ -2709,10 +2720,9 @@ error_deref_obj: return ret; } -void intel_lr_context_reset(struct drm_device *dev, - struct intel_context *ctx) +void intel_lr_context_reset(struct drm_i915_private *dev_priv, + struct intel_context *ctx) { - struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *engine; for_each_engine(engine, dev_priv) { @@ -2720,23 +2730,23 @@ void intel_lr_context_reset(struct drm_device *dev, ctx->engine[engine->id].state; struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf; + void *obj_addr; uint32_t *reg_state; - struct page *page; if (!ctx_obj) continue; - if (i915_gem_object_get_pages(ctx_obj)) { - WARN(1, "Failed get_pages for context obj\n"); + obj_addr = i915_gem_object_pin_map(ctx_obj); + if (WARN_ON(IS_ERR(obj_addr))) continue; - } - page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); - reg_state = kmap_atomic(page); + + reg_state = obj_addr + LRC_STATE_PN * PAGE_SIZE; + ctx_obj->dirty = true; reg_state[CTX_RING_HEAD+1] = 0; reg_state[CTX_RING_TAIL+1] = 0; - kunmap_atomic(reg_state); + i915_gem_object_unpin_map(ctx_obj); ringbuf->head = 0; ringbuf->tail = 0; diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 8de1ea536ad4..9affda2c650c 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -104,8 +104,11 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx, struct intel_engine_cs *engine); void intel_lr_context_unpin(struct intel_context *ctx, struct intel_engine_cs *engine); -void intel_lr_context_reset(struct drm_device *dev, - struct intel_context *ctx); + +struct drm_i915_private; + +void intel_lr_context_reset(struct drm_i915_private *dev_priv, + struct intel_context *ctx); uint64_t intel_lr_context_descriptor(struct intel_context *ctx, struct intel_engine_cs *engine); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/i915: Use new i915_gem_object_pin_map for LRC 2016-04-12 14:40 ` [PATCH 2/2] drm/i915: Use new i915_gem_object_pin_map for LRC Tvrtko Ursulin @ 2016-04-12 15:09 ` Chris Wilson 0 siblings, 0 replies; 5+ messages in thread From: Chris Wilson @ 2016-04-12 15:09 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: Intel-gfx On Tue, Apr 12, 2016 at 03:40:42PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > We can use the new pin/lazy unpin API for simplicity > and more performance in the execlist submission paths. > > v2: > * Fix error handling and convert more users. > * Compact some names for readability. > > v3: > * intel_lr_context_free was not unpinning. > * Special case for GPU reset which otherwise unbalances > the HWS object pages pin count by running the engine > initialization only (not destructors). > > v4: > * Rebased on top of hws setup/init split. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> Minor comments, both Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 3fd2ae6ce8e7..b61f8da5d6f3 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1091,8 +1091,8 @@ static int intel_lr_context_do_pin(struct intel_context *ctx, > struct drm_i915_private *dev_priv = dev->dev_private; > struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; > struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf; > - struct page *lrc_state_page; > - uint32_t *lrc_reg_state; > + void *obj_addr; obj_addr, harking back to a time when it was an unsigned long? Even then it would be more traditionally be vaddr. map, base, vaddr, obj_* > /* And setup the hardware status page. */ > - lrc_setup_hws(engine, dctx->engine[engine->id].state); > + ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); > + if (ret) { > + DRM_ERROR("Failed to set up hwd %s: %d\n", engine->name, ret); s/hwd/hws/ I would have put this set of chunks in the previous patch for less churn. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Split execlists hardware status page initialisation from setup 2016-04-12 14:40 [PATCH 1/2] drm/i915: Split execlists hardware status page initialisation from setup Tvrtko Ursulin 2016-04-12 14:40 ` [PATCH 2/2] drm/i915: Use new i915_gem_object_pin_map for LRC Tvrtko Ursulin @ 2016-04-12 16:54 ` Patchwork 2016-04-13 9:50 ` Tvrtko Ursulin 1 sibling, 1 reply; 5+ messages in thread From: Patchwork @ 2016-04-12 16:54 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: Split execlists hardware status page initialisation from setup URL : https://patchwork.freedesktop.org/series/5596/ State : failure == Summary == Series 5596v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/5596/revisions/1/mbox/ Test drv_module_reload_basic: pass -> FAIL (snb-dellxps) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> FAIL (ivb-t430s) bdw-nuci7 total:203 pass:191 dwarn:0 dfail:0 fail:0 skip:12 bdw-ultra total:203 pass:180 dwarn:0 dfail:0 fail:0 skip:23 bsw-nuc-2 total:202 pass:163 dwarn:0 dfail:0 fail:0 skip:39 byt-nuc total:202 pass:164 dwarn:0 dfail:0 fail:0 skip:38 hsw-brixbox total:203 pass:179 dwarn:0 dfail:0 fail:0 skip:24 hsw-gt2 total:203 pass:184 dwarn:0 dfail:0 fail:0 skip:19 ivb-t430s total:203 pass:174 dwarn:0 dfail:0 fail:1 skip:28 skl-i7k-2 total:203 pass:178 dwarn:0 dfail:0 fail:0 skip:25 skl-nuci5 total:203 pass:192 dwarn:0 dfail:0 fail:0 skip:11 snb-dellxps total:203 pass:164 dwarn:0 dfail:0 fail:1 skip:38 snb-x220t total:203 pass:165 dwarn:0 dfail:0 fail:1 skip:37 Results at /archive/results/CI_IGT_test/Patchwork_1875/ 42189a46296988a9e16b57dca9e25c227458888b drm-intel-nightly: 2016y-04m-12d-14h-35m-43s UTC integration manifest 6d8f2e9 drm/i915: Use new i915_gem_object_pin_map for LRC f1b4a09 drm/i915: Split execlists hardware status page initialisation from setup _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Split execlists hardware status page initialisation from setup 2016-04-12 16:54 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Split execlists hardware status page initialisation from setup Patchwork @ 2016-04-13 9:50 ` Tvrtko Ursulin 0 siblings, 0 replies; 5+ messages in thread From: Tvrtko Ursulin @ 2016-04-13 9:50 UTC (permalink / raw) To: intel-gfx On 12/04/16 17:54, Patchwork wrote: > == Series Details == > > Series: series starting with [1/2] drm/i915: Split execlists hardware status page initialisation from setup > URL : https://patchwork.freedesktop.org/series/5596/ > State : failure > > == Summary == > > Series 5596v1 Series without cover letter > http://patchwork.freedesktop.org/api/1.0/series/5596/revisions/1/mbox/ > > Test drv_module_reload_basic: > pass -> FAIL (snb-dellxps) This hasn't been filed so far and it failed once already in CI_DRM_1194. Failure are assertions in gem_exec_store after driver reload. Filed a new BZ: https://bugs.freedesktop.org/show_bug.cgi?id=94914 > Test kms_flip: > Subgroup basic-flip-vs-wf_vblank: > pass -> FAIL (ivb-t430s) Old friend https://bugs.freedesktop.org/show_bug.cgi?id=94294 > > bdw-nuci7 total:203 pass:191 dwarn:0 dfail:0 fail:0 skip:12 > bdw-ultra total:203 pass:180 dwarn:0 dfail:0 fail:0 skip:23 > bsw-nuc-2 total:202 pass:163 dwarn:0 dfail:0 fail:0 skip:39 > byt-nuc total:202 pass:164 dwarn:0 dfail:0 fail:0 skip:38 > hsw-brixbox total:203 pass:179 dwarn:0 dfail:0 fail:0 skip:24 > hsw-gt2 total:203 pass:184 dwarn:0 dfail:0 fail:0 skip:19 > ivb-t430s total:203 pass:174 dwarn:0 dfail:0 fail:1 skip:28 > skl-i7k-2 total:203 pass:178 dwarn:0 dfail:0 fail:0 skip:25 > skl-nuci5 total:203 pass:192 dwarn:0 dfail:0 fail:0 skip:11 > snb-dellxps total:203 pass:164 dwarn:0 dfail:0 fail:1 skip:38 > snb-x220t total:203 pass:165 dwarn:0 dfail:0 fail:1 skip:37 > > Results at /archive/results/CI_IGT_test/Patchwork_1875/ > > 42189a46296988a9e16b57dca9e25c227458888b drm-intel-nightly: 2016y-04m-12d-14h-35m-43s UTC integration manifest > 6d8f2e9 drm/i915: Use new i915_gem_object_pin_map for LRC > f1b4a09 drm/i915: Split execlists hardware status page initialisation from setup Merged - thanks for the review. Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-04-13 9:50 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-04-12 14:40 [PATCH 1/2] drm/i915: Split execlists hardware status page initialisation from setup Tvrtko Ursulin 2016-04-12 14:40 ` [PATCH 2/2] drm/i915: Use new i915_gem_object_pin_map for LRC Tvrtko Ursulin 2016-04-12 15:09 ` Chris Wilson 2016-04-12 16:54 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Split execlists hardware status page initialisation from setup Patchwork 2016-04-13 9:50 ` Tvrtko Ursulin
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