[PATCH 2/5] drm/i915: Read test values for lane_count and link_rate

[PATCH 2/5] drm/i915: Read test values for lane_count and link_rate

[Shubhangi Shrivastava]

During automated test request for link training we are supposed to
read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use
respective values in the next link training. This patch adds
reading and updating of these values.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2a14603..0402a4b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4045,9 +4045,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
 	return true;
 }
 
+/*
+ * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates
+ * them to cached dpcd values, thus the new values are implicitly
+ * used by rest of the code without need to be aware of the change.
+ */
 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
 	uint8_t test_result = DP_TEST_ACK;
+	uint8_t dpcd_val, ret;
+
+	ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
+				      DP_TEST_LANE_COUNT,
+				      &dpcd_val, 1);
+
+	/* update values only if read returned 1 byte */
+	if (ret == 1) {
+		dpcd_val &= DP_MAX_LANE_COUNT_MASK;
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK);
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val;
+	}
+
+	ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
+				      DP_TEST_LINK_RATE,
+				      &dpcd_val, 1);
+
+	if (ret == 1)
+		intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val;
+
 	return test_result;
 }
 
-- 
2.6.1

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[PATCH 1/5] drm/i915: Handle automated test requests for short pulse hpd

[Shubhangi Shrivastava]

This patch adds support for automated test requests during
short pulse handling in gen platforms.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7df17d12..1b26c59 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4074,7 +4074,8 @@ static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 	return test_result;
 }
 
-static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
+static void intel_dp_handle_test_request(struct intel_dp *intel_dp,
+					 bool short_pulse)
 {
 	uint8_t response = DP_TEST_NAK;
 	uint8_t rxdata = 0;
@@ -4086,6 +4087,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
 		goto update_status;
 	}
 
+	if (short_pulse && rxdata != DP_TEST_LINK_TRAINING) {
+		DRM_ERROR("Invalid test request in short pulse\n");
+		goto update_status;
+	}
+
 	switch (rxdata) {
 	case DP_TEST_LINK_TRAINING:
 		DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
@@ -4258,7 +4264,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 				   sink_irq_vector);
 
 		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
-			DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
+			intel_dp_handle_test_request(intel_dp, true);
 		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
 			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
 	}
@@ -4612,7 +4618,7 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
 				   sink_irq_vector);
 
 		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
-			intel_dp_handle_test_request(intel_dp);
+			intel_dp_handle_test_request(intel_dp, false);
 		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
 			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
 	}
-- 
2.6.1

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[PATCH 2/5] drm/i915: Read test values for lane_count and link_rate

[Shubhangi Shrivastava]

During automated test request for link training we are supposed to
read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use
respective values in the next link training. This patch adds
reading and updating of these values.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1b26c59..387800b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4010,9 +4010,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
 	return true;
 }
 
+/*
+ * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates
+ * them to cached dpcd values, thus the new values are implicitly
+ * used by rest of the code without need to be aware of the change.
+ */
 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
 	uint8_t test_result = DP_TEST_ACK;
+	uint8_t dpcd_val, ret;
+
+	ret = drm_dp_dpcd_read(&intel_dp->aux,
+			       DP_TEST_LANE_COUNT,
+			       &dpcd_val, 1);
+
+	/* update values only if read returned 1 byte */
+	if (ret == 1) {
+		dpcd_val &= DP_MAX_LANE_COUNT_MASK;
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK);
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val;
+	}
+
+	ret = drm_dp_dpcd_read(&intel_dp->aux,
+			       DP_TEST_LINK_RATE,
+			       &dpcd_val, 1);
+
+	if (ret == 1)
+		intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val;
+
 	return test_result;
 }
 
-- 
2.6.1

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[PATCH 3/5] drm/i915: Cleanup panel IRQ handling

[Shubhangi Shrivastava]

IRQ bits are set by panel in DPCD 0x201 to perform various requests.
Current code clears all bits in one go and then handles them, but
this is not proper since some scenarios require full detection and
if we clear such bits the test request may not be detected in the
later part.

It is always good to clear the bits only when handled, so this patch
moves the IRQ clearing bit post handling code.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 387800b..de9ea18 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4144,9 +4144,14 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp,
 	}
 
 update_status:
+	/* Clear interrupt first */
+	drm_dp_dpcd_writeb(&intel_dp->aux,
+			   DP_DEVICE_SERVICE_IRQ_VECTOR,
+			   DP_AUTOMATED_TEST_REQUEST);
 	status = drm_dp_dpcd_write(&intel_dp->aux,
 				   DP_TEST_RESPONSE,
 				   &response, 1);
+
 	if (status <= 0)
 		DRM_DEBUG_KMS("Could not write test response to sink\n");
 }
@@ -4283,15 +4288,22 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 	/* Try to read the source of the interrupt */
 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
-		/* Clear interrupt source */
-		drm_dp_dpcd_writeb(&intel_dp->aux,
-				   DP_DEVICE_SERVICE_IRQ_VECTOR,
-				   sink_irq_vector);
-
-		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
+		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) {
 			intel_dp_handle_test_request(intel_dp, true);
+			sink_irq_vector &= ~DP_AUTOMATED_TEST_REQUEST;
+		}
+
 		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
 			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
+
+		/* Clear interrupt source */
+		if (sink_irq_vector) {
+			DRM_DEBUG_KMS("ATR requests not handled for %x\n",
+				      sink_irq_vector);
+			drm_dp_dpcd_writeb(&intel_dp->aux,
+					   DP_DEVICE_SERVICE_IRQ_VECTOR,
+					   sink_irq_vector);
+		}
 	}
 
 	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
-- 
2.6.1

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[PATCH 4/5] drm/i915: Extract test reply to separate function

[Shubhangi Shrivastava]

Replying for automated test request must be done only when we
are ready for the request. This patch extracts this reply to
separate function as it is needed in other places in the
upcoming patches.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 18 ++++++++++--------
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index de9ea18..77882ac 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4099,6 +4099,15 @@ static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 	return test_result;
 }
 
+int intel_dp_write_test_reply(struct intel_dp *intel_dp, uint8_t reply)
+{
+	/* Clear interrupt first */
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
+			   DP_AUTOMATED_TEST_REQUEST);
+
+	return drm_dp_dpcd_write(&intel_dp->aux, DP_TEST_RESPONSE, &reply, 1);
+}
+
 static void intel_dp_handle_test_request(struct intel_dp *intel_dp,
 					 bool short_pulse)
 {
@@ -4144,14 +4153,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp,
 	}
 
 update_status:
-	/* Clear interrupt first */
-	drm_dp_dpcd_writeb(&intel_dp->aux,
-			   DP_DEVICE_SERVICE_IRQ_VECTOR,
-			   DP_AUTOMATED_TEST_REQUEST);
-	status = drm_dp_dpcd_write(&intel_dp->aux,
-				   DP_TEST_RESPONSE,
-				   &response, 1);
-
+	status = intel_dp_write_test_reply(intel_dp, response);
 	if (status <= 0)
 		DRM_DEBUG_KMS("Could not write test response to sink\n");
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b9f1304..7da13b5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1335,6 +1335,7 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
 bool
 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
+int intel_dp_write_test_reply(struct intel_dp *intel_dp, uint8_t reply);
 
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
-- 
2.6.1

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[PATCH 5/5] drm/i915: Delay acknowledging of link training for ATR

[Shubhangi Shrivastava]

Automated test request will wait for ack or nak before proceeding.
Acknowledging them ahead of time is not always good especially for
link training related requests. Scenarios where we need to do
full detection it is likely that the new detect might not read the
automated request since we have alreay ack'ed the request. So
send the ack response only when performing link training with the
given parameters.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c               | 10 ++++++----
 drivers/gpu/drm/i915/intel_dp_link_training.c |  3 +++
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 77882ac..7a0da43 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4130,7 +4130,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp,
 	case DP_TEST_LINK_TRAINING:
 		DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
 		intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
-		response = intel_dp_autotest_link_training(intel_dp);
+		intel_dp_autotest_link_training(intel_dp);
 		break;
 	case DP_TEST_LINK_VIDEO_PATTERN:
 		DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
@@ -4153,9 +4153,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp,
 	}
 
 update_status:
-	status = intel_dp_write_test_reply(intel_dp, response);
-	if (status <= 0)
-		DRM_DEBUG_KMS("Could not write test response to sink\n");
+	if (intel_dp->compliance_test_type != DP_TEST_LINK_TRAINING) {
+		status = intel_dp_write_test_reply(intel_dp, response);
+		if (status <= 0)
+			DRM_DEBUG_KMS("Could not write test response to sink\n");
+	}
 }
 
 static int
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 0b8eefc..54df07a 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -120,6 +120,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
 			      &link_bw, &rate_select);
 
+	if (intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING)
+		intel_dp_write_test_reply(intel_dp, DP_TEST_ACK);
+
 	/* Write the link configuration data */
 	link_config[0] = link_bw;
 	link_config[1] = intel_dp->lane_count;
-- 
2.6.1

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✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Handle automated test requests for short pulse hpd

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Handle automated test requests for short pulse hpd
URL   : https://patchwork.freedesktop.org/series/6240/
State : success

== Summary ==

Series 6240v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/6240/revisions/1/mbox/

Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                fail       -> PASS       (snb-x220t)
Test kms_force_connector_basic:
        Subgroup force-edid:
                skip       -> PASS       (ivb-t430s)

bdw-nuci7        total:193  pass:181  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:193  pass:170  dwarn:0   dfail:0   fail:0   skip:23 
bsw-nuc-2        total:192  pass:153  dwarn:0   dfail:0   fail:0   skip:39 
byt-nuc          total:192  pass:154  dwarn:0   dfail:0   fail:0   skip:38 
hsw-brixbox      total:193  pass:169  dwarn:0   dfail:0   fail:0   skip:24 
hsw-gt2          total:193  pass:174  dwarn:0   dfail:0   fail:0   skip:19 
ilk-hp8440p      total:193  pass:136  dwarn:0   dfail:0   fail:0   skip:57 
ivb-t430s        total:193  pass:165  dwarn:0   dfail:0   fail:0   skip:28 
skl-i7k-2        total:193  pass:168  dwarn:0   dfail:0   fail:0   skip:25 
skl-nuci5        total:193  pass:182  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:193  pass:155  dwarn:0   dfail:0   fail:0   skip:38 
snb-x220t        total:193  pass:155  dwarn:0   dfail:0   fail:1   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2058/

63b103430bfb3b1ef64623f2d70d46c29b931d15 drm-intel-nightly: 2016y-04m-25d-09h-07m-20s UTC integration manifest
269a9e2 drm/i915: Delay acknowledging of link training for ATR
c660e7b drm/i915: Extract test reply to separate function
53496af drm/i915: Cleanup panel IRQ handling
96aa906 drm/i915: Read test values for lane_count and link_rate
75bacb3 drm/i915: Handle automated test requests for short pulse hpd

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Re: [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate

[Navare, Manasi D]

The automated test request for link training needs to start the link training with the requested link rate and lane count. So after reading the TEST LANE COUNT and TEST LINK RATE values, it needs to call intel_dp_start_link_train() also.
How is the automated link train being tested currently? Could you add some details of the automated testing (test numbers from the CTS usite) in the commit message.

Regards,
Manasi Navare
Graphics Kernel Developer
OTC, Intel Corporation


-----Original Message-----
From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Shubhangi Shrivastava
Sent: Monday, April 25, 2016 1:24 AM
To: intel-gfx@lists.freedesktop.org
Cc: Shrivastava, Shubhangi
Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate

During automated test request for link training we are supposed to read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use respective values in the next link training. This patch adds reading and updating of these values.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1b26c59..387800b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4010,9 +4010,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
 	return true;
 }
 
+/*
+ * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates
+ * them to cached dpcd values, thus the new values are implicitly
+ * used by rest of the code without need to be aware of the change.
+ */
 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)  {
 	uint8_t test_result = DP_TEST_ACK;
+	uint8_t dpcd_val, ret;
+
+	ret = drm_dp_dpcd_read(&intel_dp->aux,
+			       DP_TEST_LANE_COUNT,
+			       &dpcd_val, 1);
+
+	/* update values only if read returned 1 byte */
+	if (ret == 1) {
+		dpcd_val &= DP_MAX_LANE_COUNT_MASK;
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK);
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val;
+	}
+
+	ret = drm_dp_dpcd_read(&intel_dp->aux,
+			       DP_TEST_LINK_RATE,
+			       &dpcd_val, 1);
+
+	if (ret == 1)
+		intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val;
+
 	return test_result;
 }
 
--
2.6.1

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Re: [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate

[Shubhangi Shrivastava]

This patch is intended to read test values only. Call to 
intel_dp_start_link_train will be in upcoming patch "Lane count change 
detection", which I will be posting after this patch series..

On Tuesday 26 April 2016 09:39 AM, Navare, Manasi D wrote:
> The automated test request for link training needs to start the link training with the requested link rate and lane count. So after reading the TEST LANE COUNT and TEST LINK RATE values, it needs to call intel_dp_start_link_train() also.
> How is the automated link train being tested currently? Could you add some details of the automated testing (test numbers from the CTS usite) in the commit message.
>
> Regards,
> Manasi Navare
> Graphics Kernel Developer
> OTC, Intel Corporation
>
>
> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Shubhangi Shrivastava
> Sent: Monday, April 25, 2016 1:24 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shrivastava, Shubhangi
> Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate
>
> During automated test request for link training we are supposed to read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use respective values in the next link training. This patch adds reading and updating of these values.
>
> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1b26c59..387800b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4010,9 +4010,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
>   	return true;
>   }
>   
> +/*
> + * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates
> + * them to cached dpcd values, thus the new values are implicitly
> + * used by rest of the code without need to be aware of the change.
> + */
>   static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)  {
>   	uint8_t test_result = DP_TEST_ACK;
> +	uint8_t dpcd_val, ret;
> +
> +	ret = drm_dp_dpcd_read(&intel_dp->aux,
> +			       DP_TEST_LANE_COUNT,
> +			       &dpcd_val, 1);
> +
> +	/* update values only if read returned 1 byte */
> +	if (ret == 1) {
> +		dpcd_val &= DP_MAX_LANE_COUNT_MASK;
> +		intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK);
> +		intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val;
> +	}
> +
> +	ret = drm_dp_dpcd_read(&intel_dp->aux,
> +			       DP_TEST_LINK_RATE,
> +			       &dpcd_val, 1);
> +
> +	if (ret == 1)
> +		intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val;
> +
>   	return test_result;
>   }
>   
> --
> 2.6.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate

[Thulasimani, Sivakumar]

On 5/2/2016 2:38 PM, Shubhangi Shrivastava wrote:
> This patch is intended to read test values only. Call to 
> intel_dp_start_link_train will be in upcoming patch "Lane count change 
> detection", which I will be posting after this patch series..
>
> On Tuesday 26 April 2016 09:39 AM, Navare, Manasi D wrote:
>> The automated test request for link training needs to start the link 
>> training with the requested link rate and lane count. So after 
>> reading the TEST LANE COUNT and TEST LINK RATE values, it needs to 
>> call intel_dp_start_link_train() also.
>> How is the automated link train being tested currently? Could you add 
>> some details of the automated testing (test numbers from the CTS 
>> usite) in the commit message.
>>
>> Regards,
>> Manasi Navare
>> Graphics Kernel Developer
>> OTC, Intel Corporation
>>
>>
Almost all link training tests in CTS use the TEST LANE COUNT and TEST 
LINK RATE values.
i.e 4.3.1.1 to 4.3.1.10 and 4.3.2.1 to 4.3.2.6.
This was tested using DPR100 & DPR120 compliance test tool from Unigraf.
As mentioned by Shubhangi this is just a clean up patch and further 
patches will complete
the process of using the test values in next link training.

To give some background, if you run either of the tools mentioned above, 
they give us a
short/long pulse with TEST_LINK_TRAIN request bit set, we are supposed 
to then read the
link rate and lane count values from appropriate Test DPCD registers and 
use them
in the following link training.  So as per compliance requirements you 
need to use
these values in the next link training (which is assumed to be as part 
of modeset
if we got it as part of long pulse and for short pulse we can explicitly 
retrain the link)

regards,
Sivakumar
>> -----Original Message-----
>> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On 
>> Behalf Of Shubhangi Shrivastava
>> Sent: Monday, April 25, 2016 1:24 AM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Shrivastava, Shubhangi
>> Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for 
>> lane_count and link_rate
>>
>> During automated test request for link training we are supposed to 
>> read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use 
>> respective values in the next link training. This patch adds reading 
>> and updating of these values.
>>
>> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>> Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++
>>   1 file changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
>> b/drivers/gpu/drm/i915/intel_dp.c index 1b26c59..387800b 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4010,9 +4010,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp 
>> *intel_dp, u8 *sink_irq_vector)
>>       return true;
>>   }
>>   +/*
>> + * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates
>> + * them to cached dpcd values, thus the new values are implicitly
>> + * used by rest of the code without need to be aware of the change.
>> + */
>>   static uint8_t intel_dp_autotest_link_training(struct intel_dp 
>> *intel_dp)  {
>>       uint8_t test_result = DP_TEST_ACK;
>> +    uint8_t dpcd_val, ret;
>> +
>> +    ret = drm_dp_dpcd_read(&intel_dp->aux,
>> +                   DP_TEST_LANE_COUNT,
>> +                   &dpcd_val, 1);
>> +
>> +    /* update values only if read returned 1 byte */
>> +    if (ret == 1) {
>> +        dpcd_val &= DP_MAX_LANE_COUNT_MASK;
>> +        intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK);
>> +        intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val;
>> +    }
>> +
>> +    ret = drm_dp_dpcd_read(&intel_dp->aux,
>> +                   DP_TEST_LINK_RATE,
>> +                   &dpcd_val, 1);
>> +
>> +    if (ret == 1)
>> +        intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val;
>> +
>>       return test_result;
>>   }
>>   --
>> 2.6.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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