[PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Peter Antoine]

This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.

Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_reg.h     | 5 +++--
 drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 80786d9..6e01238 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -68,10 +68,11 @@
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
-#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
+#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
+#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
 
 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
+#define	GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
 
 #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
 #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index fc3ff68..38fb321 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -312,7 +312,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+	if (IS_BROXTON(dev))
+		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
+	else
+		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 
 	/* Enable MIA caching. GuC clock gating is disabled. */
-- 
1.9.1

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✗ Fi.CI.BAT: failure for drm/i915: resize the GuC WOPCM for rc6

[Patchwork]

== Series Details ==

Series: drm/i915: resize the GuC WOPCM for rc6
URL   : https://patchwork.freedesktop.org/series/6313/
State : failure

== Summary ==

Series 6313v1 drm/i915: resize the GuC WOPCM for rc6
http://patchwork.freedesktop.org/api/1.0/series/6313/revisions/1/mbox/

Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> FAIL       (hsw-gt2)
Test kms_force_connector_basic:
        Subgroup force-edid:
                pass       -> SKIP       (ivb-t430s)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-b-frame-sequence:
                skip       -> PASS       (bdw-nuci7)

bdw-nuci7        total:200  pass:188  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:200  pass:175  dwarn:0   dfail:0   fail:0   skip:25 
bsw-nuc-2        total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41 
byt-nuc          total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41 
hsw-brixbox      total:200  pass:174  dwarn:0   dfail:0   fail:0   skip:26 
hsw-gt2          total:200  pass:178  dwarn:0   dfail:0   fail:1   skip:21 
ilk-hp8440p      total:200  pass:139  dwarn:0   dfail:0   fail:0   skip:61 
ivb-t430s        total:200  pass:168  dwarn:0   dfail:0   fail:0   skip:32 
skl-i7k-2        total:200  pass:173  dwarn:0   dfail:0   fail:0   skip:27 
skl-nuci5        total:200  pass:189  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:200  pass:158  dwarn:0   dfail:0   fail:0   skip:42 
snb-x220t        total:200  pass:158  dwarn:0   dfail:0   fail:1   skip:41 

Results at /archive/results/CI_IGT_test/Patchwork_2068/

f814551aa7232ed36d71244dd148b48660b53a78 drm-intel-nightly: 2016y-04m-25d-11h-36m-27s UTC integration manifest
c8a3953 drm/i915: resize the GuC WOPCM for rc6

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Re: ✗ Fi.CI.BAT: failure for drm/i915: resize the GuC WOPCM for rc6

[Peter Antoine]

On Tue, 26 Apr 2016, Patchwork wrote:

> == Series Details ==
>
> Series: drm/i915: resize the GuC WOPCM for rc6
> URL   : https://patchwork.freedesktop.org/series/6313/
> State : failure
>
> == Summary ==
>
> Series 6313v1 drm/i915: resize the GuC WOPCM for rc6
> http://patchwork.freedesktop.org/api/1.0/series/6313/revisions/1/mbox/
>
> Test kms_flip:
>        Subgroup basic-flip-vs-wf_vblank:
>                pass       -> FAIL       (hsw-gt2)
Patch cannot effect HSW as platform does not have GuC and GuC code is all 
guarded by platform. False Failure.

> Test kms_force_connector_basic:
>        Subgroup force-edid:
>                pass       -> SKIP       (ivb-t430s)
Nothing to do with display.

> Test kms_pipe_crc_basic:
>        Subgroup read-crc-pipe-b-frame-sequence:
>                skip       -> PASS       (bdw-nuci7)
Same.

>
> bdw-nuci7        total:200  pass:188  dwarn:0   dfail:0   fail:0   skip:12
> bdw-ultra        total:200  pass:175  dwarn:0   dfail:0   fail:0   skip:25
> bsw-nuc-2        total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> byt-nuc          total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> hsw-brixbox      total:200  pass:174  dwarn:0   dfail:0   fail:0   skip:26
> hsw-gt2          total:200  pass:178  dwarn:0   dfail:0   fail:1   skip:21
> ilk-hp8440p      total:200  pass:139  dwarn:0   dfail:0   fail:0   skip:61
> ivb-t430s        total:200  pass:168  dwarn:0   dfail:0   fail:0   skip:32
> skl-i7k-2        total:200  pass:173  dwarn:0   dfail:0   fail:0   skip:27
> skl-nuci5        total:200  pass:189  dwarn:0   dfail:0   fail:0   skip:11
> snb-dellxps      total:200  pass:158  dwarn:0   dfail:0   fail:0   skip:42
> snb-x220t        total:200  pass:158  dwarn:0   dfail:0   fail:1   skip:41
>
> Results at /archive/results/CI_IGT_test/Patchwork_2068/
>
> f814551aa7232ed36d71244dd148b48660b53a78 drm-intel-nightly: 2016y-04m-25d-11h-36m-27s UTC integration manifest
> c8a3953 drm/i915: resize the GuC WOPCM for rc6
>
>

--
    Peter Antoine (Android Graphics Driver Software Engineer)
    ---------------------------------------------------------------------
    Intel Corporation (UK) Limited
    Registered No. 1134945 (England)
    Registered Office: Pipers Way, Swindon SN3 1RJ
    VAT No: 860 2173 47
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Re: ✗ Fi.CI.BAT: failure for drm/i915: resize the GuC WOPCM for rc6

[Daniel Vetter]

On Tue, Apr 26, 2016 at 11:38:46AM +0100, Peter Antoine wrote:
> On Tue, 26 Apr 2016, Patchwork wrote:
> 
> >== Series Details ==
> >
> >Series: drm/i915: resize the GuC WOPCM for rc6
> >URL   : https://patchwork.freedesktop.org/series/6313/
> >State : failure
> >
> >== Summary ==
> >
> >Series 6313v1 drm/i915: resize the GuC WOPCM for rc6
> >http://patchwork.freedesktop.org/api/1.0/series/6313/revisions/1/mbox/
> >
> >Test kms_flip:
> >       Subgroup basic-flip-vs-wf_vblank:
> >               pass       -> FAIL       (hsw-gt2)
> Patch cannot effect HSW as platform does not have GuC and GuC code is all
> guarded by platform. False Failure.
> 
> >Test kms_force_connector_basic:
> >       Subgroup force-edid:
> >               pass       -> SKIP       (ivb-t430s)
> Nothing to do with display.
> 
> >Test kms_pipe_crc_basic:
> >       Subgroup read-crc-pipe-b-frame-sequence:
> >               skip       -> PASS       (bdw-nuci7)
> Same.

The idea is to digg through bugzilla to make sure we have bugs for all of
these, not just shrug them off.

Yes this is work, and yes it's meant to motivate people to fix up all the
fail we still have.
-Daniel

> 
> >
> >bdw-nuci7        total:200  pass:188  dwarn:0   dfail:0   fail:0   skip:12
> >bdw-ultra        total:200  pass:175  dwarn:0   dfail:0   fail:0   skip:25
> >bsw-nuc-2        total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> >byt-nuc          total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> >hsw-brixbox      total:200  pass:174  dwarn:0   dfail:0   fail:0   skip:26
> >hsw-gt2          total:200  pass:178  dwarn:0   dfail:0   fail:1   skip:21
> >ilk-hp8440p      total:200  pass:139  dwarn:0   dfail:0   fail:0   skip:61
> >ivb-t430s        total:200  pass:168  dwarn:0   dfail:0   fail:0   skip:32
> >skl-i7k-2        total:200  pass:173  dwarn:0   dfail:0   fail:0   skip:27
> >skl-nuci5        total:200  pass:189  dwarn:0   dfail:0   fail:0   skip:11
> >snb-dellxps      total:200  pass:158  dwarn:0   dfail:0   fail:0   skip:42
> >snb-x220t        total:200  pass:158  dwarn:0   dfail:0   fail:1   skip:41
> >
> >Results at /archive/results/CI_IGT_test/Patchwork_2068/
> >
> >f814551aa7232ed36d71244dd148b48660b53a78 drm-intel-nightly: 2016y-04m-25d-11h-36m-27s UTC integration manifest
> >c8a3953 drm/i915: resize the GuC WOPCM for rc6
> >
> >
> 
> --
>    Peter Antoine (Android Graphics Driver Software Engineer)
>    ---------------------------------------------------------------------
>    Intel Corporation (UK) Limited
>    Registered No. 1134945 (England)
>    Registered Office: Pipers Way, Swindon SN3 1RJ
>    VAT No: 860 2173 47
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: ✗ Fi.CI.BAT: failure for drm/i915: resize the GuC WOPCM for rc6

[Antoine, Peter]

-----Original Message-----
From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Tuesday, April 26, 2016 3:20 PM
To: Antoine, Peter <peter.antoine@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: resize the GuC WOPCM for rc6

On Tue, Apr 26, 2016 at 11:38:46AM +0100, Peter Antoine wrote:
> On Tue, 26 Apr 2016, Patchwork wrote:
> 
> >== Series Details ==
> >
> >Series: drm/i915: resize the GuC WOPCM for rc6
> >URL   : https://patchwork.freedesktop.org/series/6313/
> >State : failure
> >
> >== Summary ==
> >
> >Series 6313v1 drm/i915: resize the GuC WOPCM for rc6 
> >http://patchwork.freedesktop.org/api/1.0/series/6313/revisions/1/mbox
> >/
> >
> >Test kms_flip:
> >       Subgroup basic-flip-vs-wf_vblank:
> >               pass       -> FAIL       (hsw-gt2)
> Patch cannot effect HSW as platform does not have GuC and GuC code is 
> all guarded by platform. False Failure.

Already reported.
https://bugs.freedesktop.org/show_bug.cgi?id=94294

> 
> >Test kms_force_connector_basic:
> >       Subgroup force-edid:
> >               pass       -> SKIP       (ivb-t430s)
> Nothing to do with display.

Already reported:
https://bugs.freedesktop.org/show_bug.cgi?id=93123
> 
> >Test kms_pipe_crc_basic:
> >       Subgroup read-crc-pipe-b-frame-sequence:
> >               skip       -> PASS       (bdw-nuci7)
> Same.
The BAT should not fail on a pass.

The idea is to digg through bugzilla to make sure we have bugs for all of these, not just shrug them off.

Yes this is work, and yes it's meant to motivate people to fix up all the fail we still have.
-Daniel

> 
> >
> >bdw-nuci7        total:200  pass:188  dwarn:0   dfail:0   fail:0   skip:12
> >bdw-ultra        total:200  pass:175  dwarn:0   dfail:0   fail:0   skip:25
> >bsw-nuc-2        total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> >byt-nuc          total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> >hsw-brixbox      total:200  pass:174  dwarn:0   dfail:0   fail:0   skip:26
> >hsw-gt2          total:200  pass:178  dwarn:0   dfail:0   fail:1   skip:21
> >ilk-hp8440p      total:200  pass:139  dwarn:0   dfail:0   fail:0   skip:61
> >ivb-t430s        total:200  pass:168  dwarn:0   dfail:0   fail:0   skip:32
> >skl-i7k-2        total:200  pass:173  dwarn:0   dfail:0   fail:0   skip:27
> >skl-nuci5        total:200  pass:189  dwarn:0   dfail:0   fail:0   skip:11
> >snb-dellxps      total:200  pass:158  dwarn:0   dfail:0   fail:0   skip:42
> >snb-x220t        total:200  pass:158  dwarn:0   dfail:0   fail:1   skip:41
> >
> >Results at /archive/results/CI_IGT_test/Patchwork_2068/
> >
> >f814551aa7232ed36d71244dd148b48660b53a78 drm-intel-nightly: 
> >2016y-04m-25d-11h-36m-27s UTC integration manifest
> >c8a3953 drm/i915: resize the GuC WOPCM for rc6
> >
> >
> 
> --
>    Peter Antoine (Android Graphics Driver Software Engineer)
>    ---------------------------------------------------------------------
>    Intel Corporation (UK) Limited
>    Registered No. 1134945 (England)
>    Registered Office: Pipers Way, Swindon SN3 1RJ
>    VAT No: 860 2173 47
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Dave Gordon]

[-- Attachment #1: Type: text/plain, Size: 2279 bytes --]

On 26/04/2016 10:11, Peter Antoine wrote:
> This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
> spaces do not overlap.
>
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_reg.h     | 5 +++--
>   drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++++-
>   2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 80786d9..6e01238 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -68,10 +68,11 @@
>   #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>   
>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> +#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
> +#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
>   
>   /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> -#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
> +#define	GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
>   
>   #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>   #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index fc3ff68..38fb321 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -312,7 +312,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>   	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>   
>   	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +	if (IS_BROXTON(dev))
> +		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> +	else
> +		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +
>   	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>   
>   	/* Enable MIA caching. GuC clock gating is disabled. */

So, this gives the right result, but doesn't really show or explain why 
we have different values, or how the values are arrived at; they're just 
more magic numbers. Also, in the loader there's a check on the firmware 
size that uses different values. So I'd rather prefer the unified 
approach in the attached version ...

.Dave.

[-- Attachment #2: 0001-drm-i915-bxt-reserve-space-for-RC6-in-the-the-GuC-WO.patch --]
[-- Type: text/plain, Size: 3073 bytes --]

>From fa0f5e514eea4342933e237e693ea547b9b10f81 Mon Sep 17 00:00:00 2001
From: Peter Antoine <peter.antoine@intel.com>
Date: Tue, 26 Apr 2016 10:11:41 +0100
Subject: [PATCH] drm/i915/bxt: reserve space for RC6 in the the GuC WOPCM
Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ

This patch resizes the GuC WOPCM (specifically on BXT)
so that the GuC and RC6 memory spaces do not overlap.

Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_reg.h     |  6 +++---
 drivers/gpu/drm/i915/intel_guc_loader.c | 17 +++++++++++++----
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 80786d9..cf5a65b 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -67,11 +67,11 @@
 #define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 
+/* Defines WOPCM space available to GuC firmware */
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
-#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
-
 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
+#define   GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
+#define   BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
 
 #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
 #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 876e5da..80fc1e0 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -281,6 +281,17 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
+{
+	u32 wopcm_size = GUC_WOPCM_TOP;
+
+	/* On BXT, the top of WOPCM is reserved for RC6 context */
+	if (IS_BROXTON(dev_priv))
+		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
+
+	return wopcm_size;
+}
+
 /*
  * Load the GuC firmware blob into the MinuteIA.
  */
@@ -308,7 +319,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+	I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 
 	/* Enable MIA caching. GuC clock gating is disabled. */
@@ -552,9 +563,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 
 	/* Header and uCode will be loaded to WOPCM. Size of the two. */
 	size = guc_fw->header_size + guc_fw->ucode_size;
-
-	/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
-	if (size > GUC_WOPCM_SIZE_VALUE - 0x8000) {
+	if (size > guc_wopcm_size(dev->dev_private)) {
 		DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 		goto fail;
 	}
-- 
1.9.1


[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Antoine, Peter]

The attached version still does not explain that the WOPCM_TOP is to tell the GuC not to use that space.
The extra information does not aid anybody as the information is used internally within the GuC.

But, I have not actual objection to the patch.

Peter.

-----Original Message-----
From: Gordon, David S 
Sent: Thursday, May 5, 2016 2:41 PM
To: Antoine, Peter <peter.antoine@intel.com>; intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Subject: Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

On 26/04/2016 10:11, Peter Antoine wrote:
> This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory 
> spaces do not overlap.
>
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_reg.h     | 5 +++--
>   drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++++-
>   2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
> b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 80786d9..6e01238 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -68,10 +68,11 @@
>   #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>   
>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> +#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
> +#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
>   
>   /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> -#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
> +#define	GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
>   
>   #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>   #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index fc3ff68..38fb321 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -312,7 +312,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>   	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>   
>   	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +	if (IS_BROXTON(dev))
> +		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> +	else
> +		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +
>   	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>   
>   	/* Enable MIA caching. GuC clock gating is disabled. */

So, this gives the right result, but doesn't really show or explain why we have different values, or how the values are arrived at; they're just more magic numbers. Also, in the loader there's a check on the firmware size that uses different values. So I'd rather prefer the unified approach in the attached version ...

.Dave.
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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Dave Gordon]

[-- Attachment #1.1: Type: text/plain, Size: 978 bytes --]

On 05/05/2016 15:02, Antoine, Peter wrote:
> The attached version still does not explain that the WOPCM_TOP is to tell the GuC not to use that space.

That's NOT what WOPCM_TOP means. The GuC is allowed to use the space up 
to the value stored in the GUC_WOPCM_SIZE register (as the comment above 
the #define says). Architecturally, this is allowed to be any value 
greater than (16K+sizeof internal SRAM (64, 128, or 256K)) and less than 
or equal to GUC_WOPCM_TOP (which is a platform-independent constant), so 
we normally choose the maximm allowed. Howver on BXT, we need to leave 
some space at the top for the RC6 image, hence the logic (and comments!) 
in guc_wopcm_size().

> The extra information does not aid anybody as the information is used internally within the GuC.
It may help the next person who has to figure out what's gone wrong on 
some future chip that needs more than 64K for RC6!

.Dave.
>
> But, I have not actual objection to the patch.
>
> Peter.
>


[-- Attachment #1.2: Type: text/html, Size: 1828 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Peter Antoine]

On Thu, 5 May 2016, Dave Gordon wrote:

> On 05/05/2016 15:02, Antoine, Peter wrote:
> 
> The attached version still does not explain that the WOPCM_TOP is to tell the GuC not to use that space.
> 
> 
> That's NOT what WOPCM_TOP means. The GuC is allowed to use the space up to the value stored in the GUC_WOPCM_SIZE register (as the comment above the #define says). Architecturally, this is allowed to be any value greater than
> (16K+sizeof internal SRAM (64, 128, or 256K)) and less than or equal to GUC_WOPCM_TOP (which is a platform-independent constant), so we normally choose the maximm allowed. Howver on BXT, we need to leave some space at the top for the
> RC6 image, hence the logic (and comments!) in guc_wopcm_size().
Yes, the firmware can use upto GUC_WOPCM_TOP and to leave the rest alone.
> 
> The extra information does not aid anybody as the information is used internally within the GuC.
> 
> It may help the next person who has to figure out what's gone wrong on some future chip that needs more than 64K for RC6!

You hid a if statement in a function (making the code harder to read and 
more prone to error). Where maybe a slightly clearer comment was required.

And this patch has been held up two weeks just for a better comment.

Peter.
> 
> .Dave.

And what if the next reserved space is not for RC6?

> 
> 
> But, I have not actual objection to the patch.
> 
> Peter.
> 
> 
> 
>

--
    Peter Antoine (Android Graphics Driver Software Engineer)
    ---------------------------------------------------------------------
    Intel Corporation (UK) Limited
    Registered No. 1134945 (England)
    Registered Office: Pipers Way, Swindon SN3 1RJ
    VAT No: 860 2173 47
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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Nick Hoath]

On 06/05/2016 08:01, Peter Antoine wrote:
> On Thu, 5 May 2016, Dave Gordon wrote:
>
>> On 05/05/2016 15:02, Antoine, Peter wrote:
>>
>> The attached version still does not explain that the WOPCM_TOP is to
>> tell the GuC not to use that space.
>>
>>
>> That's NOT what WOPCM_TOP means. The GuC is allowed to use the space
>> up to the value stored in the GUC_WOPCM_SIZE register (as the comment
>> above the #define says). Architecturally, this is allowed to be any
>> value greater than
>> (16K+sizeof internal SRAM (64, 128, or 256K)) and less than or equal
>> to GUC_WOPCM_TOP (which is a platform-independent constant), so we
>> normally choose the maximm allowed. Howver on BXT, we need to leave
>> some space at the top for the
>> RC6 image, hence the logic (and comments!) in guc_wopcm_size().
> Yes, the firmware can use upto GUC_WOPCM_TOP and to leave the rest alone.
>>
>> The extra information does not aid anybody as the information is used
>> internally within the GuC.
>>
>> It may help the next person who has to figure out what's gone wrong on
>> some future chip that needs more than 64K for RC6!
>
> You hid a if statement in a function (making the code harder to read and
> more prone to error). Where maybe a slightly clearer comment was required.
>
> And this patch has been held up two weeks just for a better comment.
>
> Peter.
>>
>> .Dave.
>
> And what if the next reserved space is not for RC6?
>
>>
>>
>> But, I have not actual objection to the patch.
>>
>> Peter.
>>
>>
>>
>>
Tested-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
>
> --
>     Peter Antoine (Android Graphics Driver Software Engineer)
>     ---------------------------------------------------------------------
>     Intel Corporation (UK) Limited
>     Registered No. 1134945 (England)
>     Registered Office: Pipers Way, Swindon SN3 1RJ
>     VAT No: 860 2173 47
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Nick Hoath]

On 05/05/2016 16:04, Dave Gordon wrote:
> On 05/05/2016 15:02, Antoine, Peter wrote:
>> The attached version still does not explain that the WOPCM_TOP is to tell the GuC not to use that space.
>
> That's NOT what WOPCM_TOP means. The GuC is allowed to use the space up
> to the value stored in the GUC_WOPCM_SIZE register (as the comment above
> the #define says). Architecturally, this is allowed to be any value
> greater than (16K+sizeof internal SRAM (64, 128, or 256K)) and less than
> or equal to GUC_WOPCM_TOP (which is a platform-independent constant), so
> we normally choose the maximm allowed. Howver on BXT, we need to leave
> some space at the top for the RC6 image, hence the logic (and comments!)
> in guc_wopcm_size().
>
>> The extra information does not aid anybody as the information is used internally within the GuC.
> It may help the next person who has to figure out what's gone wrong on
> some future chip that needs more than 64K for RC6!
>
> .Dave.
>>
>> But, I have not actual objection to the patch.
>>
>> Peter.
>>
>
Unfortunately Dave's patch locked my test system on bootup, so I've t-b 
& r-b'd Peter's.
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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Dave Gordon]

On 06/05/16 10:37, Nick Hoath wrote:
> On 05/05/2016 16:04, Dave Gordon wrote:
>> On 05/05/2016 15:02, Antoine, Peter wrote:
>>> The attached version still does not explain that the WOPCM_TOP is to
>>> tell the GuC not to use that space.
>>
>> That's NOT what WOPCM_TOP means. The GuC is allowed to use the space up
>> to the value stored in the GUC_WOPCM_SIZE register (as the comment above
>> the #define says). Architecturally, this is allowed to be any value
>> greater than (16K+sizeof internal SRAM (64, 128, or 256K)) and less than
>> or equal to GUC_WOPCM_TOP (which is a platform-independent constant), so
>> we normally choose the maximm allowed. Howver on BXT, we need to leave
>> some space at the top for the RC6 image, hence the logic (and comments!)
>> in guc_wopcm_size().
>>
>>> The extra information does not aid anybody as the information is used
>>> internally within the GuC.
>> It may help the next person who has to figure out what's gone wrong on
>> some future chip that needs more than 64K for RC6!
>>
>> .Dave.
>>>
>>> But, I have not actual objection to the patch.
>>>
>>> Peter.
>>>
>>
> Unfortunately Dave's patch locked my test system on bootup, so I've t-b
> & r-b'd Peter's.

They're equivalent, unless your firmware happens to be between 458752 
and 491520 bytes in size (in which case you have a problem anyway).

To check, I've run both versions, with debug printing the value chosen 
(on SKL) and the value that would have been chosen on BXT, and they're 
identical (and both work). So I think your build had some other problem 
unrelated to the specific patch.

I've no problem with using Peter's patch for now, but it's not just a 
matter of the comments; there's also the other use(s) of 
GUC_WOP_(TOP,SIZE_VALUE), with ad-hoc additions or subtractions. So it 
still needs fixing properly.

.Dave.
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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Nick Hoath]

On 06/05/2016 13:18, Gordon, David S wrote:
> On 06/05/16 10:37, Nick Hoath wrote:
>> On 05/05/2016 16:04, Dave Gordon wrote:
>>> On 05/05/2016 15:02, Antoine, Peter wrote:
>>>> The attached version still does not explain that the WOPCM_TOP is to
>>>> tell the GuC not to use that space.
>>>
>>> That's NOT what WOPCM_TOP means. The GuC is allowed to use the space up
>>> to the value stored in the GUC_WOPCM_SIZE register (as the comment above
>>> the #define says). Architecturally, this is allowed to be any value
>>> greater than (16K+sizeof internal SRAM (64, 128, or 256K)) and less than
>>> or equal to GUC_WOPCM_TOP (which is a platform-independent constant), so
>>> we normally choose the maximm allowed. Howver on BXT, we need to leave
>>> some space at the top for the RC6 image, hence the logic (and comments!)
>>> in guc_wopcm_size().
>>>
>>>> The extra information does not aid anybody as the information is used
>>>> internally within the GuC.
>>> It may help the next person who has to figure out what's gone wrong on
>>> some future chip that needs more than 64K for RC6!
>>>
>>> .Dave.
>>>>
>>>> But, I have not actual objection to the patch.
>>>>
>>>> Peter.
>>>>
>>>
>> Unfortunately Dave's patch locked my test system on bootup, so I've t-b
>> & r-b'd Peter's.
>
> They're equivalent, unless your firmware happens to be between 458752
> and 491520 bytes in size (in which case you have a problem anyway).
>
> To check, I've run both versions, with debug printing the value chosen
> (on SKL) and the value that would have been chosen on BXT, and they're
> identical (and both work). So I think your build had some other problem
> unrelated to the specific patch.
>
> I've no problem with using Peter's patch for now, but it's not just a
> matter of the comments; there's also the other use(s) of
> GUC_WOP_(TOP,SIZE_VALUE), with ad-hoc additions or subtractions. So it
> still needs fixing properly.
>
> .Dave.
>
After a rebuild & a retest, Dave's patch works fine. Therefore for 
"drm/i915/bxt: reserve space for RC6 in the the GuC WOPCM":
Tested-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>


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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Bob Paauwe]

On Tue, 26 Apr 2016 10:11:41 +0100
Peter Antoine <peter.antoine@intel.com> wrote:

> This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
> spaces do not overlap.

Hi Peter,

With this patch applied to our IOTG kernel tree, I see a regression
with the RC6 residency values.  The pm_rc6_residency fails the accuracy
test. 

The counter is still updating, but instead of seeing appx. 3000ms in
RC6 I see appx. 100ms during the 3 second sleep.

Simply reverting this one change makes the RC6 residency counts go back
to normal.  Seems like this patch should fix a problem like this, not
cause it. 

This is on a Leaf Hill BXT CRB platform.

Any pointers or thoughts on how to debug this would be appreciated.

Thanks,
Bob

> 
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_reg.h     | 5 +++--
>  drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++++-
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 80786d9..6e01238 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -68,10 +68,11 @@
>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>  
>  #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> +#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
> +#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
>  
>  /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> -#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
> +#define	GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
>  
>  #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>  #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index fc3ff68..38fb321 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -312,7 +312,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +	if (IS_BROXTON(dev))
> +		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> +	else
> +		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +
>  	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>  
>  	/* Enable MIA caching. GuC clock gating is disabled. */



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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Re: [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

[Antoine, Peter]

Hi Bob,

It was tested on a BXT-T RVP and LeafHill A and worked fine. The patch has been in the Android tree for at least a couple of months (probably more) and has seemed to be stable. But, not sure Android was run on the BXT CRB.
 
It could be the GuC firmware crashing, there are some fixes in 8.7. Has the size of the SRAM changed on that board?
Is something else reserving space in that area?

The size that was reserved was passed onto us from the GuC firmware team via the RC6 team. It might be worth talking to the power team in Bangalore. sagar.a.kamble@intel.com is probably your best bet for RC6 issues.

I hope that helps.

Peter. 

-----Original Message-----
From: Paauwe, Bob J 
Sent: Tuesday, May 10, 2016 4:59 PM
To: Antoine, Peter <peter.antoine@intel.com>
Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

On Tue, 26 Apr 2016 10:11:41 +0100
Peter Antoine <peter.antoine@intel.com> wrote:

> This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory 
> spaces do not overlap.

Hi Peter,

With this patch applied to our IOTG kernel tree, I see a regression with the RC6 residency values.  The pm_rc6_residency fails the accuracy test. 

The counter is still updating, but instead of seeing appx. 3000ms in
RC6 I see appx. 100ms during the 3 second sleep.

Simply reverting this one change makes the RC6 residency counts go back to normal.  Seems like this patch should fix a problem like this, not cause it. 

This is on a Leaf Hill BXT CRB platform.

Any pointers or thoughts on how to debug this would be appreciated.

Thanks,
Bob

> 
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_reg.h     | 5 +++--
>  drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++++-
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
> b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 80786d9..6e01238 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -68,10 +68,11 @@
>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>  
>  #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> +#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
> +#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
>  
>  /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> -#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
> +#define	GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
>  
>  #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>  #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index fc3ff68..38fb321 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -312,7 +312,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +	if (IS_BROXTON(dev))
> +		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> +	else
> +		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +
>  	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>  
>  	/* Enable MIA caching. GuC clock gating is disabled. */



--
--
Bob Paauwe                  
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IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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