From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Zhi Wang <zhi.a.wang@intel.com>,
intel-gfx@lists.freedesktop.org, david.s.gordon@intel.com,
joonas.lahtinen@linux.intel.com, kevin.tian@intel.com,
zhiyuan.lv@intel.com
Subject: Re: [PATCH 05/15] drm/i915: Set ctx->ppgtt for aliasing PPGTT in context creation
Date: Mon, 16 May 2016 14:30:55 +0100 [thread overview]
Message-ID: <5739CB8F.60809@linux.intel.com> (raw)
In-Reply-To: <1463333573-25112-6-git-send-email-zhi.a.wang@intel.com>
On 15/05/16 18:32, Zhi Wang wrote:
> Currently ctx->ppgtt would only be initialized when full PPGTT is used.
> For aliasing PPGTT mode, ctx->ppgtt will be set when LRC context is
> populated.
>
> This patch moves the assignment into i915_gem_create_context() for better
> code structure.
Hm, it doesn't move the assignment it adds it.
Previously ctx->ppgtt was always NULL when !USES_FULL_PPGTT. Now it will
point to aliasing ppgtt.
Since there are various places in the code which do "if (ctx->ppgtt)"
(more or less) I think you need to explain why those will still work OK.
i915_gem_context_free for example?
Regards,
Tvrtko
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 4 +++-
> drivers/gpu/drm/i915/intel_lrc.c | 3 ---
> 2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 2aedd18..21498e5 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -300,6 +300,7 @@ static struct intel_context *
> i915_gem_create_context(struct drm_device *dev,
> struct drm_i915_file_private *file_priv)
> {
> + struct drm_i915_private *dev_priv = dev->dev_private;
> const bool is_global_default_ctx = file_priv == NULL;
> struct intel_context *ctx;
> int ret = 0;
> @@ -337,7 +338,8 @@ i915_gem_create_context(struct drm_device *dev,
> }
>
> ctx->ppgtt = ppgtt;
> - }
> + } else
> + ctx->ppgtt = dev_priv->mm.aliasing_ppgtt;
>
> trace_i915_context_create(ctx);
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index db10c96..397fe65 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2286,9 +2286,6 @@ populate_lr_context(struct intel_context *ctx,
> u32 *reg_state;
> int ret;
>
> - if (!ppgtt)
> - ppgtt = dev_priv->mm.aliasing_ppgtt;
> -
> ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
> if (ret) {
> DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-05-16 13:30 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-15 17:32 [PATCH 00/15] Introduce the implementation of GVT context Zhi Wang
2016-05-15 17:32 ` [PATCH 01/15] drm/i915: Factor out i915_pvinfo.h Zhi Wang
2016-05-15 17:32 ` [PATCH 02/15] drm/i915/gvt: Fold vGPU active check into inner functions Zhi Wang
2016-05-16 10:49 ` Tvrtko Ursulin
2016-05-16 13:56 ` Wang, Zhi A
2016-05-15 17:32 ` [PATCH 03/15] drm/i915: gvt: Introduce the basic architecture of GVT-g Zhi Wang
2016-05-16 12:03 ` Tvrtko Ursulin
2016-05-17 2:55 ` Wang, Zhi A
2016-05-15 17:32 ` [PATCH 04/15] drm/i915: Introduce host graphics memory partition for GVT-g Zhi Wang
2016-05-15 17:32 ` [PATCH 05/15] drm/i915: Set ctx->ppgtt for aliasing PPGTT in context creation Zhi Wang
2016-05-16 13:30 ` Tvrtko Ursulin [this message]
2016-05-16 14:16 ` Wang, Zhi A
2016-05-16 14:26 ` Wang, Zhi A
2016-05-15 17:32 ` [PATCH 06/15] drm/i915: Allow the caller to create a intel_context without PPGTT Zhi Wang
2016-05-16 15:13 ` Chris Wilson
2016-05-16 15:18 ` Wang, Zhi A
2016-05-15 17:32 ` [PATCH 07/15] drm/i915: Populate context PDPs if it has a PPGTT Zhi Wang
2016-05-15 17:32 ` [PATCH 08/15] drm/i915: Introduce an option for skipping engine context initialization Zhi Wang
2016-05-15 17:32 ` [PATCH 09/15] drm/i915: Make ring buffer size configurable Zhi Wang
2016-05-15 17:32 ` [PATCH 10/15] drm/i915: Generate addressing mode bit from flag in context Zhi Wang
2016-05-16 13:47 ` Tvrtko Ursulin
2016-05-15 17:32 ` [PATCH 11/15] drm/i915: Introduce execlist context status change notification Zhi Wang
2016-05-16 14:00 ` Tvrtko Ursulin
2016-05-16 14:28 ` Wang, Zhi A
2016-05-15 17:32 ` [PATCH 12/15] drm/i915: Support context single submission Zhi Wang
2016-05-15 17:32 ` [PATCH 13/15] drm/i915: Introduce GVT context creation API Zhi Wang
2016-05-15 17:32 ` [PATCH 14/15] drm/i915: Factor out and expose i915_steal_fence() Zhi Wang
2016-05-16 14:57 ` Chris Wilson
2016-05-16 15:13 ` Wang, Zhi A
2016-05-15 17:32 ` [PATCH 15/15] drm/i915: Expose i915_find_fence_reg() Zhi Wang
2016-05-16 5:29 ` ✗ Ro.CI.BAT: failure for Introduce the implementation of GVT context Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5739CB8F.60809@linux.intel.com \
--to=tvrtko.ursulin@linux.intel.com \
--cc=david.s.gordon@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=joonas.lahtinen@linux.intel.com \
--cc=kevin.tian@intel.com \
--cc=zhi.a.wang@intel.com \
--cc=zhiyuan.lv@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox