* [PATCH 0/9] Introduce the implementation of GVT context
@ 2016-05-17 8:19 Zhi Wang
2016-05-17 8:19 ` [PATCH 1/9] drm/i915: Factor out i915_pvinfo.h Zhi Wang
` (9 more replies)
0 siblings, 10 replies; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
Mostly this patchset introduces the implementation of GVT context. GVT
context is a special GEM context used by GVT-g. GVT-g uses it as the shadow
context.It doesn't have a drm client nor a PPGTT. And it requires a larger
ring buffer with several special features need by GVT-g workload scheduler
like context status change notification, context single submission...
v5:
- Drop PPGTT related patches.
- Let most functions take struct drm_i915_private *
- Fixed some misspelled words in Kconfig
- Only complied some feature when CONFIG_DRM_I915_GVT=y
- Drop the fecne related changes, will send it after this series.
v4:
- Based on the latest drm-intel-nightly branch.
- Drop PPGTT refactor patches. (GVT-g will use LRI to load PDPs)
- Drop i915_gem_context() refactor patches, reuse kernel context functions.
(Dave Gordon)
- Drop context allocation params and refactor as the lrc deferred
allocation function has been refactored in another styles.
- Re-wrtie GVT context creation function
Difference from community release
---------------------------------
This patchset is different from regular iGVT-g code release[4], which
is still based on old host-mediated architecture. Furthermore, this
patchset only supports BDW whereas code release supports HSW/BDW/SKL.
We will add SKL support later based on this RFC code and HSW support
will be dropped.
Internally we tested this RFC patchset with both linux and windows VM
and the architecture changes work fine.
Acknowledgment
---------------
iGVT-g implementation is several years effort and many people
contributed to the code. There names are not here yet. In later formal
patchset we will reflect individual's contribution.
st
Meanwhile, in the previous iGVT-g related discussion, Daniel, Chris
and Joonas ever gave very good inputs. We appreciate them and look
forward to more comments/suggestions from community.
We are trying to get more familiar with i915 but may still have gaps.
We are willing to adopt suggestions to keep improving. We hope to work
with community together to make iGVT-g a great component in i915 to
support graphics virtualization. Thanks!
Reference
---------
[1] https://01.org/igvt-g
[2] http://lists.freedesktop.org/archives/intel-gfx/2014-September/053098.html
[3] http://lists.freedesktop.org/archives/intel-gfx/2015-September/075397.html
Bing Niu (1):
drm/i915: Introduce host graphics memory partition for GVT-g
Zhi Wang (8):
drm/i915: Factor out i915_pvinfo.h
drm/i915/gvt: Fold vGPU active check into inner functions
drm/i915: gvt: Introduce the basic architecture of GVT-g
drm/i915: Make ring buffer size configurable
drm/i915: Generate addressing mode bit from flag in context.
drm/i915: Introduce execlist context status change notification
drm/i915: Support context single submission
drm/i915: Introduce GVT context creation API
drivers/gpu/drm/i915/Kconfig | 15 +++
drivers/gpu/drm/i915/Makefile | 5 +
drivers/gpu/drm/i915/gvt/Makefile | 5 +
drivers/gpu/drm/i915/gvt/debug.h | 36 ++++++
drivers/gpu/drm/i915/gvt/gvt.c | 205 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gvt/gvt.h | 84 +++++++++++++
drivers/gpu/drm/i915/gvt/hypercall.h | 38 ++++++
drivers/gpu/drm/i915/gvt/mpt.h | 49 ++++++++
drivers/gpu/drm/i915/i915_dma.c | 17 ++-
drivers/gpu/drm/i915/i915_drv.h | 45 ++++++-
drivers/gpu/drm/i915/i915_gem_context.c | 33 +++++
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 +-
drivers/gpu/drm/i915/i915_pvinfo.h | 115 ++++++++++++++++++
drivers/gpu/drm/i915/i915_vgpu.c | 32 +++--
drivers/gpu/drm/i915/i915_vgpu.h | 90 +-------------
drivers/gpu/drm/i915/intel_gvt.c | 140 ++++++++++++++++++++++
drivers/gpu/drm/i915/intel_gvt.h | 51 ++++++++
drivers/gpu/drm/i915/intel_lrc.c | 62 +++++++++-
drivers/gpu/drm/i915/intel_lrc.h | 7 ++
include/drm/i915_gvt.h | 31 +++++
20 files changed, 958 insertions(+), 113 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gvt/Makefile
create mode 100644 drivers/gpu/drm/i915/gvt/debug.h
create mode 100644 drivers/gpu/drm/i915/gvt/gvt.c
create mode 100644 drivers/gpu/drm/i915/gvt/gvt.h
create mode 100644 drivers/gpu/drm/i915/gvt/hypercall.h
create mode 100644 drivers/gpu/drm/i915/gvt/mpt.h
create mode 100644 drivers/gpu/drm/i915/i915_pvinfo.h
create mode 100644 drivers/gpu/drm/i915/intel_gvt.c
create mode 100644 drivers/gpu/drm/i915/intel_gvt.h
create mode 100644 include/drm/i915_gvt.h
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/9] drm/i915: Factor out i915_pvinfo.h
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
@ 2016-05-17 8:19 ` Zhi Wang
2016-05-17 8:19 ` [PATCH 2/9] drm/i915/gvt: Fold vGPU active check into inner functions Zhi Wang
` (8 subsequent siblings)
9 siblings, 0 replies; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
As the PVINFO page definition is used by both GVT-g guest (vGPU) and GVT-g
host (GVT-g kernel device model), factor it out for better code structure.
v3:
Take Joonas's comments:
- Use offsetof to calculate the member offset of PVINFO structure
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_pvinfo.h | 115 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_vgpu.h | 86 +--------------------------
2 files changed, 116 insertions(+), 85 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_pvinfo.h
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
new file mode 100644
index 0000000..6eff6d9
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _I915_PVINFO_H_
+
+/* The MMIO offset of the shared info between guest and host emulator */
+#define VGT_PVINFO_PAGE 0x78000
+#define VGT_PVINFO_SIZE 0x1000
+
+/*
+ * The following structure pages are defined in GEN MMIO space
+ * for virtualization. (One page for now)
+ */
+#define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */
+#define VGT_VERSION_MAJOR 1
+#define VGT_VERSION_MINOR 0
+
+#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
+#define INTEL_VGT_IF_VERSION \
+ INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
+
+/*
+ * notifications from guest to vgpu device model
+ */
+enum vgt_g2v_type {
+ VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
+ VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
+ VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
+ VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
+ VGT_G2V_EXECLIST_CONTEXT_CREATE,
+ VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+ VGT_G2V_MAX,
+};
+
+struct vgt_if {
+ uint64_t magic; /* VGT_MAGIC */
+ uint16_t version_major;
+ uint16_t version_minor;
+ uint32_t vgt_id; /* ID of vGT instance */
+ uint32_t rsv1[12]; /* pad to offset 0x40 */
+ /*
+ * Data structure to describe the balooning info of resources.
+ * Each VM can only have one portion of continuous area for now.
+ * (May support scattered resource in future)
+ * (starting from offset 0x40)
+ */
+ struct {
+ /* Aperture register balooning */
+ struct {
+ uint32_t base;
+ uint32_t size;
+ } mappable_gmadr; /* aperture */
+ /* GMADR register balooning */
+ struct {
+ uint32_t base;
+ uint32_t size;
+ } nonmappable_gmadr; /* non aperture */
+ /* allowed fence registers */
+ uint32_t fence_num;
+ uint32_t rsv2[3];
+ } avail_rs; /* available/assigned resource */
+ uint32_t rsv3[0x200 - 24]; /* pad to half page */
+ /*
+ * The bottom half page is for response from Gfx driver to hypervisor.
+ */
+ uint32_t rsv4;
+ uint32_t display_ready; /* ready for display owner switch */
+
+ uint32_t rsv5[4];
+
+ uint32_t g2v_notify;
+ uint32_t rsv6[7];
+
+ struct {
+ uint32_t lo;
+ uint32_t hi;
+ } pdp[4];
+
+ uint32_t execlist_context_descriptor_lo;
+ uint32_t execlist_context_descriptor_hi;
+
+ uint32_t rsv7[0x200 - 24]; /* pad to one page */
+} __packed;
+
+#define _vgtif_reg(x) \
+ (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
+
+#define vgtif_reg(x) \
+ _MMIO(_vgtif_reg(x))
+
+/* vGPU display status to be used by the host side */
+#define VGT_DRV_DISPLAY_NOT_READY 0
+#define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */
+
+#endif /* _I915_PVINFO_H_ */
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 21ffcfe..07e67d5 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -24,91 +24,7 @@
#ifndef _I915_VGPU_H_
#define _I915_VGPU_H_
-/* The MMIO offset of the shared info between guest and host emulator */
-#define VGT_PVINFO_PAGE 0x78000
-#define VGT_PVINFO_SIZE 0x1000
-
-/*
- * The following structure pages are defined in GEN MMIO space
- * for virtualization. (One page for now)
- */
-#define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */
-#define VGT_VERSION_MAJOR 1
-#define VGT_VERSION_MINOR 0
-
-#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
-#define INTEL_VGT_IF_VERSION \
- INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
-
-/*
- * notifications from guest to vgpu device model
- */
-enum vgt_g2v_type {
- VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
- VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
- VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
- VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
- VGT_G2V_EXECLIST_CONTEXT_CREATE,
- VGT_G2V_EXECLIST_CONTEXT_DESTROY,
- VGT_G2V_MAX,
-};
-
-struct vgt_if {
- uint64_t magic; /* VGT_MAGIC */
- uint16_t version_major;
- uint16_t version_minor;
- uint32_t vgt_id; /* ID of vGT instance */
- uint32_t rsv1[12]; /* pad to offset 0x40 */
- /*
- * Data structure to describe the balooning info of resources.
- * Each VM can only have one portion of continuous area for now.
- * (May support scattered resource in future)
- * (starting from offset 0x40)
- */
- struct {
- /* Aperture register balooning */
- struct {
- uint32_t base;
- uint32_t size;
- } mappable_gmadr; /* aperture */
- /* GMADR register balooning */
- struct {
- uint32_t base;
- uint32_t size;
- } nonmappable_gmadr; /* non aperture */
- /* allowed fence registers */
- uint32_t fence_num;
- uint32_t rsv2[3];
- } avail_rs; /* available/assigned resource */
- uint32_t rsv3[0x200 - 24]; /* pad to half page */
- /*
- * The bottom half page is for response from Gfx driver to hypervisor.
- */
- uint32_t rsv4;
- uint32_t display_ready; /* ready for display owner switch */
-
- uint32_t rsv5[4];
-
- uint32_t g2v_notify;
- uint32_t rsv6[7];
-
- struct {
- uint32_t lo;
- uint32_t hi;
- } pdp[4];
-
- uint32_t execlist_context_descriptor_lo;
- uint32_t execlist_context_descriptor_hi;
-
- uint32_t rsv7[0x200 - 24]; /* pad to one page */
-} __packed;
-
-#define vgtif_reg(x) \
- _MMIO((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x))
-
-/* vGPU display status to be used by the host side */
-#define VGT_DRV_DISPLAY_NOT_READY 0
-#define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */
+#include "i915_pvinfo.h"
extern void i915_check_vgpu(struct drm_i915_private *dev_priv);
extern int intel_vgt_balloon(struct drm_device *dev);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/9] drm/i915/gvt: Fold vGPU active check into inner functions
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
2016-05-17 8:19 ` [PATCH 1/9] drm/i915: Factor out i915_pvinfo.h Zhi Wang
@ 2016-05-17 8:19 ` Zhi Wang
2016-05-18 10:54 ` Tvrtko Ursulin
2016-05-17 8:19 ` [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g Zhi Wang
` (7 subsequent siblings)
9 siblings, 1 reply; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
v5:
- Let functions take struct drm_i915_private *. (Tvrtko)
- Fold vGPU related active check into the inner functions. (Kevin)
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++++-------
drivers/gpu/drm/i915/i915_vgpu.c | 13 +++++++++----
drivers/gpu/drm/i915/i915_vgpu.h | 4 ++--
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7eab619..820b59e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2737,11 +2737,9 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
i915_address_space_init(&ggtt->base, dev_priv);
ggtt->base.total += PAGE_SIZE;
- if (intel_vgpu_active(dev_priv)) {
- ret = intel_vgt_balloon(dev);
- if (ret)
- return ret;
- }
+ ret = intel_vgt_balloon(dev_priv);
+ if (ret)
+ return ret;
if (!HAS_LLC(dev))
ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
@@ -2841,8 +2839,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
i915_gem_cleanup_stolen(dev);
if (drm_mm_initialized(&ggtt->base.mm)) {
- if (intel_vgpu_active(dev_priv))
- intel_vgt_deballoon();
+ intel_vgt_deballoon(dev_priv);
drm_mm_takedown(&ggtt->base.mm);
list_del(&ggtt->base.global_link);
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index d5a7a5e..5312816 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -101,10 +101,13 @@ static struct _balloon_info_ bl_info;
* This function is called to deallocate the ballooned-out graphic memory, when
* driver is unloaded or when ballooning fails.
*/
-void intel_vgt_deballoon(void)
+void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
{
int i;
+ if (!intel_vgpu_active(dev_priv))
+ return;
+
DRM_DEBUG("VGT deballoon.\n");
for (i = 0; i < 4; i++) {
@@ -177,9 +180,8 @@ static int vgt_balloon_space(struct drm_mm *mm,
* Returns:
* zero on success, non-zero if configuration invalid or ballooning failed
*/
-int intel_vgt_balloon(struct drm_device *dev)
+int intel_vgt_balloon(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_ggtt *ggtt = &dev_priv->ggtt;
unsigned long ggtt_end = ggtt->base.start + ggtt->base.total;
@@ -187,6 +189,9 @@ int intel_vgt_balloon(struct drm_device *dev)
unsigned long unmappable_base, unmappable_size, unmappable_end;
int ret;
+ if (!intel_vgpu_active(dev_priv))
+ return 0;
+
mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
@@ -258,6 +263,6 @@ int intel_vgt_balloon(struct drm_device *dev)
err:
DRM_ERROR("VGT balloon fail\n");
- intel_vgt_deballoon();
+ intel_vgt_deballoon(dev_priv);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 07e67d5..f8917c6 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -27,7 +27,7 @@
#include "i915_pvinfo.h"
extern void i915_check_vgpu(struct drm_i915_private *dev_priv);
-extern int intel_vgt_balloon(struct drm_device *dev);
-extern void intel_vgt_deballoon(void);
+extern int intel_vgt_balloon(struct drm_i915_private *dev_priv);
+extern void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
#endif /* _I915_VGPU_H_ */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
2016-05-17 8:19 ` [PATCH 1/9] drm/i915: Factor out i915_pvinfo.h Zhi Wang
2016-05-17 8:19 ` [PATCH 2/9] drm/i915/gvt: Fold vGPU active check into inner functions Zhi Wang
@ 2016-05-17 8:19 ` Zhi Wang
2016-05-18 11:22 ` Tvrtko Ursulin
2016-05-20 11:49 ` Chris Wilson
2016-05-17 8:19 ` [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g Zhi Wang
` (6 subsequent siblings)
9 siblings, 2 replies; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.
v5:
Take Tvrtko's comments:
- Fix the misspelled words in Kconfg
- Let functions take drm_i915_private * instead of struct drm_device *
- Remove redundant prints/local varible initialization
v3:
Take Joonas' comments:
- Change file name i915_gvt.* to intel_gvt.*
- Move GVT kernel parameter into intel_gvt.c
- Remove redundant debug macros
- Change error handling style
- Add introductions for some stub functions
- Introduce drm/i915_gvt.h.
Take Kevin's comments:
- Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c
v2:
- Introduce i915_gvt.c.
It's necessary to introduce the stubs between i915 driver and GVT-g host,
as GVT-g components is configurable in kernel config. When disabled, the
stubs here do nothing.
Take Joonas' comments:
- Replace boolean return value with int.
- Replace customized info/warn/debug macros with DRM macros.
- Document all non-static functions like i915.
- Remove empty and unused functions.
- Replace magic number with marcos.
- Set GVT-g in kernel config to "n" by default.
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/Kconfig | 15 +++
drivers/gpu/drm/i915/Makefile | 5 +
drivers/gpu/drm/i915/gvt/Makefile | 5 +
drivers/gpu/drm/i915/gvt/debug.h | 36 ++++++
drivers/gpu/drm/i915/gvt/gvt.c | 205 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gvt/gvt.h | 84 ++++++++++++++
drivers/gpu/drm/i915/gvt/hypercall.h | 38 +++++++
drivers/gpu/drm/i915/gvt/mpt.h | 49 +++++++++
drivers/gpu/drm/i915/i915_dma.c | 17 ++-
drivers/gpu/drm/i915/i915_drv.h | 12 ++
drivers/gpu/drm/i915/intel_gvt.c | 98 +++++++++++++++++
drivers/gpu/drm/i915/intel_gvt.h | 49 +++++++++
include/drm/i915_gvt.h | 31 ++++++
13 files changed, 640 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gvt/Makefile
create mode 100644 drivers/gpu/drm/i915/gvt/debug.h
create mode 100644 drivers/gpu/drm/i915/gvt/gvt.c
create mode 100644 drivers/gpu/drm/i915/gvt/gvt.h
create mode 100644 drivers/gpu/drm/i915/gvt/hypercall.h
create mode 100644 drivers/gpu/drm/i915/gvt/mpt.h
create mode 100644 drivers/gpu/drm/i915/intel_gvt.c
create mode 100644 drivers/gpu/drm/i915/intel_gvt.h
create mode 100644 include/drm/i915_gvt.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 29a32b1..feb56ee 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -57,6 +57,21 @@ config DRM_I915_USERPTR
If in doubt, say "Y".
+config DRM_I915_GVT
+ bool "Intel GVT-g host driver"
+ depends on DRM_I915
+ default n
+ help
+ Enabling GVT-g mediated graphics pass-through technique for Intel i915
+ based integrated graphics card. With GVT-g, it's possible to have one
+ integrated i915 device shared by multiple VMs. Performance critical
+ operations such as aperture accesses and ring buffer operations
+ are passed-through to VM, with a minimal set of conflicting resources
+ (e.g. display settings) mediated by GVT host driver. The benefit of GVT
+ is on both the performance, given that each VM could directly operate
+ its aperture space and submit commands like running on native, and
+ the feature completeness, given that a true GEN hardware is exposed.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 63c4d2b..e48145b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -103,6 +103,11 @@ i915-y += i915_vgpu.o
# legacy horrors
i915-y += i915_dma.o
+ifeq ($(CONFIG_DRM_I915_GVT),y)
+i915-y += intel_gvt.o
+include $(src)/gvt/Makefile
+endif
+
obj-$(CONFIG_DRM_I915) += i915.o
CFLAGS_i915_trace_points.o := -I$(src)
diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile
new file mode 100644
index 0000000..d0f21a6
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -0,0 +1,5 @@
+GVT_DIR := gvt
+GVT_SOURCE := gvt.o
+
+ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall
+i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/debug.h b/drivers/gpu/drm/i915/gvt/debug.h
new file mode 100644
index 0000000..5b067d2
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/debug.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __GVT_DEBUG_H__
+#define __GVT_DEBUG_H__
+
+#define gvt_info(fmt, args...) \
+ DRM_INFO("gvt: "fmt, ##args)
+
+#define gvt_err(fmt, args...) \
+ DRM_ERROR("gvt: "fmt, ##args)
+
+#define gvt_dbg_core(fmt, args...) \
+ DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)
+
+#endif
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
new file mode 100644
index 0000000..aa40357
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <linux/types.h>
+#include <xen/xen.h>
+#include <linux/kthread.h>
+
+#include "gvt.h"
+
+struct intel_gvt_host intel_gvt_host;
+
+static const char * const supported_hypervisors[] = {
+ [INTEL_GVT_HYPERVISOR_XEN] = "XEN",
+ [INTEL_GVT_HYPERVISOR_KVM] = "KVM",
+};
+
+#define MB(x) (x * 1024ULL * 1024ULL)
+#define GB(x) (x * MB(1024))
+
+/*
+ * The layout of BAR0 in BDW:
+ * |< - MMIO 2MB ->|<- Reserved 6MB ->|<- MAX GTT 8MB->|
+ *
+ * GTT offset in BAR0 starts from 8MB to 16MB, and
+ * Whatever GTT size is configured in BIOS,
+ * the size of BAR0 is always 16MB. The actual configured
+ * GTT size can be found in GMCH_CTRL.
+ */
+static struct intel_gvt_device_info broadwell_device_info = {
+ .max_gtt_gm_sz = GB(4), /* 4GB */
+ .gtt_start_offset = MB(8), /* 8MB */
+ .max_gtt_size = MB(8), /* 8MB */
+ .gtt_entry_size = 8,
+ .gtt_entry_size_shift = 3,
+ .gmadr_bytes_in_cmd = 8,
+ .mmio_size = MB(2), /* 2MB */
+ .mmio_bar = 0, /* BAR 0 */
+ .max_support_vgpu = 8,
+};
+
+static int init_gvt_host(void)
+{
+ if (WARN(intel_gvt_host.initialized,
+ "Intel GVT host has already been initialized\n"))
+ return -EINVAL;
+
+ /* Xen DOM U */
+ if (xen_domain() && !xen_initial_domain())
+ return -ENODEV;
+
+ if (xen_initial_domain()) {
+ /* Xen Dom0 */
+ intel_gvt_host.mpt = try_then_request_module(
+ symbol_get(xengt_mpt), "xengt");
+ intel_gvt_host.hypervisor_type = INTEL_GVT_HYPERVISOR_XEN;
+ } else {
+ /* not in Xen. Try KVMGT */
+ intel_gvt_host.mpt = try_then_request_module(
+ symbol_get(kvmgt_mpt), "kvm");
+ intel_gvt_host.hypervisor_type = INTEL_GVT_HYPERVISOR_KVM;
+ }
+
+ if (!intel_gvt_host.mpt) {
+ gvt_err("Fail to load any MPT modules.\n");
+ return -EINVAL;
+ }
+
+ if (!intel_gvt_hypervisor_detect_host())
+ return -ENODEV;
+
+ gvt_info("Running with hypervisor %s in host mode\n",
+ supported_hypervisors[intel_gvt_host.hypervisor_type]);
+
+ idr_init(&intel_gvt_host.gvt_idr);
+ mutex_init(&intel_gvt_host.gvt_idr_lock);
+
+ intel_gvt_host.initialized = true;
+ return 0;
+}
+
+static int init_device_info(struct intel_gvt *gvt)
+{
+ if (IS_BROADWELL(gvt->dev_priv))
+ gvt->device_info = &broadwell_device_info;
+ else
+ return -ENODEV;
+
+ return 0;
+}
+
+static void free_gvt_device(struct intel_gvt *gvt)
+{
+ mutex_lock(&intel_gvt_host.gvt_idr_lock);
+ idr_remove(&intel_gvt_host.gvt_idr, gvt->id);
+ mutex_unlock(&intel_gvt_host.gvt_idr_lock);
+
+ vfree(gvt);
+}
+
+static struct intel_gvt *alloc_gvt_device(struct drm_i915_private *dev_priv)
+{
+ struct intel_gvt *gvt;
+ int ret;
+
+ gvt = vzalloc(sizeof(*gvt));
+ if (!gvt)
+ return ERR_PTR(-ENOMEM);
+
+ mutex_lock(&intel_gvt_host.gvt_idr_lock);
+ ret = idr_alloc(&intel_gvt_host.gvt_idr, gvt, 0, 0, GFP_KERNEL);
+ mutex_unlock(&intel_gvt_host.gvt_idr_lock);
+
+ if (ret < 0)
+ goto err;
+
+ gvt->id = ret;
+ mutex_init(&gvt->lock);
+ gvt->dev_priv = dev_priv;
+ idr_init(&gvt->vgpu_idr);
+
+ return gvt;
+err:
+ free_gvt_device(gvt);
+ return ERR_PTR(ret);
+}
+
+/**
+ * intel_gvt_destroy_device - destroy a GVT device
+ * @gvt_device: gvt device
+ *
+ * This function is called at the driver unloading stage, to destroy a
+ * GVT device and free the related resources.
+ *
+ */
+void intel_gvt_destroy_device(void *device)
+{
+ struct intel_gvt *gvt = (struct intel_gvt *)device;
+
+ free_gvt_device(gvt);
+}
+
+/**
+ * intel_gvt_create_device - create a GVT device
+ * @dev_priv: drm i915 private data
+ *
+ * This function is called at the initialization stage, to create a
+ * GVT device and initialize necessary GVT components for it.
+ *
+ * Returns:
+ * pointer to the intel gvt device structure, error pointer if failed.
+ */
+void *intel_gvt_create_device(struct drm_i915_private *dev_priv)
+{
+ struct intel_gvt *gvt;
+ int ret;
+
+ if (!intel_gvt_host.initialized) {
+ ret = init_gvt_host();
+ if (ret)
+ return ERR_PTR(ret);
+ }
+
+ gvt_dbg_core("create new gvt device\n");
+
+ gvt = alloc_gvt_device(dev_priv);
+ if (IS_ERR(gvt)) {
+ ret = PTR_ERR(gvt);
+ goto out_err;
+ }
+
+ gvt_dbg_core("init gvt device, id %d\n", gvt->id);
+
+ ret = init_device_info(gvt);
+ if (ret)
+ goto out_free_gvt_device;
+
+ gvt_dbg_core("gvt device creation done, id %d\n", gvt->id);
+
+ return gvt;
+
+out_free_gvt_device:
+ free_gvt_device(gvt);
+out_err:
+ return ERR_PTR(ret);
+}
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
new file mode 100644
index 0000000..9e6e22b
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _GVT_H_
+#define _GVT_H_
+
+#include "i915_drv.h"
+#include "i915_vgpu.h"
+
+#include "debug.h"
+#include "hypercall.h"
+
+#define GVT_MAX_VGPU 8
+#define GVT_ALIGN(addr, size) ((addr) & (~((typeof(addr))(size) - 1)))
+
+enum {
+ INTEL_GVT_HYPERVISOR_XEN = 0,
+ INTEL_GVT_HYPERVISOR_KVM,
+};
+
+struct intel_gvt_host {
+ bool initialized;
+ int hypervisor_type;
+ struct mutex gvt_idr_lock;
+ struct idr gvt_idr;
+ struct intel_gvt_mpt *mpt;
+};
+
+extern struct intel_gvt_host intel_gvt_host;
+
+/* Describe the limitation of HW.*/
+struct intel_gvt_device_info {
+ u64 max_gtt_gm_sz;
+ u32 gtt_start_offset;
+ u32 gtt_end_offset;
+ u32 max_gtt_size;
+ u32 gtt_entry_size;
+ u32 gtt_entry_size_shift;
+ u32 gmadr_bytes_in_cmd;
+ u32 mmio_size;
+ u32 mmio_bar;
+ u32 max_support_vgpu;
+};
+
+struct intel_vgpu {
+ struct intel_gvt *gvt;
+ int id;
+ int vm_id;
+ bool warn_untrack;
+};
+
+struct intel_gvt {
+ struct mutex lock;
+ int id;
+
+ struct drm_i915_private *dev_priv;
+ struct idr vgpu_idr;
+
+ struct intel_gvt_device_info *device_info;
+};
+
+#include "mpt.h"
+
+#endif
diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h
new file mode 100644
index 0000000..254df8b
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/hypercall.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _GVT_HYPERCALL_H_
+#define _GVT_HYPERCALL_H_
+
+/*
+ * Specific GVT-g MPT modules function collections. Currently GVT-g supports
+ * both Xen and KVM by providing dedicated hypervisor-related MPT modules.
+ */
+struct intel_gvt_mpt {
+ int (*detect_host)(void);
+};
+
+extern struct intel_gvt_mpt xengt_mpt;
+extern struct intel_gvt_mpt kvmgt_mpt;
+
+#endif /* _GVT_HYPERCALL_H_ */
diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h
new file mode 100644
index 0000000..783f4f8
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/mpt.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _GVT_MPT_H_
+#define _GVT_MPT_H_
+
+/**
+ * DOC: Hypervisor Service APIs for GVT-g Core Logic
+ *
+ * This is the glue layer between specific hypervisor MPT modules and GVT-g core
+ * logic. Each kind of hypervisor MPT module provides a collection of function
+ * callbacks via gvt_kernel_dm and will be attached to GVT host when driver
+ * loading. GVT-g core logic will call these APIs to request specific services
+ * from hypervisor.
+ */
+
+/**
+ * intel_gvt_hypervisor_detect_host - check if GVT-g is running within
+ * hypervisor host/privilged domain
+ *
+ * Returns:
+ * Zero on success, -ENODEV if current kernel is running inside a VM
+ */
+static inline int intel_gvt_hypervisor_detect_host(void)
+{
+ return intel_gvt_host.mpt->detect_host();
+}
+
+#endif /* _GVT_MPT_H_ */
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 547100f..502d7cd 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -35,6 +35,7 @@
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "intel_gvt.h"
#include "i915_vgpu.h"
#include "i915_trace.h"
#include <linux/pci.h>
@@ -1245,18 +1246,22 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
goto out_ggtt;
}
+ ret = intel_gvt_init(dev_priv);
+ if (ret)
+ goto out_ggtt;
+
/* WARNING: Apparently we must kick fbdev drivers before vgacon,
* otherwise the vga fbdev driver falls over. */
ret = i915_kick_out_firmware_fb(dev_priv);
if (ret) {
DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
- goto out_ggtt;
+ goto out_gvt;
}
ret = i915_kick_out_vgacon(dev_priv);
if (ret) {
DRM_ERROR("failed to remove conflicting VGA console\n");
- goto out_ggtt;
+ goto out_gvt;
}
pci_set_master(dev->pdev);
@@ -1267,7 +1272,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
if (ret) {
DRM_ERROR("failed to set DMA mask\n");
- goto out_ggtt;
+ goto out_gvt;
}
}
@@ -1297,7 +1302,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
aperture_size);
if (!ggtt->mappable) {
ret = -EIO;
- goto out_ggtt;
+ goto out_gvt;
}
ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
@@ -1330,6 +1335,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
return 0;
+out_gvt:
+ intel_gvt_cleanup(dev_priv);
out_ggtt:
i915_ggtt_cleanup_hw(dev);
@@ -1488,6 +1495,8 @@ int i915_driver_unload(struct drm_device *dev)
intel_fbdev_fini(dev);
+ intel_gvt_cleanup(dev_priv);
+
ret = i915_gem_suspend(dev);
if (ret) {
DRM_ERROR("failed to idle hardware: %d\n", ret);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72f0b02..7d0b8d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1703,6 +1703,10 @@ struct i915_workarounds {
u32 hw_whitelist_count[I915_NUM_ENGINES];
};
+struct i915_gvt {
+ void *gvt;
+};
+
struct i915_virtual_gpu {
bool active;
};
@@ -1742,6 +1746,8 @@ struct drm_i915_private {
struct i915_virtual_gpu vgpu;
+ struct i915_gvt gvt;
+
struct intel_guc guc;
struct intel_csr csr;
@@ -2868,6 +2874,12 @@ void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
+
+static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
+{
+ return dev_priv->gvt.gvt ? true : false;
+}
+
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
{
return dev_priv->vgpu.active;
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
new file mode 100644
index 0000000..815cc9f
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "i915_drv.h"
+#include "intel_gvt.h"
+
+/**
+ * DOC: Intel GVT-g host support
+ *
+ * Intel GVT-g is a graphics virtualization technology which shares the
+ * GPU among multiple virtual machines on a time-sharing basis. Each
+ * virtual machine is presented a virtual GPU (vGPU), which has equivalent
+ * features as the underlying physical GPU (pGPU), so i915 driver can run
+ * seamlessly in a virtual machine. This file provides the englightments
+ * of GVT and the necessary components used by GVT in i915 driver.
+ */
+
+struct gvt_kernel_params gvt_kparams = {
+ .enable = false,
+};
+
+/* i915.gvt_enable */
+module_param_named(gvt_enable, gvt_kparams.enable, bool, 0600);
+MODULE_PARM_DESC(gvt_enable, "Enable Intel GVT-g host support");
+
+static bool is_supported_device(struct drm_i915_private *dev_priv)
+{
+ if (IS_BROADWELL(dev_priv))
+ return true;
+ return false;
+}
+
+/**
+ * intel_gvt_init - initialize GVT components
+ * @dev_priv: drm i915 private data
+ *
+ * This function is called at the initialization stage to initialize the
+ * GVT components.
+ */
+int intel_gvt_init(struct drm_i915_private *dev_priv)
+{
+ void *device;
+
+ if (!gvt_kparams.enable) {
+ DRM_DEBUG_DRIVER("GVT-g is disabled by kernel params\n");
+ return 0;
+ }
+
+ if (!is_supported_device(dev_priv)) {
+ DRM_DEBUG_DRIVER("Unsupported device. GVT-g is disabled\n");
+ return 0;
+ }
+
+ device = intel_gvt_create_device(dev_priv);
+ if (IS_ERR(device)) {
+ DRM_DEBUG_DRIVER("GVT-g is disabled\n");
+ return 0;
+ }
+
+ dev_priv->gvt.gvt = device;
+ return 0;
+}
+
+/**
+ * intel_gvt_cleanup - cleanup GVT components when i915 driver is unloading
+ * @dev_priv: drm i915 private *
+ *
+ * This function is called at the i915 driver unloading stage, to shutdown
+ * GVT components and release the related resources.
+ */
+void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
+{
+ if (!intel_gvt_active(dev_priv))
+ return;
+
+ intel_gvt_destroy_device(dev_priv->gvt.gvt);
+ dev_priv->gvt.gvt = NULL;
+}
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
new file mode 100644
index 0000000..8079dfd
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _INTEL_GVT_H_
+#define _INTEL_GVT_H_
+
+#ifdef CONFIG_DRM_I915_GVT
+
+#include <drm/i915_gvt.h>
+
+struct gvt_kernel_params {
+ bool enable;
+};
+
+extern struct gvt_kernel_params gvt_kparams;
+
+extern int intel_gvt_init(struct drm_i915_private *dev_priv);
+extern void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
+#else
+static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
+{
+ return 0;
+}
+static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
+{
+}
+#endif
+
+#endif /* _INTEL_GVT_H_ */
diff --git a/include/drm/i915_gvt.h b/include/drm/i915_gvt.h
new file mode 100644
index 0000000..4ed8b88
--- /dev/null
+++ b/include/drm/i915_gvt.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _I915_GVT_H
+#define _I915_GVT_H
+
+extern void *intel_gvt_create_device(void *dev_priv);
+extern void intel_gvt_destroy_device(void *gvt);
+
+#endif /* _I915_GVT_H */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
` (2 preceding siblings ...)
2016-05-17 8:19 ` [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g Zhi Wang
@ 2016-05-17 8:19 ` Zhi Wang
2016-05-20 12:00 ` Chris Wilson
2016-05-17 8:19 ` [PATCH 5/9] drm/i915: Make ring buffer size configurable Zhi Wang
` (5 subsequent siblings)
9 siblings, 1 reply; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
From: Bing Niu <bing.niu@intel.com>
This patch introduces host graphics memory partition when GVT-g
is enabled.
Under GVT-g, i915 host driver only owned limited graphics resources,
others are managed by GVT-g resource allocator and kept for other vGPUs.
v3:
- Remove fence partition, will use i915 fence stealing in future.(Kevin)
- Santinize GVT host gm kernel parameters. (Joonas)
v2:
- Address all coding-style comments from Joonas previously.
- Fix errors and warnning reported by checkpatch.pl. (Joonas)
- Move the graphs into the header files. (Daniel)
Signed-off-by: Bing Niu <bing.niu@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 22 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_vgpu.c | 21 +++++++++++++++-----
drivers/gpu/drm/i915/intel_gvt.c | 42 ++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_gvt.h | 2 ++
4 files changed, 82 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d0b8d3..ea04352 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1703,8 +1703,30 @@ struct i915_workarounds {
u32 hw_whitelist_count[I915_NUM_ENGINES];
};
+/*
+ * Under GVT-g, i915 host driver only owned limited graphics resources,
+ * others are managed by GVT-g resource allocator and kept for other vGPUs.
+ *
+ * For graphics memory space partition, a typical layout looks like:
+ *
+ * +-------+-----------------------+------+-----------------------+
+ * |* Host | *GVT-g Resource |* Host| *GVT-g Resource |
+ * | Owned | Allocator Managed | Owned| Allocator Managed |
+ * | | | | |
+ * +---------------+-------+----------------------+-------+-------+
+ * | | | | | | | | |
+ * | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 |
+ * | | | | | | | | |
+ * +-------+-------+-------+--------------+-------+-------+-------+
+ * | Aperture | Hidden |
+ * +-------------------------------+------------------------------+
+ * | GGTT memory space |
+ * +--------------------------------------------------------------+
+ */
struct i915_gvt {
void *gvt;
+ u64 low_gm_size;
+ u64 high_gm_size;
};
struct i915_virtual_gpu {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 5312816..9382f04 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -189,13 +189,24 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
unsigned long unmappable_base, unmappable_size, unmappable_end;
int ret;
- if (!intel_vgpu_active(dev_priv))
+ if (!intel_vgpu_active(dev_priv) && !intel_gvt_active(dev_priv))
return 0;
- mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
- mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
- unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
- unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
+ if (intel_gvt_active(dev_priv)) {
+ mappable_base = 0;
+ mappable_size = dev_priv->gvt.low_gm_size;
+ unmappable_base = dev_priv->ggtt.mappable_end;
+ unmappable_size = dev_priv->gvt.high_gm_size;
+ } else if (intel_vgpu_active(dev_priv)) {
+ mappable_base = I915_READ(
+ vgtif_reg(avail_rs.mappable_gmadr.base));
+ mappable_size = I915_READ(
+ vgtif_reg(avail_rs.mappable_gmadr.size));
+ unmappable_base = I915_READ(
+ vgtif_reg(avail_rs.nonmappable_gmadr.base));
+ unmappable_size = I915_READ(
+ vgtif_reg(avail_rs.nonmappable_gmadr.size));
+ }
mappable_end = mappable_base + mappable_size;
unmappable_end = unmappable_base + unmappable_size;
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 815cc9f..005f156 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -43,6 +43,46 @@ struct gvt_kernel_params gvt_kparams = {
module_param_named(gvt_enable, gvt_kparams.enable, bool, 0600);
MODULE_PARM_DESC(gvt_enable, "Enable Intel GVT-g host support");
+/* i915.gvt_low_gm_size */
+module_param_named(gvt_low_gm_size, gvt_kparams.low_gm_size, charp, 0600);
+MODULE_PARM_DESC(gvt_low_gm_size, "GVT low graphics memory size");
+
+/* i915.gvt_high_gm_size */
+module_param_named(gvt_high_gm_size, gvt_kparams.high_gm_size, charp, 0600);
+MODULE_PARM_DESC(gvt_high_gm_size, "GVT high graphics memory size");
+
+#define KB(x) ((x) * 1024)
+#define MB(x) (KB(x) * 1024)
+
+#define MAX_GVT_LOW_GM_SIZE MB(96)
+#define MAX_GVT_HIGH_GM_SIZE MB(384)
+
+static void sanitize_gm_size(struct drm_i915_private *dev_priv)
+{
+ u64 low_gm_size, high_gm_size;
+
+ low_gm_size = high_gm_size = 0;
+
+ /* Try to parse kernel parameter first */
+ if (gvt_kparams.low_gm_size)
+ low_gm_size = memparse(gvt_kparams.low_gm_size, NULL);
+
+ if (gvt_kparams.high_gm_size)
+ high_gm_size = memparse(gvt_kparams.high_gm_size, NULL);
+
+ if (!low_gm_size || low_gm_size > MAX_GVT_LOW_GM_SIZE)
+ low_gm_size = MAX_GVT_LOW_GM_SIZE;
+
+ if (!high_gm_size || high_gm_size > MAX_GVT_HIGH_GM_SIZE)
+ high_gm_size = MAX_GVT_HIGH_GM_SIZE;
+
+ dev_priv->gvt.low_gm_size = low_gm_size;
+ dev_priv->gvt.high_gm_size = high_gm_size;
+
+ DRM_DEBUG_DRIVER("GVT low graphics memory size: %llx\n", low_gm_size);
+ DRM_DEBUG_DRIVER("GVT high graphics memory size: %llx\n", high_gm_size);
+}
+
static bool is_supported_device(struct drm_i915_private *dev_priv)
{
if (IS_BROADWELL(dev_priv))
@@ -71,6 +111,8 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return 0;
}
+ sanitize_gm_size(dev_priv);
+
device = intel_gvt_create_device(dev_priv);
if (IS_ERR(device)) {
DRM_DEBUG_DRIVER("GVT-g is disabled\n");
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index 8079dfd..bfceee1 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -30,6 +30,8 @@
struct gvt_kernel_params {
bool enable;
+ char *low_gm_size;
+ char *high_gm_size;
};
extern struct gvt_kernel_params gvt_kparams;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 5/9] drm/i915: Make ring buffer size configurable
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
` (3 preceding siblings ...)
2016-05-17 8:19 ` [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g Zhi Wang
@ 2016-05-17 8:19 ` Zhi Wang
2016-05-20 12:01 ` Chris Wilson
2016-05-17 8:19 ` [PATCH 6/9] drm/i915: Generate addressing mode bit from flag in context Zhi Wang
` (4 subsequent siblings)
9 siblings, 1 reply; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
This patch introduces an option for configuring ring buffer size during
context creation. If no ring buffer size is specified, the default size
(4 * PAGE_SIZE) will be used.
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea04352..cc83f2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -883,6 +883,7 @@ struct intel_context {
uint32_t *lrc_reg_state;
bool initialised;
} engine[I915_NUM_ENGINES];
+ u32 ring_buffer_size;
struct list_head link;
};
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index db10c96..d52c806 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2495,7 +2495,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
struct intel_engine_cs *engine)
{
struct drm_i915_gem_object *ctx_obj;
- uint32_t context_size;
+ uint32_t context_size, ring_buffer_size;
struct intel_ringbuffer *ringbuf;
int ret;
@@ -2513,7 +2513,11 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
return PTR_ERR(ctx_obj);
}
- ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
+ ring_buffer_size = ctx->ring_buffer_size;
+ if (!ring_buffer_size)
+ ring_buffer_size = 4 * PAGE_SIZE;
+
+ ringbuf = intel_engine_create_ringbuffer(engine, ring_buffer_size);
if (IS_ERR(ringbuf)) {
ret = PTR_ERR(ringbuf);
goto error_deref_obj;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 6/9] drm/i915: Generate addressing mode bit from flag in context.
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
` (4 preceding siblings ...)
2016-05-17 8:19 ` [PATCH 5/9] drm/i915: Make ring buffer size configurable Zhi Wang
@ 2016-05-17 8:19 ` Zhi Wang
2016-05-20 12:03 ` Chris Wilson
2016-05-17 8:19 ` [PATCH 7/9] drm/i915: Introduce execlist context status change notification Zhi Wang
` (3 subsequent siblings)
9 siblings, 1 reply; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
Previously the addressing mode bit in context descriptor is generated from
context PPGTT. As we allow context could be used without PPGTT, and we
still need to know the addressing mode during context submission, a flag
is introduced.
And the addressing mode bit will be generated from this flag.
v5:
- Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
drivers/gpu/drm/i915/intel_lrc.c | 9 +++++----
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cc83f2d..91f69e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -884,6 +884,7 @@ struct intel_context {
bool initialised;
} engine[I915_NUM_ENGINES];
u32 ring_buffer_size;
+ bool use_48bit_addressing_mode;
struct list_head link;
};
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 2aedd18..057e2fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -339,6 +339,8 @@ i915_gem_create_context(struct drm_device *dev,
ctx->ppgtt = ppgtt;
}
+ ctx->use_48bit_addressing_mode = USES_FULL_48BIT_PPGTT(dev_priv);
+
trace_i915_context_create(ctx);
return ctx;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d52c806..d97623f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -214,7 +214,8 @@ enum {
LEGACY_64B_CONTEXT
};
#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
-#define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
+#define GEN8_CTX_ADDRESSING_MODE(ctx) \
+ (ctx->use_48bit_addressing_mode ? \
LEGACY_64B_CONTEXT :\
LEGACY_32B_CONTEXT)
enum {
@@ -281,8 +282,6 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
(engine->id == VCS || engine->id == VCS2);
engine->ctx_desc_template = GEN8_CTX_VALID;
- engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
- GEN8_CTX_ADDRESSING_MODE_SHIFT;
if (IS_GEN8(dev_priv))
engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
@@ -325,8 +324,10 @@ intel_lr_context_descriptor_update(struct intel_context *ctx,
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
desc = engine->ctx_desc_template; /* bits 0-11 */
+ desc |= GEN8_CTX_ADDRESSING_MODE(ctx) << /* bits 3-4 */
+ GEN8_CTX_ADDRESSING_MODE_SHIFT;
desc |= ctx->engine[engine->id].lrc_vma->node.start + /* bits 12-31 */
- LRC_PPHWSP_PN * PAGE_SIZE;
+ LRC_PPHWSP_PN * PAGE_SIZE;
desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
ctx->engine[engine->id].lrc_desc = desc;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 7/9] drm/i915: Introduce execlist context status change notification
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
` (5 preceding siblings ...)
2016-05-17 8:19 ` [PATCH 6/9] drm/i915: Generate addressing mode bit from flag in context Zhi Wang
@ 2016-05-17 8:19 ` Zhi Wang
2016-05-17 10:51 ` Tvrtko Ursulin
2016-05-20 11:16 ` Chris Wilson
2016-05-17 8:19 ` [PATCH 8/9] drm/i915: Support context single submission Zhi Wang
` (2 subsequent siblings)
9 siblings, 2 replies; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
This patch introduces an approach to track the execlist context status
change.
GVT-g uses GVT context as the "shadow context". The content inside GVT
context will be copied back to guest after the context is idle. So GVT-g
has to know the status of the execlist context.
This function is configurable in the context creation service. Currently,
Only GVT-g will create the "status-change-notification" enabled GEM
context.
v5:
- Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko)
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
drivers/gpu/drm/i915/intel_lrc.c | 30 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_lrc.h | 7 +++++++
3 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91f69e5..9688006 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -882,9 +882,15 @@ struct intel_context {
u64 lrc_desc;
uint32_t *lrc_reg_state;
bool initialised;
+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
+ struct atomic_notifier_head status_notifier_head;
+#endif
} engine[I915_NUM_ENGINES];
u32 ring_buffer_size;
bool use_48bit_addressing_mode;
+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
+ bool enable_status_change_notification;
+#endif
struct list_head link;
};
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d97623f..9069836 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -415,6 +415,20 @@ static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
spin_unlock_irq(&dev_priv->uncore.lock);
}
+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
+static inline void execlists_context_status_change(
+ struct drm_i915_gem_request *req,
+ unsigned long status)
+{
+ if (!req->ctx->enable_status_change_notification)
+ return;
+
+ atomic_notifier_call_chain(
+ &req->ctx->engine[req->engine->id].status_notifier_head,
+ status, req);
+}
+#endif
+
static void execlists_context_unqueue(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
@@ -450,6 +464,13 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
if (unlikely(!req0))
return;
+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
+ execlists_context_status_change(req0, CONTEXT_SCHEDULE_IN);
+
+ if (req1)
+ execlists_context_status_change(req1, CONTEXT_SCHEDULE_IN);
+#endif
+
if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
/*
* WaIdleLiteRestore: make sure we never cause a lite restore
@@ -488,6 +509,10 @@ execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id)
if (--head_req->elsp_submitted > 0)
return 0;
+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
+ execlists_context_status_change(head_req, CONTEXT_SCHEDULE_OUT);
+#endif
+
list_del(&head_req->execlist_link);
i915_gem_request_unreference(head_req);
@@ -2534,6 +2559,11 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
ctx->engine[engine->id].state = ctx_obj;
ctx->engine[engine->id].initialised = engine->init_context == NULL;
+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
+ if (ctx->enable_status_change_notification)
+ ATOMIC_INIT_NOTIFIER_HEAD(
+ &ctx->engine[engine->id].status_notifier_head);
+#endif
return 0;
error_ringbuf:
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 1afba03..99f84c9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -57,6 +57,13 @@
#define GEN8_CSB_READ_PTR(csb_status) \
(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
+enum {
+ CONTEXT_SCHEDULE_IN = 0,
+ CONTEXT_SCHEDULE_OUT,
+};
+#endif
+
/* Logical Rings */
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 8/9] drm/i915: Support context single submission
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
` (6 preceding siblings ...)
2016-05-17 8:19 ` [PATCH 7/9] drm/i915: Introduce execlist context status change notification Zhi Wang
@ 2016-05-17 8:19 ` Zhi Wang
2016-05-20 12:04 ` Chris Wilson
2016-05-17 8:19 ` [PATCH 9/9] drm/i915: Introduce GVT context creation API Zhi Wang
2016-05-17 8:56 ` ✗ Ro.CI.BAT: failure for Introduce the implementation of GVT context (rev2) Patchwork
9 siblings, 1 reply; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
This patch introduces the support of context signle submission. As GVT
context may come from different guests, which requires different
configuration of render registers. It can't be combined in a dual ELSP
submission combo.
We make this function as a context feature in context creation service.
Only GVT-g will create this kinds of GEM context currently.
v5:
- Only compile this feature when CONFIG_DRM_I915_GVT=y. (Tvrtko)
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 15 +++++++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9688006..b8f1e9a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -890,8 +890,8 @@ struct intel_context {
bool use_48bit_addressing_mode;
#if IS_ENABLED(CONFIG_DRM_I915_GVT)
bool enable_status_change_notification;
+ bool single_submission;
#endif
-
struct list_head link;
};
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9069836..8d1a9c2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -455,6 +455,21 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
i915_gem_request_unreference(req0);
req0 = cursor;
} else {
+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
+
+ /*
+ * req0 (after merged) ctx requires single submission,
+ * stop picking
+ */
+ if (req0->ctx->single_submission)
+ break;
+ /*
+ * req0 ctx doesn't require single submission, but
+ * next req ctx requires, stop picking req1
+ */
+ if (cursor->ctx->single_submission)
+ break;
+#endif
req1 = cursor;
WARN_ON(req1->elsp_submitted);
break;
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 9/9] drm/i915: Introduce GVT context creation API
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
` (7 preceding siblings ...)
2016-05-17 8:19 ` [PATCH 8/9] drm/i915: Support context single submission Zhi Wang
@ 2016-05-17 8:19 ` Zhi Wang
2016-05-20 12:06 ` Chris Wilson
2016-05-17 8:56 ` ✗ Ro.CI.BAT: failure for Introduce the implementation of GVT context (rev2) Patchwork
9 siblings, 1 reply; 30+ messages in thread
From: Zhi Wang @ 2016-05-17 8:19 UTC (permalink / raw)
To: intel-gfx, tvrtko.ursulin, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
GVT workload scheduler needs special host LRC contexts, the so called
"shadow LRC context" to submit guest workload to host i915. During the
guest workload submission, GVT fills the shadow LRC context with the
content of guest LRC context: engine context is copied without changes,
ring context is mostly owned by host i915.
The GVT-g workload scheduler flow:
+-----------+ +-----------+
| GVT Guest | | GVT Guest |
+-+-----^---+ +-+-----^---+
| | | |
| | GVT-g | | GVT-g
vELSP write| | emulates vELSP write| | emulates
| | Execlist/CSB | | Execlist/CSB
| | Status | | Status
| | | |
+------v-----+-------------------------v-----+---------+
| GVT Virtual Execlist Submission |
+------+-------------------------------+---------------+
| |
| Per-VM/Ring Workoad Q | Per-VM/Ring Workload Q
+---------------------+--+ +------------------------+
+---v--------+ ^ +---v--------+
|GVT Workload|... | |GVT Workload|...
+------------+ | +------------+
|
| Pick Workload from Q
+--------------------+---------------------------------+
| GVT Workload Scheduler |
+--------------------+---------------------------------+
| * Shadow guest LRC context
+------v------+ * Shadow guest ring buffer
| GVT Context | * Scan/Patch guest RB instructions
+------+------+
|
v
Host i915 GEM Submission
v5:
- Only compile this feature when CONFIG_DRM_I915_GVT is enabled.
- Rebase the code into new repo.
- Add a comment about the ring buffer size.
v2:
Mostly based on Daniel's idea. Call the refactored core logic of GEM
context creation service and LRC context creation service to create the GVT
context.
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b8f1e9a..7e5a506 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3398,6 +3398,7 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
void i915_gem_context_free(struct kref *ctx_ref);
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
+struct intel_context *i915_gem_create_gvt_context(struct drm_device *dev);
static inline void i915_gem_context_reference(struct intel_context *ctx)
{
kref_get(&ctx->ref);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 057e2fe..a69bb86 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -354,6 +354,37 @@ err_destroy:
return ERR_PTR(ret);
}
+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
+/**
+ * i915_gem_create_gvt_context - create a GVT GEM context
+ * @dev: drm device *
+ *
+ * This function is used to create a GVT specific GEM context.
+ *
+ * Returns:
+ * pointer to intel_context on success, NULL if failed
+ *
+ */
+struct intel_context *
+i915_gem_create_gvt_context(struct drm_device *dev)
+{
+ struct intel_context *ctx;
+
+ mutex_lock(&dev->struct_mutex);
+
+ ctx = i915_gem_create_context(dev, NULL);
+ if (IS_ERR(ctx))
+ goto out;
+
+ ctx->enable_status_change_notification = true;
+ ctx->ring_buffer_size = 512 * PAGE_SIZE; /* Max ring buffer size */
+ ctx->single_submission = true;
+out:
+ mutex_unlock(&dev->struct_mutex);
+ return ctx;
+}
+#endif
+
static void i915_gem_context_unpin(struct intel_context *ctx,
struct intel_engine_cs *engine)
{
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* ✗ Ro.CI.BAT: failure for Introduce the implementation of GVT context (rev2)
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
` (8 preceding siblings ...)
2016-05-17 8:19 ` [PATCH 9/9] drm/i915: Introduce GVT context creation API Zhi Wang
@ 2016-05-17 8:56 ` Patchwork
9 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2016-05-17 8:56 UTC (permalink / raw)
To: Wang, Zhi A; +Cc: intel-gfx
== Series Details ==
Series: Introduce the implementation of GVT context (rev2)
URL : https://patchwork.freedesktop.org/series/7208/
State : failure
== Summary ==
Series 7208v2 Introduce the implementation of GVT context
http://patchwork.freedesktop.org/api/1.0/series/7208/revisions/2/mbox
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (ro-byt-n2820)
Test kms_sink_crc_basic:
skip -> PASS (ro-skl-i7-6700hq)
fi-byt-n2820 total:218 pass:174 dwarn:0 dfail:0 fail:3 skip:41
fi-hsw-i7-4770k total:219 pass:198 dwarn:0 dfail:0 fail:0 skip:21
fi-hsw-i7-4770r total:219 pass:193 dwarn:0 dfail:0 fail:0 skip:26
fi-skl-i5-6260u total:219 pass:207 dwarn:0 dfail:0 fail:0 skip:12
fi-skl-i7-6700k total:219 pass:191 dwarn:0 dfail:0 fail:0 skip:28
fi-snb-i7-2600 total:37 pass:27 dwarn:0 dfail:0 fail:0 skip:9
ro-bdw-i5-5250u total:219 pass:181 dwarn:0 dfail:0 fail:0 skip:38
ro-bdw-i7-5557U total:219 pass:206 dwarn:0 dfail:0 fail:0 skip:13
ro-bdw-i7-5600u total:219 pass:187 dwarn:0 dfail:0 fail:0 skip:32
ro-bsw-n3050 total:219 pass:175 dwarn:0 dfail:0 fail:2 skip:42
ro-byt-n2820 total:218 pass:173 dwarn:0 dfail:0 fail:4 skip:41
ro-hsw-i3-4010u total:218 pass:193 dwarn:0 dfail:0 fail:0 skip:25
ro-hsw-i7-4770r total:219 pass:194 dwarn:0 dfail:0 fail:0 skip:25
ro-ilk-i7-620lm total:219 pass:151 dwarn:0 dfail:0 fail:1 skip:67
ro-ilk1-i5-650 total:214 pass:152 dwarn:0 dfail:0 fail:1 skip:61
ro-ivb-i7-3770 total:219 pass:183 dwarn:0 dfail:0 fail:0 skip:36
ro-ivb2-i7-3770 total:219 pass:187 dwarn:0 dfail:0 fail:0 skip:32
ro-skl-i7-6700hq total:214 pass:190 dwarn:0 dfail:0 fail:0 skip:24
ro-snb-i7-2620M total:219 pass:177 dwarn:0 dfail:0 fail:1 skip:41
fi-bdw-i7-5557u failed to connect after reboot
fi-bsw-n3050 failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_914/
e76bda7 drm-intel-nightly: 2016y-05m-17d-07h-12m-14s UTC integration manifest
7d1ad2f drm/i915: Introduce GVT context creation API
099ab53 drm/i915: Support context single submission
a6a4b2f drm/i915: Introduce execlist context status change notification
05ae1a3 drm/i915: Generate addressing mode bit from flag in context.
2d0e08a drm/i915: Make ring buffer size configurable
85391c9 drm/i915: Introduce host graphics memory partition for GVT-g
107c22f drm/i915: gvt: Introduce the basic architecture of GVT-g
38aeac2 drm/i915/gvt: Fold vGPU active check into inner functions
15f8497 drm/i915: Factor out i915_pvinfo.h
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 7/9] drm/i915: Introduce execlist context status change notification
2016-05-17 8:19 ` [PATCH 7/9] drm/i915: Introduce execlist context status change notification Zhi Wang
@ 2016-05-17 10:51 ` Tvrtko Ursulin
2016-05-17 15:18 ` Wang, Zhi A
2016-05-20 11:16 ` Chris Wilson
1 sibling, 1 reply; 30+ messages in thread
From: Tvrtko Ursulin @ 2016-05-17 10:51 UTC (permalink / raw)
To: Zhi Wang, intel-gfx, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
Hi,
On 17/05/16 09:19, Zhi Wang wrote:
> This patch introduces an approach to track the execlist context status
> change.
>
> GVT-g uses GVT context as the "shadow context". The content inside GVT
> context will be copied back to guest after the context is idle. So GVT-g
> has to know the status of the execlist context.
>
> This function is configurable in the context creation service. Currently,
> Only GVT-g will create the "status-change-notification" enabled GEM
> context.
>
> v5:
>
> - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko)
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
> drivers/gpu/drm/i915/intel_lrc.c | 30 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_lrc.h | 7 +++++++
> 3 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 91f69e5..9688006 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -882,9 +882,15 @@ struct intel_context {
> u64 lrc_desc;
> uint32_t *lrc_reg_state;
> bool initialised;
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + struct atomic_notifier_head status_notifier_head;
> +#endif
> } engine[I915_NUM_ENGINES];
> u32 ring_buffer_size;
> bool use_48bit_addressing_mode;
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + bool enable_status_change_notification;
> +#endif
>
> struct list_head link;
> };
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d97623f..9069836 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -415,6 +415,20 @@ static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
> spin_unlock_irq(&dev_priv->uncore.lock);
> }
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> +static inline void execlists_context_status_change(
> + struct drm_i915_gem_request *req,
> + unsigned long status)
> +{
> + if (!req->ctx->enable_status_change_notification)
> + return;
> +
> + atomic_notifier_call_chain(
> + &req->ctx->engine[req->engine->id].status_notifier_head,
> + status, req);
> +}
I recommend the usual:
#else
static inline void execlists_context_status_change(
struct drm_i915_gem_request *req,
unsigned long status)
{
}
And then you don't have to have many #ifdefs scattered around.
> +#endif
> +
> static void execlists_context_unqueue(struct intel_engine_cs *engine)
> {
> struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
> @@ -450,6 +464,13 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
> if (unlikely(!req0))
> return;
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + execlists_context_status_change(req0, CONTEXT_SCHEDULE_IN);
> +
> + if (req1)
> + execlists_context_status_change(req1, CONTEXT_SCHEDULE_IN);
> +#endif
> +
> if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
> /*
> * WaIdleLiteRestore: make sure we never cause a lite restore
> @@ -488,6 +509,10 @@ execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id)
> if (--head_req->elsp_submitted > 0)
> return 0;
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + execlists_context_status_change(head_req, CONTEXT_SCHEDULE_OUT);
> +#endif
> +
> list_del(&head_req->execlist_link);
> i915_gem_request_unreference(head_req);
>
> @@ -2534,6 +2559,11 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
> ctx->engine[engine->id].state = ctx_obj;
> ctx->engine[engine->id].initialised = engine->init_context == NULL;
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + if (ctx->enable_status_change_notification)
> + ATOMIC_INIT_NOTIFIER_HEAD(
> + &ctx->engine[engine->id].status_notifier_head);
> +#endif
> return 0;
>
> error_ringbuf:
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 1afba03..99f84c9 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -57,6 +57,13 @@
> #define GEN8_CSB_READ_PTR(csb_status) \
> (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> +enum {
> + CONTEXT_SCHEDULE_IN = 0,
> + CONTEXT_SCHEDULE_OUT,
> +};
> +#endif
> +
> /* Logical Rings */
> int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
> int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 7/9] drm/i915: Introduce execlist context status change notification
2016-05-17 10:51 ` Tvrtko Ursulin
@ 2016-05-17 15:18 ` Wang, Zhi A
0 siblings, 0 replies; 30+ messages in thread
From: Wang, Zhi A @ 2016-05-17 15:18 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, chris@chris-wilson.co.uk,
Tian, Kevin, Lv, Zhiyuan
Yes. Sure will do that. :) Thanks for the comments. How about other patches? :)
-----Original Message-----
From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com]
Sent: Tuesday, May 17, 2016 1:52 PM
To: Wang, Zhi A <zhi.a.wang@intel.com>; intel-gfx@lists.freedesktop.org; joonas.lahtinen@linux.intel.com; chris@chris-wilson.co.uk; Tian, Kevin <kevin.tian@intel.com>; Lv, Zhiyuan <zhiyuan.lv@intel.com>
Subject: Re: [PATCH 7/9] drm/i915: Introduce execlist context status change notification
Hi,
On 17/05/16 09:19, Zhi Wang wrote:
> This patch introduces an approach to track the execlist context status
> change.
>
> GVT-g uses GVT context as the "shadow context". The content inside GVT
> context will be copied back to guest after the context is idle. So
> GVT-g has to know the status of the execlist context.
>
> This function is configurable in the context creation service.
> Currently, Only GVT-g will create the "status-change-notification"
> enabled GEM context.
>
> v5:
>
> - Only compile this feature when CONFIG_DRM_I915_GVT is
> enabled.(Tvrtko)
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
> drivers/gpu/drm/i915/intel_lrc.c | 30 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_lrc.h | 7 +++++++
> 3 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 91f69e5..9688006 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -882,9 +882,15 @@ struct intel_context {
> u64 lrc_desc;
> uint32_t *lrc_reg_state;
> bool initialised;
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + struct atomic_notifier_head status_notifier_head; #endif
> } engine[I915_NUM_ENGINES];
> u32 ring_buffer_size;
> bool use_48bit_addressing_mode;
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + bool enable_status_change_notification;
> +#endif
>
> struct list_head link;
> };
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index d97623f..9069836 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -415,6 +415,20 @@ static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
> spin_unlock_irq(&dev_priv->uncore.lock);
> }
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> +static inline void execlists_context_status_change(
> + struct drm_i915_gem_request *req,
> + unsigned long status)
> +{
> + if (!req->ctx->enable_status_change_notification)
> + return;
> +
> + atomic_notifier_call_chain(
> + &req->ctx->engine[req->engine->id].status_notifier_head,
> + status, req);
> +}
I recommend the usual:
#else
static inline void execlists_context_status_change(
struct drm_i915_gem_request *req,
unsigned long status)
{
}
And then you don't have to have many #ifdefs scattered around.
> +#endif
> +
> static void execlists_context_unqueue(struct intel_engine_cs *engine)
> {
> struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; @@ -450,6
> +464,13 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
> if (unlikely(!req0))
> return;
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + execlists_context_status_change(req0, CONTEXT_SCHEDULE_IN);
> +
> + if (req1)
> + execlists_context_status_change(req1, CONTEXT_SCHEDULE_IN); #endif
> +
> if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
> /*
> * WaIdleLiteRestore: make sure we never cause a lite restore @@
> -488,6 +509,10 @@ execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id)
> if (--head_req->elsp_submitted > 0)
> return 0;
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + execlists_context_status_change(head_req, CONTEXT_SCHEDULE_OUT);
> +#endif
> +
> list_del(&head_req->execlist_link);
> i915_gem_request_unreference(head_req);
>
> @@ -2534,6 +2559,11 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
> ctx->engine[engine->id].state = ctx_obj;
> ctx->engine[engine->id].initialised = engine->init_context == NULL;
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + if (ctx->enable_status_change_notification)
> + ATOMIC_INIT_NOTIFIER_HEAD(
> + &ctx->engine[engine->id].status_notifier_head);
> +#endif
> return 0;
>
> error_ringbuf:
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h
> b/drivers/gpu/drm/i915/intel_lrc.h
> index 1afba03..99f84c9 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -57,6 +57,13 @@
> #define GEN8_CSB_READ_PTR(csb_status) \
> (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> +enum {
> + CONTEXT_SCHEDULE_IN = 0,
> + CONTEXT_SCHEDULE_OUT,
> +};
> +#endif
> +
> /* Logical Rings */
> int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
> int intel_logical_ring_reserve_space(struct drm_i915_gem_request
> *request);
>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/9] drm/i915/gvt: Fold vGPU active check into inner functions
2016-05-17 8:19 ` [PATCH 2/9] drm/i915/gvt: Fold vGPU active check into inner functions Zhi Wang
@ 2016-05-18 10:54 ` Tvrtko Ursulin
2016-05-20 10:27 ` Wang, Zhi A
0 siblings, 1 reply; 30+ messages in thread
From: Tvrtko Ursulin @ 2016-05-18 10:54 UTC (permalink / raw)
To: Zhi Wang, intel-gfx, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
On 17/05/16 09:19, Zhi Wang wrote:
> v5:
> - Let functions take struct drm_i915_private *. (Tvrtko)
>
> - Fold vGPU related active check into the inner functions. (Kevin)
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++++-------
> drivers/gpu/drm/i915/i915_vgpu.c | 13 +++++++++----
> drivers/gpu/drm/i915/i915_vgpu.h | 4 ++--
> 3 files changed, 15 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7eab619..820b59e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2737,11 +2737,9 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
> i915_address_space_init(&ggtt->base, dev_priv);
> ggtt->base.total += PAGE_SIZE;
>
> - if (intel_vgpu_active(dev_priv)) {
> - ret = intel_vgt_balloon(dev);
> - if (ret)
> - return ret;
> - }
> + ret = intel_vgt_balloon(dev_priv);
> + if (ret)
> + return ret;
>
> if (!HAS_LLC(dev))
> ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
> @@ -2841,8 +2839,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
> i915_gem_cleanup_stolen(dev);
>
> if (drm_mm_initialized(&ggtt->base.mm)) {
> - if (intel_vgpu_active(dev_priv))
> - intel_vgt_deballoon();
> + intel_vgt_deballoon(dev_priv);
>
> drm_mm_takedown(&ggtt->base.mm);
> list_del(&ggtt->base.global_link);
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index d5a7a5e..5312816 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -101,10 +101,13 @@ static struct _balloon_info_ bl_info;
> * This function is called to deallocate the ballooned-out graphic memory, when
> * driver is unloaded or when ballooning fails.
> */
> -void intel_vgt_deballoon(void)
> +void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
> {
> int i;
>
> + if (!intel_vgpu_active(dev_priv))
> + return;
> +
> DRM_DEBUG("VGT deballoon.\n");
>
> for (i = 0; i < 4; i++) {
> @@ -177,9 +180,8 @@ static int vgt_balloon_space(struct drm_mm *mm,
> * Returns:
> * zero on success, non-zero if configuration invalid or ballooning failed
> */
> -int intel_vgt_balloon(struct drm_device *dev)
> +int intel_vgt_balloon(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> struct i915_ggtt *ggtt = &dev_priv->ggtt;
> unsigned long ggtt_end = ggtt->base.start + ggtt->base.total;
>
> @@ -187,6 +189,9 @@ int intel_vgt_balloon(struct drm_device *dev)
> unsigned long unmappable_base, unmappable_size, unmappable_end;
> int ret;
>
> + if (!intel_vgpu_active(dev_priv))
> + return 0;
> +
> mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
> mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
> unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
> @@ -258,6 +263,6 @@ int intel_vgt_balloon(struct drm_device *dev)
>
> err:
> DRM_ERROR("VGT balloon fail\n");
> - intel_vgt_deballoon();
> + intel_vgt_deballoon(dev_priv);
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 07e67d5..f8917c6 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -27,7 +27,7 @@
> #include "i915_pvinfo.h"
>
> extern void i915_check_vgpu(struct drm_i915_private *dev_priv);
> -extern int intel_vgt_balloon(struct drm_device *dev);
> -extern void intel_vgt_deballoon(void);
> +extern int intel_vgt_balloon(struct drm_i915_private *dev_priv);
> +extern void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
>
> #endif /* _I915_VGPU_H_ */
>
Looks clean to me.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g
2016-05-17 8:19 ` [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g Zhi Wang
@ 2016-05-18 11:22 ` Tvrtko Ursulin
2016-05-20 10:57 ` Wang, Zhi A
2016-05-20 11:49 ` Chris Wilson
1 sibling, 1 reply; 30+ messages in thread
From: Tvrtko Ursulin @ 2016-05-18 11:22 UTC (permalink / raw)
To: Zhi Wang, intel-gfx, joonas.lahtinen, chris, kevin.tian,
zhiyuan.lv
On 17/05/16 09:19, Zhi Wang wrote:
> This patch introduces the very basic framework of GVT-g device model,
> includes basic prototypes, definitions, initialization.
>
> v5:
> Take Tvrtko's comments:
> - Fix the misspelled words in Kconfg
> - Let functions take drm_i915_private * instead of struct drm_device *
> - Remove redundant prints/local varible initialization
>
> v3:
> Take Joonas' comments:
> - Change file name i915_gvt.* to intel_gvt.*
> - Move GVT kernel parameter into intel_gvt.c
> - Remove redundant debug macros
> - Change error handling style
> - Add introductions for some stub functions
> - Introduce drm/i915_gvt.h.
>
> Take Kevin's comments:
> - Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c
>
> v2:
> - Introduce i915_gvt.c.
> It's necessary to introduce the stubs between i915 driver and GVT-g host,
> as GVT-g components is configurable in kernel config. When disabled, the
> stubs here do nothing.
>
> Take Joonas' comments:
> - Replace boolean return value with int.
> - Replace customized info/warn/debug macros with DRM macros.
> - Document all non-static functions like i915.
> - Remove empty and unused functions.
> - Replace magic number with marcos.
> - Set GVT-g in kernel config to "n" by default.
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/Kconfig | 15 +++
> drivers/gpu/drm/i915/Makefile | 5 +
> drivers/gpu/drm/i915/gvt/Makefile | 5 +
> drivers/gpu/drm/i915/gvt/debug.h | 36 ++++++
> drivers/gpu/drm/i915/gvt/gvt.c | 205 +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/gvt/gvt.h | 84 ++++++++++++++
> drivers/gpu/drm/i915/gvt/hypercall.h | 38 +++++++
> drivers/gpu/drm/i915/gvt/mpt.h | 49 +++++++++
> drivers/gpu/drm/i915/i915_dma.c | 17 ++-
> drivers/gpu/drm/i915/i915_drv.h | 12 ++
> drivers/gpu/drm/i915/intel_gvt.c | 98 +++++++++++++++++
> drivers/gpu/drm/i915/intel_gvt.h | 49 +++++++++
> include/drm/i915_gvt.h | 31 ++++++
> 13 files changed, 640 insertions(+), 4 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gvt/Makefile
> create mode 100644 drivers/gpu/drm/i915/gvt/debug.h
> create mode 100644 drivers/gpu/drm/i915/gvt/gvt.c
> create mode 100644 drivers/gpu/drm/i915/gvt/gvt.h
> create mode 100644 drivers/gpu/drm/i915/gvt/hypercall.h
> create mode 100644 drivers/gpu/drm/i915/gvt/mpt.h
> create mode 100644 drivers/gpu/drm/i915/intel_gvt.c
> create mode 100644 drivers/gpu/drm/i915/intel_gvt.h
> create mode 100644 include/drm/i915_gvt.h
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index 29a32b1..feb56ee 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -57,6 +57,21 @@ config DRM_I915_USERPTR
>
> If in doubt, say "Y".
>
> +config DRM_I915_GVT
> + bool "Intel GVT-g host driver"
> + depends on DRM_I915
> + default n
> + help
> + Enabling GVT-g mediated graphics pass-through technique for Intel i915
> + based integrated graphics card. With GVT-g, it's possible to have one
> + integrated i915 device shared by multiple VMs. Performance critical
> + operations such as aperture accesses and ring buffer operations
> + are passed-through to VM, with a minimal set of conflicting resources
Maybe I am confused but to me this is not clear. If we have multiple VMs
sharing the GPU where performance critical operations are passed-through
to the *VM* ? Aren't they passed-through to the GPU/host/hypervisor or
something rather than the VM?
> + (e.g. display settings) mediated by GVT host driver. The benefit of GVT
> + is on both the performance, given that each VM could directly operate
> + its aperture space and submit commands like running on native, and
> + the feature completeness, given that a true GEN hardware is exposed.
> +
> menu "drm/i915 Debugging"
> depends on DRM_I915
> depends on EXPERT
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 63c4d2b..e48145b 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -103,6 +103,11 @@ i915-y += i915_vgpu.o
> # legacy horrors
> i915-y += i915_dma.o
>
> +ifeq ($(CONFIG_DRM_I915_GVT),y)
> +i915-y += intel_gvt.o
> +include $(src)/gvt/Makefile
> +endif
> +
> obj-$(CONFIG_DRM_I915) += i915.o
>
> CFLAGS_i915_trace_points.o := -I$(src)
> diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile
> new file mode 100644
> index 0000000..d0f21a6
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/Makefile
> @@ -0,0 +1,5 @@
> +GVT_DIR := gvt
> +GVT_SOURCE := gvt.o
> +
> +ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall
> +i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
> diff --git a/drivers/gpu/drm/i915/gvt/debug.h b/drivers/gpu/drm/i915/gvt/debug.h
> new file mode 100644
> index 0000000..5b067d2
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/debug.h
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef __GVT_DEBUG_H__
> +#define __GVT_DEBUG_H__
> +
> +#define gvt_info(fmt, args...) \
> + DRM_INFO("gvt: "fmt, ##args)
> +
> +#define gvt_err(fmt, args...) \
> + DRM_ERROR("gvt: "fmt, ##args)
> +
> +#define gvt_dbg_core(fmt, args...) \
> + DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
> new file mode 100644
> index 0000000..aa40357
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/gvt.c
> @@ -0,0 +1,205 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include <linux/types.h>
> +#include <xen/xen.h>
> +#include <linux/kthread.h>
> +
> +#include "gvt.h"
> +
> +struct intel_gvt_host intel_gvt_host;
> +
> +static const char * const supported_hypervisors[] = {
> + [INTEL_GVT_HYPERVISOR_XEN] = "XEN",
> + [INTEL_GVT_HYPERVISOR_KVM] = "KVM",
> +};
> +
> +#define MB(x) (x * 1024ULL * 1024ULL)
> +#define GB(x) (x * MB(1024))
> +
> +/*
> + * The layout of BAR0 in BDW:
> + * |< - MMIO 2MB ->|<- Reserved 6MB ->|<- MAX GTT 8MB->|
> + *
> + * GTT offset in BAR0 starts from 8MB to 16MB, and
> + * Whatever GTT size is configured in BIOS,
> + * the size of BAR0 is always 16MB. The actual configured
> + * GTT size can be found in GMCH_CTRL.
> + */
> +static struct intel_gvt_device_info broadwell_device_info = {
> + .max_gtt_gm_sz = GB(4), /* 4GB */
> + .gtt_start_offset = MB(8), /* 8MB */
> + .max_gtt_size = MB(8), /* 8MB */
> + .gtt_entry_size = 8,
> + .gtt_entry_size_shift = 3,
> + .gmadr_bytes_in_cmd = 8,
> + .mmio_size = MB(2), /* 2MB */
> + .mmio_bar = 0, /* BAR 0 */
> + .max_support_vgpu = 8,
> +};
> +
> +static int init_gvt_host(void)
> +{
> + if (WARN(intel_gvt_host.initialized,
> + "Intel GVT host has already been initialized\n"))
> + return -EINVAL;
> +
> + /* Xen DOM U */
> + if (xen_domain() && !xen_initial_domain())
> + return -ENODEV;
> +
> + if (xen_initial_domain()) {
> + /* Xen Dom0 */
> + intel_gvt_host.mpt = try_then_request_module(
> + symbol_get(xengt_mpt), "xengt");
> + intel_gvt_host.hypervisor_type = INTEL_GVT_HYPERVISOR_XEN;
> + } else {
> + /* not in Xen. Try KVMGT */
> + intel_gvt_host.mpt = try_then_request_module(
> + symbol_get(kvmgt_mpt), "kvm");
> + intel_gvt_host.hypervisor_type = INTEL_GVT_HYPERVISOR_KVM;
> + }
> +
> + if (!intel_gvt_host.mpt) {
> + gvt_err("Fail to load any MPT modules.\n");
> + return -EINVAL;
> + }
> +
> + if (!intel_gvt_hypervisor_detect_host())
> + return -ENODEV;
> +
> + gvt_info("Running with hypervisor %s in host mode\n",
> + supported_hypervisors[intel_gvt_host.hypervisor_type]);
> +
> + idr_init(&intel_gvt_host.gvt_idr);
> + mutex_init(&intel_gvt_host.gvt_idr_lock);
> +
> + intel_gvt_host.initialized = true;
> + return 0;
> +}
> +
> +static int init_device_info(struct intel_gvt *gvt)
> +{
> + if (IS_BROADWELL(gvt->dev_priv))
> + gvt->device_info = &broadwell_device_info;
> + else
> + return -ENODEV;
> +
My previous comment was that intel_gvt_create_device (which calls this)
can only get called if is_supported_device succeeded. And the latter has
the same IS_BROADWELL check.
So to me error handling in init_device_info looks redundant.
I would probably just remove this function and initialize device info
directly in intel_gvt_create_device which would simplify error handling
there and you probably would end up with one debug message in there as
well then.
> + return 0;
> +}
> +
> +static void free_gvt_device(struct intel_gvt *gvt)
> +{
> + mutex_lock(&intel_gvt_host.gvt_idr_lock);
> + idr_remove(&intel_gvt_host.gvt_idr, gvt->id);
> + mutex_unlock(&intel_gvt_host.gvt_idr_lock);
> +
> + vfree(gvt);
> +}
> +
> +static struct intel_gvt *alloc_gvt_device(struct drm_i915_private *dev_priv)
> +{
> + struct intel_gvt *gvt;
> + int ret;
> +
> + gvt = vzalloc(sizeof(*gvt));
> + if (!gvt)
> + return ERR_PTR(-ENOMEM);
> +
> + mutex_lock(&intel_gvt_host.gvt_idr_lock);
> + ret = idr_alloc(&intel_gvt_host.gvt_idr, gvt, 0, 0, GFP_KERNEL);
> + mutex_unlock(&intel_gvt_host.gvt_idr_lock);
> +
> + if (ret < 0)
> + goto err;
> +
> + gvt->id = ret;
> + mutex_init(&gvt->lock);
> + gvt->dev_priv = dev_priv;
> + idr_init(&gvt->vgpu_idr);
> +
> + return gvt;
> +err:
> + free_gvt_device(gvt);
> + return ERR_PTR(ret);
> +}
> +
> +/**
> + * intel_gvt_destroy_device - destroy a GVT device
> + * @gvt_device: gvt device
> + *
> + * This function is called at the driver unloading stage, to destroy a
> + * GVT device and free the related resources.
> + *
> + */
> +void intel_gvt_destroy_device(void *device)
You said this is a void * because you do not want to include gvt/gvt.h -
but this is gvt.c so why does not it not make sense to include it?
Or you mean you don't want to include it from the callers of
intel_gvt_destroy_device?
I think it is really not ideal to have void * in the API here and also
in the data structures elsewhere. Are you sure headers cannot be
re-organized so that the correct types are used? Maybe a few forward
declarations at the right places?
> +{
> + struct intel_gvt *gvt = (struct intel_gvt *)device;
> +
> + free_gvt_device(gvt);
> +}
> +
> +/**
> + * intel_gvt_create_device - create a GVT device
> + * @dev_priv: drm i915 private data
> + *
> + * This function is called at the initialization stage, to create a
> + * GVT device and initialize necessary GVT components for it.
> + *
> + * Returns:
> + * pointer to the intel gvt device structure, error pointer if failed.
> + */
> +void *intel_gvt_create_device(struct drm_i915_private *dev_priv)
> +{
> + struct intel_gvt *gvt;
> + int ret;
> +
> + if (!intel_gvt_host.initialized) {
> + ret = init_gvt_host();
> + if (ret)
> + return ERR_PTR(ret);
> + }
> +
> + gvt_dbg_core("create new gvt device\n");
> +
> + gvt = alloc_gvt_device(dev_priv);
> + if (IS_ERR(gvt)) {
> + ret = PTR_ERR(gvt);
> + goto out_err;
> + }
> +
> + gvt_dbg_core("init gvt device, id %d\n", gvt->id);
> +
> + ret = init_device_info(gvt);
> + if (ret)
> + goto out_free_gvt_device;
> +
> + gvt_dbg_core("gvt device creation done, id %d\n", gvt->id);
> +
> + return gvt;
> +
> +out_free_gvt_device:
> + free_gvt_device(gvt);
> +out_err:
> + return ERR_PTR(ret);
> +}
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
> new file mode 100644
> index 0000000..9e6e22b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/gvt.h
> @@ -0,0 +1,84 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _GVT_H_
> +#define _GVT_H_
> +
> +#include "i915_drv.h"
> +#include "i915_vgpu.h"
> +
> +#include "debug.h"
> +#include "hypercall.h"
> +
> +#define GVT_MAX_VGPU 8
> +#define GVT_ALIGN(addr, size) ((addr) & (~((typeof(addr))(size) - 1)))
> +
> +enum {
> + INTEL_GVT_HYPERVISOR_XEN = 0,
> + INTEL_GVT_HYPERVISOR_KVM,
> +};
> +
> +struct intel_gvt_host {
> + bool initialized;
> + int hypervisor_type;
> + struct mutex gvt_idr_lock;
> + struct idr gvt_idr;
> + struct intel_gvt_mpt *mpt;
> +};
> +
> +extern struct intel_gvt_host intel_gvt_host;
> +
> +/* Describe the limitation of HW.*/
> +struct intel_gvt_device_info {
> + u64 max_gtt_gm_sz;
> + u32 gtt_start_offset;
> + u32 gtt_end_offset;
> + u32 max_gtt_size;
> + u32 gtt_entry_size;
> + u32 gtt_entry_size_shift;
> + u32 gmadr_bytes_in_cmd;
> + u32 mmio_size;
> + u32 mmio_bar;
> + u32 max_support_vgpu;
> +};
> +
> +struct intel_vgpu {
> + struct intel_gvt *gvt;
> + int id;
> + int vm_id;
> + bool warn_untrack;
> +};
> +
> +struct intel_gvt {
> + struct mutex lock;
> + int id;
> +
> + struct drm_i915_private *dev_priv;
> + struct idr vgpu_idr;
> +
> + struct intel_gvt_device_info *device_info;
> +};
> +
> +#include "mpt.h"
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h
> new file mode 100644
> index 0000000..254df8b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/hypercall.h
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _GVT_HYPERCALL_H_
> +#define _GVT_HYPERCALL_H_
> +
> +/*
> + * Specific GVT-g MPT modules function collections. Currently GVT-g supports
> + * both Xen and KVM by providing dedicated hypervisor-related MPT modules.
> + */
> +struct intel_gvt_mpt {
> + int (*detect_host)(void);
> +};
> +
> +extern struct intel_gvt_mpt xengt_mpt;
> +extern struct intel_gvt_mpt kvmgt_mpt;
> +
> +#endif /* _GVT_HYPERCALL_H_ */
> diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h
> new file mode 100644
> index 0000000..783f4f8
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/mpt.h
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _GVT_MPT_H_
> +#define _GVT_MPT_H_
> +
> +/**
> + * DOC: Hypervisor Service APIs for GVT-g Core Logic
> + *
> + * This is the glue layer between specific hypervisor MPT modules and GVT-g core
> + * logic. Each kind of hypervisor MPT module provides a collection of function
> + * callbacks via gvt_kernel_dm and will be attached to GVT host when driver
> + * loading. GVT-g core logic will call these APIs to request specific services
> + * from hypervisor.
> + */
> +
> +/**
> + * intel_gvt_hypervisor_detect_host - check if GVT-g is running within
> + * hypervisor host/privilged domain
> + *
> + * Returns:
> + * Zero on success, -ENODEV if current kernel is running inside a VM
> + */
> +static inline int intel_gvt_hypervisor_detect_host(void)
> +{
> + return intel_gvt_host.mpt->detect_host();
> +}
> +
> +#endif /* _GVT_MPT_H_ */
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 547100f..502d7cd 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -35,6 +35,7 @@
> #include "intel_drv.h"
> #include <drm/i915_drm.h>
> #include "i915_drv.h"
> +#include "intel_gvt.h"
> #include "i915_vgpu.h"
> #include "i915_trace.h"
> #include <linux/pci.h>
> @@ -1245,18 +1246,22 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
> goto out_ggtt;
> }
>
> + ret = intel_gvt_init(dev_priv);
> + if (ret)
> + goto out_ggtt;
> +
> /* WARNING: Apparently we must kick fbdev drivers before vgacon,
> * otherwise the vga fbdev driver falls over. */
> ret = i915_kick_out_firmware_fb(dev_priv);
> if (ret) {
> DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
> - goto out_ggtt;
> + goto out_gvt;
> }
>
> ret = i915_kick_out_vgacon(dev_priv);
> if (ret) {
> DRM_ERROR("failed to remove conflicting VGA console\n");
> - goto out_ggtt;
> + goto out_gvt;
> }
>
> pci_set_master(dev->pdev);
> @@ -1267,7 +1272,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
> if (ret) {
> DRM_ERROR("failed to set DMA mask\n");
>
> - goto out_ggtt;
> + goto out_gvt;
> }
> }
>
> @@ -1297,7 +1302,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
> aperture_size);
> if (!ggtt->mappable) {
> ret = -EIO;
> - goto out_ggtt;
> + goto out_gvt;
> }
>
> ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
> @@ -1330,6 +1335,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>
> return 0;
>
> +out_gvt:
> + intel_gvt_cleanup(dev_priv);
> out_ggtt:
> i915_ggtt_cleanup_hw(dev);
>
> @@ -1488,6 +1495,8 @@ int i915_driver_unload(struct drm_device *dev)
>
> intel_fbdev_fini(dev);
>
> + intel_gvt_cleanup(dev_priv);
> +
> ret = i915_gem_suspend(dev);
> if (ret) {
> DRM_ERROR("failed to idle hardware: %d\n", ret);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72f0b02..7d0b8d3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1703,6 +1703,10 @@ struct i915_workarounds {
> u32 hw_whitelist_count[I915_NUM_ENGINES];
> };
>
> +struct i915_gvt {
> + void *gvt;
> +};
> +
> struct i915_virtual_gpu {
> bool active;
> };
> @@ -1742,6 +1746,8 @@ struct drm_i915_private {
>
> struct i915_virtual_gpu vgpu;
>
> + struct i915_gvt gvt;
> +
> struct intel_guc guc;
>
> struct intel_csr csr;
> @@ -2868,6 +2874,12 @@ void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
> u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
>
> void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
> +
> +static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
> +{
> + return dev_priv->gvt.gvt ? true : false;
> +}
> +
> static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
> {
> return dev_priv->vgpu.active;
> diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
> new file mode 100644
> index 0000000..815cc9f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_gvt.c
> @@ -0,0 +1,98 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_gvt.h"
> +
> +/**
> + * DOC: Intel GVT-g host support
> + *
> + * Intel GVT-g is a graphics virtualization technology which shares the
> + * GPU among multiple virtual machines on a time-sharing basis. Each
> + * virtual machine is presented a virtual GPU (vGPU), which has equivalent
> + * features as the underlying physical GPU (pGPU), so i915 driver can run
> + * seamlessly in a virtual machine. This file provides the englightments
> + * of GVT and the necessary components used by GVT in i915 driver.
> + */
> +
> +struct gvt_kernel_params gvt_kparams = {
> + .enable = false,
> +};
> +
> +/* i915.gvt_enable */
> +module_param_named(gvt_enable, gvt_kparams.enable, bool, 0600);
> +MODULE_PARM_DESC(gvt_enable, "Enable Intel GVT-g host support");
> +
> +static bool is_supported_device(struct drm_i915_private *dev_priv)
> +{
> + if (IS_BROADWELL(dev_priv))
> + return true;
> + return false;
> +}
> +
> +/**
> + * intel_gvt_init - initialize GVT components
> + * @dev_priv: drm i915 private data
> + *
> + * This function is called at the initialization stage to initialize the
> + * GVT components.
> + */
> +int intel_gvt_init(struct drm_i915_private *dev_priv)
> +{
> + void *device;
> +
> + if (!gvt_kparams.enable) {
> + DRM_DEBUG_DRIVER("GVT-g is disabled by kernel params\n");
> + return 0;
> + }
> +
> + if (!is_supported_device(dev_priv)) {
> + DRM_DEBUG_DRIVER("Unsupported device. GVT-g is disabled\n");
> + return 0;
> + }
> +
> + device = intel_gvt_create_device(dev_priv);
> + if (IS_ERR(device)) {
> + DRM_DEBUG_DRIVER("GVT-g is disabled\n");
> + return 0;
> + }
> +
> + dev_priv->gvt.gvt = device;
> + return 0;
> +}
> +
> +/**
> + * intel_gvt_cleanup - cleanup GVT components when i915 driver is unloading
> + * @dev_priv: drm i915 private *
> + *
> + * This function is called at the i915 driver unloading stage, to shutdown
> + * GVT components and release the related resources.
> + */
> +void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
> +{
> + if (!intel_gvt_active(dev_priv))
> + return;
> +
> + intel_gvt_destroy_device(dev_priv->gvt.gvt);
> + dev_priv->gvt.gvt = NULL;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
> new file mode 100644
> index 0000000..8079dfd
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_gvt.h
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#ifndef _INTEL_GVT_H_
> +#define _INTEL_GVT_H_
> +
> +#ifdef CONFIG_DRM_I915_GVT
> +
> +#include <drm/i915_gvt.h>
> +
> +struct gvt_kernel_params {
> + bool enable;
> +};
> +
> +extern struct gvt_kernel_params gvt_kparams;
> +
> +extern int intel_gvt_init(struct drm_i915_private *dev_priv);
> +extern void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
> +#else
> +static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
> +{
> + return 0;
> +}
> +static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
> +{
> +}
> +#endif
> +
> +#endif /* _INTEL_GVT_H_ */
> diff --git a/include/drm/i915_gvt.h b/include/drm/i915_gvt.h
> new file mode 100644
> index 0000000..4ed8b88
> --- /dev/null
> +++ b/include/drm/i915_gvt.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + * All Rights Reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction, including
> + * without limitation the rights to use, copy, modify, merge, publish,
> + * distribute, sub license, and/or sell copies of the Software, and to
> + * permit persons to whom the Software is furnished to do so, subject to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> + * next paragraph) shall be included in all copies or substantial portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +#ifndef _I915_GVT_H
> +#define _I915_GVT_H
> +
> +extern void *intel_gvt_create_device(void *dev_priv);
void * dev_priv, vey bad :) And the below signature I've commented already.
> +extern void intel_gvt_destroy_device(void *gvt);
> +
> +#endif /* _I915_GVT_H */
>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/9] drm/i915/gvt: Fold vGPU active check into inner functions
2016-05-18 10:54 ` Tvrtko Ursulin
@ 2016-05-20 10:27 ` Wang, Zhi A
0 siblings, 0 replies; 30+ messages in thread
From: Wang, Zhi A @ 2016-05-20 10:27 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, chris@chris-wilson.co.uk,
Tian, Kevin, Lv, Zhiyuan
Thanks! :)
> -----Original Message-----
> From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com]
> Sent: Wednesday, May 18, 2016 1:55 PM
> To: Wang, Zhi A <zhi.a.wang@intel.com>; intel-gfx@lists.freedesktop.org;
> joonas.lahtinen@linux.intel.com; chris@chris-wilson.co.uk; Tian, Kevin
> <kevin.tian@intel.com>; Lv, Zhiyuan <zhiyuan.lv@intel.com>
> Subject: Re: [PATCH 2/9] drm/i915/gvt: Fold vGPU active check into inner
> functions
>
>
> On 17/05/16 09:19, Zhi Wang wrote:
> > v5:
> > - Let functions take struct drm_i915_private *. (Tvrtko)
> >
> > - Fold vGPU related active check into the inner functions. (Kevin)
> >
> > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++++-------
> > drivers/gpu/drm/i915/i915_vgpu.c | 13 +++++++++----
> > drivers/gpu/drm/i915/i915_vgpu.h | 4 ++--
> > 3 files changed, 15 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 7eab619..820b59e 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -2737,11 +2737,9 @@ static int i915_gem_setup_global_gtt(struct
> drm_device *dev,
> > i915_address_space_init(&ggtt->base, dev_priv);
> > ggtt->base.total += PAGE_SIZE;
> >
> > - if (intel_vgpu_active(dev_priv)) {
> > - ret = intel_vgt_balloon(dev);
> > - if (ret)
> > - return ret;
> > - }
> > + ret = intel_vgt_balloon(dev_priv);
> > + if (ret)
> > + return ret;
> >
> > if (!HAS_LLC(dev))
> > ggtt->base.mm.color_adjust = i915_gtt_color_adjust; @@
> -2841,8
> > +2839,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
> > i915_gem_cleanup_stolen(dev);
> >
> > if (drm_mm_initialized(&ggtt->base.mm)) {
> > - if (intel_vgpu_active(dev_priv))
> > - intel_vgt_deballoon();
> > + intel_vgt_deballoon(dev_priv);
> >
> > drm_mm_takedown(&ggtt->base.mm);
> > list_del(&ggtt->base.global_link);
> > diff --git a/drivers/gpu/drm/i915/i915_vgpu.c
> > b/drivers/gpu/drm/i915/i915_vgpu.c
> > index d5a7a5e..5312816 100644
> > --- a/drivers/gpu/drm/i915/i915_vgpu.c
> > +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> > @@ -101,10 +101,13 @@ static struct _balloon_info_ bl_info;
> > * This function is called to deallocate the ballooned-out graphic memory,
> when
> > * driver is unloaded or when ballooning fails.
> > */
> > -void intel_vgt_deballoon(void)
> > +void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
> > {
> > int i;
> >
> > + if (!intel_vgpu_active(dev_priv))
> > + return;
> > +
> > DRM_DEBUG("VGT deballoon.\n");
> >
> > for (i = 0; i < 4; i++) {
> > @@ -177,9 +180,8 @@ static int vgt_balloon_space(struct drm_mm *mm,
> > * Returns:
> > * zero on success, non-zero if configuration invalid or ballooning failed
> > */
> > -int intel_vgt_balloon(struct drm_device *dev)
> > +int intel_vgt_balloon(struct drm_i915_private *dev_priv)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(dev);
> > struct i915_ggtt *ggtt = &dev_priv->ggtt;
> > unsigned long ggtt_end = ggtt->base.start + ggtt->base.total;
> >
> > @@ -187,6 +189,9 @@ int intel_vgt_balloon(struct drm_device *dev)
> > unsigned long unmappable_base, unmappable_size,
> unmappable_end;
> > int ret;
> >
> > + if (!intel_vgpu_active(dev_priv))
> > + return 0;
> > +
> > mappable_base =
> I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
> > mappable_size =
> I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
> > unmappable_base =
> > I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
> > @@ -258,6 +263,6 @@ int intel_vgt_balloon(struct drm_device *dev)
> >
> > err:
> > DRM_ERROR("VGT balloon fail\n");
> > - intel_vgt_deballoon();
> > + intel_vgt_deballoon(dev_priv);
> > return ret;
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_vgpu.h
> > b/drivers/gpu/drm/i915/i915_vgpu.h
> > index 07e67d5..f8917c6 100644
> > --- a/drivers/gpu/drm/i915/i915_vgpu.h
> > +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> > @@ -27,7 +27,7 @@
> > #include "i915_pvinfo.h"
> >
> > extern void i915_check_vgpu(struct drm_i915_private *dev_priv);
> > -extern int intel_vgt_balloon(struct drm_device *dev); -extern void
> > intel_vgt_deballoon(void);
> > +extern int intel_vgt_balloon(struct drm_i915_private *dev_priv);
> > +extern void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
> >
> > #endif /* _I915_VGPU_H_ */
> >
>
> Looks clean to me.
>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Regards,
>
> Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g
2016-05-18 11:22 ` Tvrtko Ursulin
@ 2016-05-20 10:57 ` Wang, Zhi A
0 siblings, 0 replies; 30+ messages in thread
From: Wang, Zhi A @ 2016-05-20 10:57 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx@lists.freedesktop.org,
joonas.lahtinen@linux.intel.com, chris@chris-wilson.co.uk,
Tian, Kevin, Lv, Zhiyuan
Thanks Tvrtko.:) See my replies below.
> -----Original Message-----
> From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com]
> Sent: Wednesday, May 18, 2016 2:23 PM
> To: Wang, Zhi A <zhi.a.wang@intel.com>; intel-gfx@lists.freedesktop.org;
> joonas.lahtinen@linux.intel.com; chris@chris-wilson.co.uk; Tian, Kevin
> <kevin.tian@intel.com>; Lv, Zhiyuan <zhiyuan.lv@intel.com>
> Subject: Re: [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of
> GVT-g
>
>
> On 17/05/16 09:19, Zhi Wang wrote:
> > This patch introduces the very basic framework of GVT-g device model,
> > includes basic prototypes, definitions, initialization.
> >
> > v5:
> > Take Tvrtko's comments:
> > - Fix the misspelled words in Kconfg
> > - Let functions take drm_i915_private * instead of struct drm_device *
> > - Remove redundant prints/local varible initialization
> >
> > v3:
> > Take Joonas' comments:
> > - Change file name i915_gvt.* to intel_gvt.*
> > - Move GVT kernel parameter into intel_gvt.c
> > - Remove redundant debug macros
> > - Change error handling style
> > - Add introductions for some stub functions
> > - Introduce drm/i915_gvt.h.
> >
> > Take Kevin's comments:
> > - Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c
> >
> > v2:
> > - Introduce i915_gvt.c.
> > It's necessary to introduce the stubs between i915 driver and GVT-g
> > host, as GVT-g components is configurable in kernel config. When
> > disabled, the stubs here do nothing.
> >
> > Take Joonas' comments:
> > - Replace boolean return value with int.
> > - Replace customized info/warn/debug macros with DRM macros.
> > - Document all non-static functions like i915.
> > - Remove empty and unused functions.
> > - Replace magic number with marcos.
> > - Set GVT-g in kernel config to "n" by default.
> >
> > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> > ---
> > drivers/gpu/drm/i915/Kconfig | 15 +++
> > drivers/gpu/drm/i915/Makefile | 5 +
> > drivers/gpu/drm/i915/gvt/Makefile | 5 +
> > drivers/gpu/drm/i915/gvt/debug.h | 36 ++++++
> > drivers/gpu/drm/i915/gvt/gvt.c | 205
> +++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/gvt/gvt.h | 84 ++++++++++++++
> > drivers/gpu/drm/i915/gvt/hypercall.h | 38 +++++++
> > drivers/gpu/drm/i915/gvt/mpt.h | 49 +++++++++
> > drivers/gpu/drm/i915/i915_dma.c | 17 ++-
> > drivers/gpu/drm/i915/i915_drv.h | 12 ++
> > drivers/gpu/drm/i915/intel_gvt.c | 98 +++++++++++++++++
> > drivers/gpu/drm/i915/intel_gvt.h | 49 +++++++++
> > include/drm/i915_gvt.h | 31 ++++++
> > 13 files changed, 640 insertions(+), 4 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/gvt/Makefile
> > create mode 100644 drivers/gpu/drm/i915/gvt/debug.h
> > create mode 100644 drivers/gpu/drm/i915/gvt/gvt.c
> > create mode 100644 drivers/gpu/drm/i915/gvt/gvt.h
> > create mode 100644 drivers/gpu/drm/i915/gvt/hypercall.h
> > create mode 100644 drivers/gpu/drm/i915/gvt/mpt.h
> > create mode 100644 drivers/gpu/drm/i915/intel_gvt.c
> > create mode 100644 drivers/gpu/drm/i915/intel_gvt.h
> > create mode 100644 include/drm/i915_gvt.h
> >
> > diff --git a/drivers/gpu/drm/i915/Kconfig
> > b/drivers/gpu/drm/i915/Kconfig index 29a32b1..feb56ee 100644
> > --- a/drivers/gpu/drm/i915/Kconfig
> > +++ b/drivers/gpu/drm/i915/Kconfig
> > @@ -57,6 +57,21 @@ config DRM_I915_USERPTR
> >
> > If in doubt, say "Y".
> >
> > +config DRM_I915_GVT
> > + bool "Intel GVT-g host driver"
> > + depends on DRM_I915
> > + default n
> > + help
> > + Enabling GVT-g mediated graphics pass-through technique for
> Intel i915
> > + based integrated graphics card. With GVT-g, it's possible to
> have one
> > + integrated i915 device shared by multiple VMs. Performance
> critical
> > + operations such as aperture accesses and ring buffer
> operations
> > + are passed-through to VM, with a minimal set of conflicting
> > +resources
>
> Maybe I am confused but to me this is not clear. If we have multiple VMs
> sharing the GPU where performance critical operations are passed-through to
> the *VM* ? Aren't they passed-through to the GPU/host/hypervisor or
> something rather than the VM?
>
This section is talking about aperture partition.
For aperture partition, first hypervisor will allocate a aperture region and notify VM the begin/end of this region, then VM would know in the whole "guest" aperture bar, only a portion could be used. Then hypervisor directly map the guest aperture region to the allocated host aperture portion through the EPT. When guest accesses this aperture, it won't be trapped, just directly reached the related host aperture region.
> > + (e.g. display settings) mediated by GVT host driver. The benefit
> of GVT
> > + is on both the performance, given that each VM could directly
> operate
> > + its aperture space and submit commands like running on native,
> and
> > + the feature completeness, given that a true GEN hardware is
> exposed.
> > +
> > menu "drm/i915 Debugging"
> > depends on DRM_I915
> > depends on EXPERT
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index 63c4d2b..e48145b 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -103,6 +103,11 @@ i915-y += i915_vgpu.o
> > # legacy horrors
> > i915-y += i915_dma.o
> >
> > +ifeq ($(CONFIG_DRM_I915_GVT),y)
> > +i915-y += intel_gvt.o
> > +include $(src)/gvt/Makefile
> > +endif
> > +
> > obj-$(CONFIG_DRM_I915) += i915.o
> >
> > CFLAGS_i915_trace_points.o := -I$(src) diff --git
> > a/drivers/gpu/drm/i915/gvt/Makefile
> > b/drivers/gpu/drm/i915/gvt/Makefile
> > new file mode 100644
> > index 0000000..d0f21a6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gvt/Makefile
> > @@ -0,0 +1,5 @@
> > +GVT_DIR := gvt
> > +GVT_SOURCE := gvt.o
> > +
> > +ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall
> > +i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
> > diff --git a/drivers/gpu/drm/i915/gvt/debug.h
> > b/drivers/gpu/drm/i915/gvt/debug.h
> > new file mode 100644
> > index 0000000..5b067d2
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gvt/debug.h
> > @@ -0,0 +1,36 @@
> > +/*
> > + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> > +DEALINGS IN THE
> > + * SOFTWARE.
> > + */
> > +
> > +#ifndef __GVT_DEBUG_H__
> > +#define __GVT_DEBUG_H__
> > +
> > +#define gvt_info(fmt, args...) \
> > + DRM_INFO("gvt: "fmt, ##args)
> > +
> > +#define gvt_err(fmt, args...) \
> > + DRM_ERROR("gvt: "fmt, ##args)
> > +
> > +#define gvt_dbg_core(fmt, args...) \
> > + DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/i915/gvt/gvt.c
> > b/drivers/gpu/drm/i915/gvt/gvt.c new file mode 100644 index
> > 0000000..aa40357
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gvt/gvt.c
> > @@ -0,0 +1,205 @@
> > +/*
> > + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> > +DEALINGS IN THE
> > + * SOFTWARE.
> > + */
> > +
> > +#include <linux/types.h>
> > +#include <xen/xen.h>
> > +#include <linux/kthread.h>
> > +
> > +#include "gvt.h"
> > +
> > +struct intel_gvt_host intel_gvt_host;
> > +
> > +static const char * const supported_hypervisors[] = {
> > + [INTEL_GVT_HYPERVISOR_XEN] = "XEN",
> > + [INTEL_GVT_HYPERVISOR_KVM] = "KVM",
> > +};
> > +
> > +#define MB(x) (x * 1024ULL * 1024ULL) #define GB(x) (x * MB(1024))
> > +
> > +/*
> > + * The layout of BAR0 in BDW:
> > + * |< - MMIO 2MB ->|<- Reserved 6MB ->|<- MAX GTT 8MB->|
> > + *
> > + * GTT offset in BAR0 starts from 8MB to 16MB, and
> > + * Whatever GTT size is configured in BIOS,
> > + * the size of BAR0 is always 16MB. The actual configured
> > + * GTT size can be found in GMCH_CTRL.
> > + */
> > +static struct intel_gvt_device_info broadwell_device_info = {
> > + .max_gtt_gm_sz = GB(4), /* 4GB */
> > + .gtt_start_offset = MB(8), /* 8MB */
> > + .max_gtt_size = MB(8), /* 8MB */
> > + .gtt_entry_size = 8,
> > + .gtt_entry_size_shift = 3,
> > + .gmadr_bytes_in_cmd = 8,
> > + .mmio_size = MB(2), /* 2MB */
> > + .mmio_bar = 0, /* BAR 0 */
> > + .max_support_vgpu = 8,
> > +};
> > +
> > +static int init_gvt_host(void)
> > +{
> > + if (WARN(intel_gvt_host.initialized,
> > + "Intel GVT host has already been initialized\n"))
> > + return -EINVAL;
> > +
> > + /* Xen DOM U */
> > + if (xen_domain() && !xen_initial_domain())
> > + return -ENODEV;
> > +
> > + if (xen_initial_domain()) {
> > + /* Xen Dom0 */
> > + intel_gvt_host.mpt = try_then_request_module(
> > + symbol_get(xengt_mpt), "xengt");
> > + intel_gvt_host.hypervisor_type = INTEL_GVT_HYPERVISOR_XEN;
> > + } else {
> > + /* not in Xen. Try KVMGT */
> > + intel_gvt_host.mpt = try_then_request_module(
> > + symbol_get(kvmgt_mpt), "kvm");
> > + intel_gvt_host.hypervisor_type = INTEL_GVT_HYPERVISOR_KVM;
> > + }
> > +
> > + if (!intel_gvt_host.mpt) {
> > + gvt_err("Fail to load any MPT modules.\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (!intel_gvt_hypervisor_detect_host())
> > + return -ENODEV;
> > +
> > + gvt_info("Running with hypervisor %s in host mode\n",
> > + supported_hypervisors[intel_gvt_host.hypervisor_type]);
> > +
> > + idr_init(&intel_gvt_host.gvt_idr);
> > + mutex_init(&intel_gvt_host.gvt_idr_lock);
> > +
> > + intel_gvt_host.initialized = true;
> > + return 0;
> > +}
> > +
> > +static int init_device_info(struct intel_gvt *gvt) {
> > + if (IS_BROADWELL(gvt->dev_priv))
> > + gvt->device_info = &broadwell_device_info;
> > + else
> > + return -ENODEV;
> > +
>
> My previous comment was that intel_gvt_create_device (which calls this) can
> only get called if is_supported_device succeeded. And the latter has the same
> IS_BROADWELL check.
>
> So to me error handling in init_device_info looks redundant.
>
> I would probably just remove this function and initialize device info directly in
> intel_gvt_create_device which would simplify error handling there and you
> probably would end up with one debug message in there as well then.
>
Good point. Got it now. :)
> > + return 0;
> > +}
> > +
> > +static void free_gvt_device(struct intel_gvt *gvt) {
> > + mutex_lock(&intel_gvt_host.gvt_idr_lock);
> > + idr_remove(&intel_gvt_host.gvt_idr, gvt->id);
> > + mutex_unlock(&intel_gvt_host.gvt_idr_lock);
> > +
> > + vfree(gvt);
> > +}
> > +
> > +static struct intel_gvt *alloc_gvt_device(struct drm_i915_private
> > +*dev_priv) {
> > + struct intel_gvt *gvt;
> > + int ret;
> > +
> > + gvt = vzalloc(sizeof(*gvt));
> > + if (!gvt)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + mutex_lock(&intel_gvt_host.gvt_idr_lock);
> > + ret = idr_alloc(&intel_gvt_host.gvt_idr, gvt, 0, 0, GFP_KERNEL);
> > + mutex_unlock(&intel_gvt_host.gvt_idr_lock);
> > +
> > + if (ret < 0)
> > + goto err;
> > +
> > + gvt->id = ret;
> > + mutex_init(&gvt->lock);
> > + gvt->dev_priv = dev_priv;
> > + idr_init(&gvt->vgpu_idr);
> > +
> > + return gvt;
> > +err:
> > + free_gvt_device(gvt);
> > + return ERR_PTR(ret);
> > +}
> > +
> > +/**
> > + * intel_gvt_destroy_device - destroy a GVT device
> > + * @gvt_device: gvt device
> > + *
> > + * This function is called at the driver unloading stage, to destroy
> > +a
> > + * GVT device and free the related resources.
> > + *
> > + */
> > +void intel_gvt_destroy_device(void *device)
>
> You said this is a void * because you do not want to include gvt/gvt.h - but this
> is gvt.c so why does not it not make sense to include it?
>
> Or you mean you don't want to include it from the callers of
> intel_gvt_destroy_device?
>
> I think it is really not ideal to have void * in the API here and also in the data
> structures elsewhere. Are you sure headers cannot be re-organized so that the
> correct types are used? Maybe a few forward declarations at the right places?
>
Yes. I don't want the caller of the intel_gvt_{creat/destroy}_device to include "gvt/gvt.h". As "struct intel_gvt" will be a big data structure in furture, if I get intel_gvt_*_device take it, I have to introduce a lot of sub-data structures.
Probably I can let them take "struct i915_gvt" directly. So we don't need to pass void * in API.
> > +{
> > + struct intel_gvt *gvt = (struct intel_gvt *)device;
> > +
> > + free_gvt_device(gvt);
> > +}
> > +
> > +/**
> > + * intel_gvt_create_device - create a GVT device
> > + * @dev_priv: drm i915 private data
> > + *
> > + * This function is called at the initialization stage, to create a
> > + * GVT device and initialize necessary GVT components for it.
> > + *
> > + * Returns:
> > + * pointer to the intel gvt device structure, error pointer if failed.
> > + */
> > +void *intel_gvt_create_device(struct drm_i915_private *dev_priv) {
> > + struct intel_gvt *gvt;
> > + int ret;
> > +
> > + if (!intel_gvt_host.initialized) {
> > + ret = init_gvt_host();
> > + if (ret)
> > + return ERR_PTR(ret);
> > + }
> > +
> > + gvt_dbg_core("create new gvt device\n");
> > +
> > + gvt = alloc_gvt_device(dev_priv);
> > + if (IS_ERR(gvt)) {
> > + ret = PTR_ERR(gvt);
> > + goto out_err;
> > + }
> > +
> > + gvt_dbg_core("init gvt device, id %d\n", gvt->id);
> > +
> > + ret = init_device_info(gvt);
> > + if (ret)
> > + goto out_free_gvt_device;
> > +
> > + gvt_dbg_core("gvt device creation done, id %d\n", gvt->id);
> > +
> > + return gvt;
> > +
> > +out_free_gvt_device:
> > + free_gvt_device(gvt);
> > +out_err:
> > + return ERR_PTR(ret);
> > +}
> > diff --git a/drivers/gpu/drm/i915/gvt/gvt.h
> > b/drivers/gpu/drm/i915/gvt/gvt.h new file mode 100644 index
> > 0000000..9e6e22b
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gvt/gvt.h
> > @@ -0,0 +1,84 @@
> > +/*
> > + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> > +DEALINGS IN THE
> > + * SOFTWARE.
> > + */
> > +
> > +#ifndef _GVT_H_
> > +#define _GVT_H_
> > +
> > +#include "i915_drv.h"
> > +#include "i915_vgpu.h"
> > +
> > +#include "debug.h"
> > +#include "hypercall.h"
> > +
> > +#define GVT_MAX_VGPU 8
> > +#define GVT_ALIGN(addr, size) ((addr) & (~((typeof(addr))(size) -
> > +1)))
> > +
> > +enum {
> > + INTEL_GVT_HYPERVISOR_XEN = 0,
> > + INTEL_GVT_HYPERVISOR_KVM,
> > +};
> > +
> > +struct intel_gvt_host {
> > + bool initialized;
> > + int hypervisor_type;
> > + struct mutex gvt_idr_lock;
> > + struct idr gvt_idr;
> > + struct intel_gvt_mpt *mpt;
> > +};
> > +
> > +extern struct intel_gvt_host intel_gvt_host;
> > +
> > +/* Describe the limitation of HW.*/
> > +struct intel_gvt_device_info {
> > + u64 max_gtt_gm_sz;
> > + u32 gtt_start_offset;
> > + u32 gtt_end_offset;
> > + u32 max_gtt_size;
> > + u32 gtt_entry_size;
> > + u32 gtt_entry_size_shift;
> > + u32 gmadr_bytes_in_cmd;
> > + u32 mmio_size;
> > + u32 mmio_bar;
> > + u32 max_support_vgpu;
> > +};
> > +
> > +struct intel_vgpu {
> > + struct intel_gvt *gvt;
> > + int id;
> > + int vm_id;
> > + bool warn_untrack;
> > +};
> > +
> > +struct intel_gvt {
> > + struct mutex lock;
> > + int id;
> > +
> > + struct drm_i915_private *dev_priv;
> > + struct idr vgpu_idr;
> > +
> > + struct intel_gvt_device_info *device_info; };
> > +
> > +#include "mpt.h"
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h
> > b/drivers/gpu/drm/i915/gvt/hypercall.h
> > new file mode 100644
> > index 0000000..254df8b
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gvt/hypercall.h
> > @@ -0,0 +1,38 @@
> > +/*
> > + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> > +DEALINGS IN THE
> > + * SOFTWARE.
> > + */
> > +
> > +#ifndef _GVT_HYPERCALL_H_
> > +#define _GVT_HYPERCALL_H_
> > +
> > +/*
> > + * Specific GVT-g MPT modules function collections. Currently GVT-g
> > +supports
> > + * both Xen and KVM by providing dedicated hypervisor-related MPT
> modules.
> > + */
> > +struct intel_gvt_mpt {
> > + int (*detect_host)(void);
> > +};
> > +
> > +extern struct intel_gvt_mpt xengt_mpt; extern struct intel_gvt_mpt
> > +kvmgt_mpt;
> > +
> > +#endif /* _GVT_HYPERCALL_H_ */
> > diff --git a/drivers/gpu/drm/i915/gvt/mpt.h
> > b/drivers/gpu/drm/i915/gvt/mpt.h new file mode 100644 index
> > 0000000..783f4f8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gvt/mpt.h
> > @@ -0,0 +1,49 @@
> > +/*
> > + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> > +DEALINGS IN THE
> > + * SOFTWARE.
> > + */
> > +
> > +#ifndef _GVT_MPT_H_
> > +#define _GVT_MPT_H_
> > +
> > +/**
> > + * DOC: Hypervisor Service APIs for GVT-g Core Logic
> > + *
> > + * This is the glue layer between specific hypervisor MPT modules and
> > +GVT-g core
> > + * logic. Each kind of hypervisor MPT module provides a collection of
> > +function
> > + * callbacks via gvt_kernel_dm and will be attached to GVT host when
> > +driver
> > + * loading. GVT-g core logic will call these APIs to request specific
> > +services
> > + * from hypervisor.
> > + */
> > +
> > +/**
> > + * intel_gvt_hypervisor_detect_host - check if GVT-g is running
> > +within
> > + * hypervisor host/privilged domain
> > + *
> > + * Returns:
> > + * Zero on success, -ENODEV if current kernel is running inside a VM
> > +*/ static inline int intel_gvt_hypervisor_detect_host(void)
> > +{
> > + return intel_gvt_host.mpt->detect_host();
> > +}
> > +
> > +#endif /* _GVT_MPT_H_ */
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c index 547100f..502d7cd 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -35,6 +35,7 @@
> > #include "intel_drv.h"
> > #include <drm/i915_drm.h>
> > #include "i915_drv.h"
> > +#include "intel_gvt.h"
> > #include "i915_vgpu.h"
> > #include "i915_trace.h"
> > #include <linux/pci.h>
> > @@ -1245,18 +1246,22 @@ static int i915_driver_init_hw(struct
> drm_i915_private *dev_priv)
> > goto out_ggtt;
> > }
> >
> > + ret = intel_gvt_init(dev_priv);
> > + if (ret)
> > + goto out_ggtt;
> > +
> > /* WARNING: Apparently we must kick fbdev drivers before vgacon,
> > * otherwise the vga fbdev driver falls over. */
> > ret = i915_kick_out_firmware_fb(dev_priv);
> > if (ret) {
> > DRM_ERROR("failed to remove conflicting framebuffer
> drivers\n");
> > - goto out_ggtt;
> > + goto out_gvt;
> > }
> >
> > ret = i915_kick_out_vgacon(dev_priv);
> > if (ret) {
> > DRM_ERROR("failed to remove conflicting VGA console\n");
> > - goto out_ggtt;
> > + goto out_gvt;
> > }
> >
> > pci_set_master(dev->pdev);
> > @@ -1267,7 +1272,7 @@ static int i915_driver_init_hw(struct
> drm_i915_private *dev_priv)
> > if (ret) {
> > DRM_ERROR("failed to set DMA mask\n");
> >
> > - goto out_ggtt;
> > + goto out_gvt;
> > }
> > }
> >
> > @@ -1297,7 +1302,7 @@ static int i915_driver_init_hw(struct
> drm_i915_private *dev_priv)
> > aperture_size);
> > if (!ggtt->mappable) {
> > ret = -EIO;
> > - goto out_ggtt;
> > + goto out_gvt;
> > }
> >
> > ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
> > @@ -1330,6 +1335,8 @@ static int i915_driver_init_hw(struct
> > drm_i915_private *dev_priv)
> >
> > return 0;
> >
> > +out_gvt:
> > + intel_gvt_cleanup(dev_priv);
> > out_ggtt:
> > i915_ggtt_cleanup_hw(dev);
> >
> > @@ -1488,6 +1495,8 @@ int i915_driver_unload(struct drm_device *dev)
> >
> > intel_fbdev_fini(dev);
> >
> > + intel_gvt_cleanup(dev_priv);
> > +
> > ret = i915_gem_suspend(dev);
> > if (ret) {
> > DRM_ERROR("failed to idle hardware: %d\n", ret); diff --git
> > a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 72f0b02..7d0b8d3 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1703,6 +1703,10 @@ struct i915_workarounds {
> > u32 hw_whitelist_count[I915_NUM_ENGINES];
> > };
> >
> > +struct i915_gvt {
> > + void *gvt;
> > +};
> > +
> > struct i915_virtual_gpu {
> > bool active;
> > };
> > @@ -1742,6 +1746,8 @@ struct drm_i915_private {
> >
> > struct i915_virtual_gpu vgpu;
> >
> > + struct i915_gvt gvt;
> > +
> > struct intel_guc guc;
> >
> > struct intel_csr csr;
> > @@ -2868,6 +2874,12 @@ void intel_uncore_forcewake_put__locked(struct
> drm_i915_private *dev_priv,
> > u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
> >
> > void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
> > +
> > +static inline bool intel_gvt_active(struct drm_i915_private
> > +*dev_priv) {
> > + return dev_priv->gvt.gvt ? true : false; }
> > +
> > static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
> > {
> > return dev_priv->vgpu.active;
> > diff --git a/drivers/gpu/drm/i915/intel_gvt.c
> > b/drivers/gpu/drm/i915/intel_gvt.c
> > new file mode 100644
> > index 0000000..815cc9f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/intel_gvt.c
> > @@ -0,0 +1,98 @@
> > +/*
> > + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> > +DEALINGS IN THE
> > + * SOFTWARE.
> > + */
> > +
> > +#include "i915_drv.h"
> > +#include "intel_gvt.h"
> > +
> > +/**
> > + * DOC: Intel GVT-g host support
> > + *
> > + * Intel GVT-g is a graphics virtualization technology which shares
> > +the
> > + * GPU among multiple virtual machines on a time-sharing basis. Each
> > + * virtual machine is presented a virtual GPU (vGPU), which has
> > +equivalent
> > + * features as the underlying physical GPU (pGPU), so i915 driver can
> > +run
> > + * seamlessly in a virtual machine. This file provides the
> > +englightments
> > + * of GVT and the necessary components used by GVT in i915 driver.
> > + */
> > +
> > +struct gvt_kernel_params gvt_kparams = {
> > + .enable = false,
> > +};
> > +
> > +/* i915.gvt_enable */
> > +module_param_named(gvt_enable, gvt_kparams.enable, bool, 0600);
> > +MODULE_PARM_DESC(gvt_enable, "Enable Intel GVT-g host support");
> > +
> > +static bool is_supported_device(struct drm_i915_private *dev_priv) {
> > + if (IS_BROADWELL(dev_priv))
> > + return true;
> > + return false;
> > +}
> > +
> > +/**
> > + * intel_gvt_init - initialize GVT components
> > + * @dev_priv: drm i915 private data
> > + *
> > + * This function is called at the initialization stage to initialize
> > +the
> > + * GVT components.
> > + */
> > +int intel_gvt_init(struct drm_i915_private *dev_priv) {
> > + void *device;
> > +
> > + if (!gvt_kparams.enable) {
> > + DRM_DEBUG_DRIVER("GVT-g is disabled by kernel params\n");
> > + return 0;
> > + }
> > +
> > + if (!is_supported_device(dev_priv)) {
> > + DRM_DEBUG_DRIVER("Unsupported device. GVT-g is disabled\n");
> > + return 0;
> > + }
> > +
> > + device = intel_gvt_create_device(dev_priv);
> > + if (IS_ERR(device)) {
> > + DRM_DEBUG_DRIVER("GVT-g is disabled\n");
> > + return 0;
> > + }
> > +
> > + dev_priv->gvt.gvt = device;
> > + return 0;
> > +}
> > +
> > +/**
> > + * intel_gvt_cleanup - cleanup GVT components when i915 driver is
> > +unloading
> > + * @dev_priv: drm i915 private *
> > + *
> > + * This function is called at the i915 driver unloading stage, to
> > +shutdown
> > + * GVT components and release the related resources.
> > + */
> > +void intel_gvt_cleanup(struct drm_i915_private *dev_priv) {
> > + if (!intel_gvt_active(dev_priv))
> > + return;
> > +
> > + intel_gvt_destroy_device(dev_priv->gvt.gvt);
> > + dev_priv->gvt.gvt = NULL;
> > +}
> > diff --git a/drivers/gpu/drm/i915/intel_gvt.h
> > b/drivers/gpu/drm/i915/intel_gvt.h
> > new file mode 100644
> > index 0000000..8079dfd
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/intel_gvt.h
> > @@ -0,0 +1,49 @@
> > +/*
> > + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> > +DEALINGS IN THE
> > + * SOFTWARE.
> > + */
> > +
> > +#ifndef _INTEL_GVT_H_
> > +#define _INTEL_GVT_H_
> > +
> > +#ifdef CONFIG_DRM_I915_GVT
> > +
> > +#include <drm/i915_gvt.h>
> > +
> > +struct gvt_kernel_params {
> > + bool enable;
> > +};
> > +
> > +extern struct gvt_kernel_params gvt_kparams;
> > +
> > +extern int intel_gvt_init(struct drm_i915_private *dev_priv); extern
> > +void intel_gvt_cleanup(struct drm_i915_private *dev_priv); #else
> > +static inline int intel_gvt_init(struct drm_i915_private *dev_priv) {
> > + return 0;
> > +}
> > +static inline void intel_gvt_cleanup(struct drm_i915_private
> > +*dev_priv) { } #endif
> > +
> > +#endif /* _INTEL_GVT_H_ */
> > diff --git a/include/drm/i915_gvt.h b/include/drm/i915_gvt.h new file
> > mode 100644 index 0000000..4ed8b88
> > --- /dev/null
> > +++ b/include/drm/i915_gvt.h
> > @@ -0,0 +1,31 @@
> > +/*
> > + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> > + * All Rights Reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > + * "Software"), to deal in the Software without restriction,
> > +including
> > + * without limitation the rights to use, copy, modify, merge,
> > +publish,
> > + * distribute, sub license, and/or sell copies of the Software, and
> > +to
> > + * permit persons to whom the Software is furnished to do so, subject
> > +to
> > + * the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the
> > + * next paragraph) shall be included in all copies or substantial
> > +portions
> > + * of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> > +OTHER
> > + * DEALINGS IN THE SOFTWARE.
> > + */
> > +#ifndef _I915_GVT_H
> > +#define _I915_GVT_H
> > +
> > +extern void *intel_gvt_create_device(void *dev_priv);
>
> void * dev_priv, vey bad :) And the below signature I've commented already.
>
Sure. Will improve it in the next version. :)
> > +extern void intel_gvt_destroy_device(void *gvt);
> > +
> > +#endif /* _I915_GVT_H */
> >
>
>
> Regards,
>
> Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 7/9] drm/i915: Introduce execlist context status change notification
2016-05-17 8:19 ` [PATCH 7/9] drm/i915: Introduce execlist context status change notification Zhi Wang
2016-05-17 10:51 ` Tvrtko Ursulin
@ 2016-05-20 11:16 ` Chris Wilson
2016-05-20 11:42 ` Wang, Zhi A
1 sibling, 1 reply; 30+ messages in thread
From: Chris Wilson @ 2016-05-20 11:16 UTC (permalink / raw)
To: Zhi Wang; +Cc: intel-gfx, zhiyuan.lv
On Tue, May 17, 2016 at 04:19:07AM -0400, Zhi Wang wrote:
> This patch introduces an approach to track the execlist context status
> change.
>
> GVT-g uses GVT context as the "shadow context". The content inside GVT
> context will be copied back to guest after the context is idle. So GVT-g
> has to know the status of the execlist context.
>
> This function is configurable in the context creation service. Currently,
> Only GVT-g will create the "status-change-notification" enabled GEM
> context.
>
> v5:
>
> - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko)
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
> drivers/gpu/drm/i915/intel_lrc.c | 30 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_lrc.h | 7 +++++++
> 3 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 91f69e5..9688006 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -882,9 +882,15 @@ struct intel_context {
> u64 lrc_desc;
> uint32_t *lrc_reg_state;
> bool initialised;
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + struct atomic_notifier_head status_notifier_head;
struct atomic_notifier_head status_notifier;
> +#endif
> } engine[I915_NUM_ENGINES];
> u32 ring_buffer_size;
> bool use_48bit_addressing_mode;
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + bool enable_status_change_notification;
unsigned status_notify;
> +#endif
>
> struct list_head link;
> };
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d97623f..9069836 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -415,6 +415,20 @@ static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
> spin_unlock_irq(&dev_priv->uncore.lock);
> }
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
Actually, I think there will be other use cases for this notifier.
So let's not clutter the code with #ifdefs. Remove the ones from the
struct and do
> +static inline void execlists_context_status_change(
> + struct drm_i915_gem_request *req,
> + unsigned long status)
> +{
if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
return;
instead. The compiler should be fine with the dead-code elimination.
> + if (!req->ctx->enable_status_change_notification)
What locks are you holding here?
if (!READ_ONCE(req->ctx->status_notify))
return;
> + return;
> +
> + atomic_notifier_call_chain(
> + &req->ctx->engine[req->engine->id].status_notifier_head,
I think we have enough justification for req->ctx_engine;
> + status, req);
> +}
> +#endif
> +
> static void execlists_context_unqueue(struct intel_engine_cs *engine)
> {
> struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
> @@ -450,6 +464,13 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
> if (unlikely(!req0))
> return;
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + execlists_context_status_change(req0, CONTEXT_SCHEDULE_IN);
> +
> + if (req1)
> + execlists_context_status_change(req1, CONTEXT_SCHEDULE_IN);
> +#endif
> +
> if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
> /*
> * WaIdleLiteRestore: make sure we never cause a lite restore
> @@ -488,6 +509,10 @@ execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id)
> if (--head_req->elsp_submitted > 0)
> return 0;
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + execlists_context_status_change(head_req, CONTEXT_SCHEDULE_OUT);
> +#endif
> +
> list_del(&head_req->execlist_link);
> i915_gem_request_unreference(head_req);
>
> @@ -2534,6 +2559,11 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
> ctx->engine[engine->id].state = ctx_obj;
> ctx->engine[engine->id].initialised = engine->init_context == NULL;
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> + if (ctx->enable_status_change_notification)
Always do the init. That allows us to start switching the notify on/off
at runtime.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 7/9] drm/i915: Introduce execlist context status change notification
2016-05-20 11:16 ` Chris Wilson
@ 2016-05-20 11:42 ` Wang, Zhi A
0 siblings, 0 replies; 30+ messages in thread
From: Wang, Zhi A @ 2016-05-20 11:42 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx@lists.freedesktop.org, Lv, Zhiyuan
Oh. Thanks Chris!
> -----Original Message-----
> From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> Sent: Friday, May 20, 2016 2:17 PM
> To: Wang, Zhi A <zhi.a.wang@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; tvrtko.ursulin@linux.intel.com;
> joonas.lahtinen@linux.intel.com; Tian, Kevin <kevin.tian@intel.com>; Lv,
> Zhiyuan <zhiyuan.lv@intel.com>
> Subject: Re: [PATCH 7/9] drm/i915: Introduce execlist context status change
> notification
>
> On Tue, May 17, 2016 at 04:19:07AM -0400, Zhi Wang wrote:
> > This patch introduces an approach to track the execlist context status
> > change.
> >
> > GVT-g uses GVT context as the "shadow context". The content inside GVT
> > context will be copied back to guest after the context is idle. So
> > GVT-g has to know the status of the execlist context.
> >
> > This function is configurable in the context creation service.
> > Currently, Only GVT-g will create the "status-change-notification"
> > enabled GEM context.
> >
> > v5:
> >
> > - Only compile this feature when CONFIG_DRM_I915_GVT is
> > enabled.(Tvrtko)
> >
> > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
> > drivers/gpu/drm/i915/intel_lrc.c | 30 ++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_lrc.h | 7 +++++++
> > 3 files changed, 43 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 91f69e5..9688006 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -882,9 +882,15 @@ struct intel_context {
> > u64 lrc_desc;
> > uint32_t *lrc_reg_state;
> > bool initialised;
> > +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> > + struct atomic_notifier_head status_notifier_head;
>
> struct atomic_notifier_head status_notifier;
>
> > +#endif
> > } engine[I915_NUM_ENGINES];
> > u32 ring_buffer_size;
> > bool use_48bit_addressing_mode;
> > +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> > + bool enable_status_change_notification;
>
> unsigned status_notify;
>
> > +#endif
> >
> > struct list_head link;
> > };
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index d97623f..9069836 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -415,6 +415,20 @@ static void execlists_submit_requests(struct
> drm_i915_gem_request *rq0,
> > spin_unlock_irq(&dev_priv->uncore.lock);
> > }
> >
> > +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
>
> Actually, I think there will be other use cases for this notifier.
> So let's not clutter the code with #ifdefs. Remove the ones from the struct and
> do
>
OK. I guess the reason you want to turn a "bool" to "unsigned" is:
if (status_notify & NOTFIY_CONTEXT_STATUS)
notify context status change
if (status_notify & NOTIFY_OTHER_THINGS)
notify other things
.... extend it in future.
Or is there any other reason? Glad to know. :)
> > +static inline void execlists_context_status_change(
> > + struct drm_i915_gem_request *req,
> > + unsigned long status)
> > +{
>
> if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
> return;
>
> instead. The compiler should be fine with the dead-code elimination.
>
OK. Will do.
>
> > + if (!req->ctx->enable_status_change_notification)
>
> What locks are you holding here?
>
I'm holding engine->execlist_lock at this path.
> if (!READ_ONCE(req->ctx->status_notify))
> return;
>
> > + return;
> > +
> > + atomic_notifier_call_chain(
> > + &req->ctx->engine[req->engine->id].status_notifier_head,
>
> I think we have enough justification for req->ctx_engine;
>
Are you saying you're doing some refactors on req->ctx, or you want to get some local pointers in this function, so that the req->xxxxx could be much shorter? :)
> > + status, req);
> > +}
> > +#endif
> > +
> > static void execlists_context_unqueue(struct intel_engine_cs *engine)
> > {
> > struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; @@ -450,6
> > +464,13 @@ static void execlists_context_unqueue(struct intel_engine_cs
> *engine)
> > if (unlikely(!req0))
> > return;
> >
> > +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> > + execlists_context_status_change(req0, CONTEXT_SCHEDULE_IN);
> > +
> > + if (req1)
> > + execlists_context_status_change(req1, CONTEXT_SCHEDULE_IN);
>
> > +#endif
> > +
> > if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
> > /*
> > * WaIdleLiteRestore: make sure we never cause a lite restore @@
> > -488,6 +509,10 @@ execlists_check_remove_request(struct intel_engine_cs
> *engine, u32 ctx_id)
> > if (--head_req->elsp_submitted > 0)
> > return 0;
> >
> > +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> > + execlists_context_status_change(head_req, CONTEXT_SCHEDULE_OUT);
> > +#endif
> > +
> > list_del(&head_req->execlist_link);
> > i915_gem_request_unreference(head_req);
> >
> > @@ -2534,6 +2559,11 @@ static int execlists_context_deferred_alloc(struct
> intel_context *ctx,
> > ctx->engine[engine->id].state = ctx_obj;
> > ctx->engine[engine->id].initialised = engine->init_context == NULL;
> >
> > +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> > + if (ctx->enable_status_change_notification)
>
> Always do the init. That allows us to start switching the notify on/off at
> runtime.
Good idea. Will do :)
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g
2016-05-17 8:19 ` [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g Zhi Wang
2016-05-18 11:22 ` Tvrtko Ursulin
@ 2016-05-20 11:49 ` Chris Wilson
2016-05-20 12:18 ` Wang, Zhi A
1 sibling, 1 reply; 30+ messages in thread
From: Chris Wilson @ 2016-05-20 11:49 UTC (permalink / raw)
To: Zhi Wang; +Cc: intel-gfx, zhiyuan.lv
On Tue, May 17, 2016 at 04:19:03AM -0400, Zhi Wang wrote:
> +config DRM_I915_GVT
> + bool "Intel GVT-g host driver"
> + depends on DRM_I915
> + default n
> + help
> + Enabling GVT-g mediated graphics pass-through technique for Intel i915
> + based integrated graphics card. With GVT-g, it's possible to have one
> + integrated i915 device shared by multiple VMs. Performance critical
> + operations such as aperture accesses and ring buffer operations
> + are passed-through to VM, with a minimal set of conflicting resources
> + (e.g. display settings) mediated by GVT host driver. The benefit of GVT
> + is on both the performance, given that each VM could directly operate
> + its aperture space and submit commands like running on native, and
> + the feature completeness, given that a true GEN hardware is exposed.
Just like that? No userspace support required? i.e. can it work with
kvm or xen? Wants a comment on any possible danger (or why is it 'n' by
default)?
> +#ifndef __GVT_DEBUG_H__
> +#define __GVT_DEBUG_H__
> +
> +#define gvt_info(fmt, args...) \
> + DRM_INFO("gvt: "fmt, ##args)
> +
> +#define gvt_err(fmt, args...) \
> + DRM_ERROR("gvt: "fmt, ##args)
I think it is fair to say that neither of these will look nice in
user-facing messages.
> +
> +#define gvt_dbg_core(fmt, args...) \
> + DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
> new file mode 100644
> index 0000000..aa40357
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/gvt.c
> @@ -0,0 +1,205 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include <linux/types.h>
> +#include <xen/xen.h>
> +#include <linux/kthread.h>
> +
> +#include "gvt.h"
> +
> +struct intel_gvt_host intel_gvt_host;
> +
> +static const char * const supported_hypervisors[] = {
> + [INTEL_GVT_HYPERVISOR_XEN] = "XEN",
> + [INTEL_GVT_HYPERVISOR_KVM] = "KVM",
> +};
> +
> +#define MB(x) (x * 1024ULL * 1024ULL)
> +#define GB(x) (x * MB(1024))
> +
> +/*
> + * The layout of BAR0 in BDW:
> + * |< - MMIO 2MB ->|<- Reserved 6MB ->|<- MAX GTT 8MB->|
> + *
> + * GTT offset in BAR0 starts from 8MB to 16MB, and
> + * Whatever GTT size is configured in BIOS,
> + * the size of BAR0 is always 16MB. The actual configured
> + * GTT size can be found in GMCH_CTRL.
> + */
> +static struct intel_gvt_device_info broadwell_device_info = {
> + .max_gtt_gm_sz = GB(4), /* 4GB */
> + .gtt_start_offset = MB(8), /* 8MB */
> + .max_gtt_size = MB(8), /* 8MB */
> + .gtt_entry_size = 8,
> + .gtt_entry_size_shift = 3,
> + .gmadr_bytes_in_cmd = 8,
> + .mmio_size = MB(2), /* 2MB */
> + .mmio_bar = 0, /* BAR 0 */
> + .max_support_vgpu = 8,
Too much superfluous detail upfront. It is hard to critique when you have
no idea what it is for. At the moment, it looks like you are duplicating
information we have elsewhere, and I'd rather not. (For starters, it
makes GVT a bigger maintainance burden.)
> +/**
> + * intel_gvt_destroy_device - destroy a GVT device
> + * @gvt_device: gvt device
> + *
> + * This function is called at the driver unloading stage, to destroy a
> + * GVT device and free the related resources.
> + *
> + */
> +void intel_gvt_destroy_device(void *device)
This should not be void *. You can forward declare struct intel_gvt such
that the core has an opaque pointer.
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72f0b02..7d0b8d3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1703,6 +1703,10 @@ struct i915_workarounds {
> u32 hw_whitelist_count[I915_NUM_ENGINES];
> };
>
> +struct i915_gvt {
> + void *gvt;
As before. No void * here.
> +};
> +struct gvt_kernel_params {
> + bool enable;
> +};
> +
> +extern struct gvt_kernel_params gvt_kparams;
No. Just make room for them inside i915_params. Module parameters
deserve extra scrutiny as they are (soft) ABI (even if we think users
shouldn't be using them).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g
2016-05-17 8:19 ` [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g Zhi Wang
@ 2016-05-20 12:00 ` Chris Wilson
2016-05-20 12:19 ` Wang, Zhi A
0 siblings, 1 reply; 30+ messages in thread
From: Chris Wilson @ 2016-05-20 12:00 UTC (permalink / raw)
To: Zhi Wang; +Cc: intel-gfx, zhiyuan.lv
On Tue, May 17, 2016 at 04:19:04AM -0400, Zhi Wang wrote:
> From: Bing Niu <bing.niu@intel.com>
>
> This patch introduces host graphics memory partition when GVT-g
> is enabled.
>
> Under GVT-g, i915 host driver only owned limited graphics resources,
> others are managed by GVT-g resource allocator and kept for other vGPUs.
Strong justification required for why the user is expected to get these
right via module parameters.
> +/*
> + * Under GVT-g, i915 host driver only owned limited graphics resources,
> + * others are managed by GVT-g resource allocator and kept for other vGPUs.
> + *
> + * For graphics memory space partition, a typical layout looks like:
> + *
> + * +-------+-----------------------+------+-----------------------+
> + * |* Host | *GVT-g Resource |* Host| *GVT-g Resource |
> + * | Owned | Allocator Managed | Owned| Allocator Managed |
> + * | | | | |
> + * +---------------+-------+----------------------+-------+-------+
> + * | | | | | | | | |
> + * | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 |
> + * | | | | | | | | |
> + * +-------+-------+-------+--------------+-------+-------+-------+
> + * | Aperture | Hidden |
> + * +-------------------------------+------------------------------+
> + * | GGTT memory space |
> + * +--------------------------------------------------------------+
> + */
> struct i915_gvt {
> void *gvt;
> + u64 low_gm_size;
> + u64 high_gm_size;
> };
>
> struct i915_virtual_gpu {
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 5312816..9382f04 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -189,13 +189,24 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
> unsigned long unmappable_base, unmappable_size, unmappable_end;
> int ret;
>
> - if (!intel_vgpu_active(dev_priv))
> + if (!intel_vgpu_active(dev_priv) && !intel_gvt_active(dev_priv))
> return 0;
>
> - mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
> - mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
> - unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
> - unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
> + if (intel_gvt_active(dev_priv)) {
> + mappable_base = 0;
> + mappable_size = dev_priv->gvt.low_gm_size;
> + unmappable_base = dev_priv->ggtt.mappable_end;
> + unmappable_size = dev_priv->gvt.high_gm_size;
> + } else if (intel_vgpu_active(dev_priv)) {
> + mappable_base = I915_READ(
> + vgtif_reg(avail_rs.mappable_gmadr.base));
> + mappable_size = I915_READ(
> + vgtif_reg(avail_rs.mappable_gmadr.size));
> + unmappable_base = I915_READ(
> + vgtif_reg(avail_rs.nonmappable_gmadr.base));
> + unmappable_size = I915_READ(
> + vgtif_reg(avail_rs.nonmappable_gmadr.size));
> + }
else
return 0;
and lose the early return.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 5/9] drm/i915: Make ring buffer size configurable
2016-05-17 8:19 ` [PATCH 5/9] drm/i915: Make ring buffer size configurable Zhi Wang
@ 2016-05-20 12:01 ` Chris Wilson
2016-05-20 12:20 ` Wang, Zhi A
0 siblings, 1 reply; 30+ messages in thread
From: Chris Wilson @ 2016-05-20 12:01 UTC (permalink / raw)
To: Zhi Wang; +Cc: intel-gfx, zhiyuan.lv
On Tue, May 17, 2016 at 04:19:05AM -0400, Zhi Wang wrote:
> This patch introduces an option for configuring ring buffer size during
> context creation. If no ring buffer size is specified, the default size
> (4 * PAGE_SIZE) will be used.
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++--
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ea04352..cc83f2d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -883,6 +883,7 @@ struct intel_context {
> uint32_t *lrc_reg_state;
> bool initialised;
> } engine[I915_NUM_ENGINES];
> + u32 ring_buffer_size;
>
> struct list_head link;
> };
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index db10c96..d52c806 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2495,7 +2495,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
> struct intel_engine_cs *engine)
> {
> struct drm_i915_gem_object *ctx_obj;
> - uint32_t context_size;
> + uint32_t context_size, ring_buffer_size;
> struct intel_ringbuffer *ringbuf;
> int ret;
>
> @@ -2513,7 +2513,11 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
> return PTR_ERR(ctx_obj);
> }
>
> - ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
> + ring_buffer_size = ctx->ring_buffer_size;
> + if (!ring_buffer_size)
> + ring_buffer_size = 4 * PAGE_SIZE;
Just don't let it be zero (during construction).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 6/9] drm/i915: Generate addressing mode bit from flag in context.
2016-05-17 8:19 ` [PATCH 6/9] drm/i915: Generate addressing mode bit from flag in context Zhi Wang
@ 2016-05-20 12:03 ` Chris Wilson
2016-05-20 12:23 ` Wang, Zhi A
0 siblings, 1 reply; 30+ messages in thread
From: Chris Wilson @ 2016-05-20 12:03 UTC (permalink / raw)
To: Zhi Wang; +Cc: intel-gfx, zhiyuan.lv
On Tue, May 17, 2016 at 04:19:06AM -0400, Zhi Wang wrote:
> Previously the addressing mode bit in context descriptor is generated from
> context PPGTT. As we allow context could be used without PPGTT, and we
> still need to know the addressing mode during context submission, a flag
> is introduced.
>
> And the addressing mode bit will be generated from this flag.
>
> v5:
>
> - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
> drivers/gpu/drm/i915/intel_lrc.c | 9 +++++----
> 3 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cc83f2d..91f69e5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -884,6 +884,7 @@ struct intel_context {
> bool initialised;
> } engine[I915_NUM_ENGINES];
> u32 ring_buffer_size;
> + bool use_48bit_addressing_mode;
A whole bool? You could put the desc.addressing_mode in there!
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 8/9] drm/i915: Support context single submission
2016-05-17 8:19 ` [PATCH 8/9] drm/i915: Support context single submission Zhi Wang
@ 2016-05-20 12:04 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2016-05-20 12:04 UTC (permalink / raw)
To: Zhi Wang; +Cc: intel-gfx, zhiyuan.lv
On Tue, May 17, 2016 at 04:19:08AM -0400, Zhi Wang wrote:
> This patch introduces the support of context signle submission. As GVT
> context may come from different guests, which requires different
> configuration of render registers. It can't be combined in a dual ELSP
> submission combo.
>
> We make this function as a context feature in context creation service.
> Only GVT-g will create this kinds of GEM context currently.
>
> v5:
>
> - Only compile this feature when CONFIG_DRM_I915_GVT=y. (Tvrtko)
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_lrc.c | 15 +++++++++++++++
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9688006..b8f1e9a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -890,8 +890,8 @@ struct intel_context {
> bool use_48bit_addressing_mode;
> #if IS_ENABLED(CONFIG_DRM_I915_GVT)
> bool enable_status_change_notification;
> + bool single_submission;
> #endif
> -
> struct list_head link;
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 9069836..8d1a9c2 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -455,6 +455,21 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
> i915_gem_request_unreference(req0);
> req0 = cursor;
> } else {
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> +
But no ifdefs in code.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 9/9] drm/i915: Introduce GVT context creation API
2016-05-17 8:19 ` [PATCH 9/9] drm/i915: Introduce GVT context creation API Zhi Wang
@ 2016-05-20 12:06 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2016-05-20 12:06 UTC (permalink / raw)
Cc: intel-gfx, zhiyuan.lv
On Tue, May 17, 2016 at 04:19:09AM -0400, Zhi Wang wrote:
> GVT workload scheduler needs special host LRC contexts, the so called
> "shadow LRC context" to submit guest workload to host i915. During the
> guest workload submission, GVT fills the shadow LRC context with the
> content of guest LRC context: engine context is copied without changes,
> ring context is mostly owned by host i915.
>
> The GVT-g workload scheduler flow:
>
> +-----------+ +-----------+
> | GVT Guest | | GVT Guest |
> +-+-----^---+ +-+-----^---+
> | | | |
> | | GVT-g | | GVT-g
> vELSP write| | emulates vELSP write| | emulates
> | | Execlist/CSB | | Execlist/CSB
> | | Status | | Status
> | | | |
> +------v-----+-------------------------v-----+---------+
> | GVT Virtual Execlist Submission |
> +------+-------------------------------+---------------+
> | |
> | Per-VM/Ring Workoad Q | Per-VM/Ring Workload Q
> +---------------------+--+ +------------------------+
> +---v--------+ ^ +---v--------+
> |GVT Workload|... | |GVT Workload|...
> +------------+ | +------------+
> |
> | Pick Workload from Q
> +--------------------+---------------------------------+
> | GVT Workload Scheduler |
> +--------------------+---------------------------------+
> | * Shadow guest LRC context
> +------v------+ * Shadow guest ring buffer
> | GVT Context | * Scan/Patch guest RB instructions
> +------+------+
> |
> v
> Host i915 GEM Submission
> v5:
> - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.
> - Rebase the code into new repo.
> - Add a comment about the ring buffer size.
>
> v2:
>
> Mostly based on Daniel's idea. Call the refactored core logic of GEM
> context creation service and LRC context creation service to create the GVT
> context.
>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gem_context.c | 31 +++++++++++++++++++++++++++++++
> 2 files changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b8f1e9a..7e5a506 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3398,6 +3398,7 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
> void i915_gem_context_free(struct kref *ctx_ref);
> struct drm_i915_gem_object *
> i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
> +struct intel_context *i915_gem_create_gvt_context(struct drm_device *dev);
> static inline void i915_gem_context_reference(struct intel_context *ctx)
> {
> kref_get(&ctx->ref);
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 057e2fe..a69bb86 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -354,6 +354,37 @@ err_destroy:
> return ERR_PTR(ret);
> }
>
> +#if IS_ENABLED(CONFIG_DRM_I915_GVT)
> +/**
> + * i915_gem_create_gvt_context - create a GVT GEM context
> + * @dev: drm device *
> + *
> + * This function is used to create a GVT specific GEM context.
> + *
> + * Returns:
> + * pointer to intel_context on success, NULL if failed
> + *
> + */
> +struct intel_context *
> +i915_gem_create_gvt_context(struct drm_device *dev)
i915_gem_context_create_gvt
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g
2016-05-20 11:49 ` Chris Wilson
@ 2016-05-20 12:18 ` Wang, Zhi A
2016-05-20 12:37 ` Chris Wilson
0 siblings, 1 reply; 30+ messages in thread
From: Wang, Zhi A @ 2016-05-20 12:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx@lists.freedesktop.org, Lv, Zhiyuan
Thanks! See my replies below.
> -----Original Message-----
> From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> Sent: Friday, May 20, 2016 2:49 PM
> To: Wang, Zhi A <zhi.a.wang@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; tvrtko.ursulin@linux.intel.com;
> joonas.lahtinen@linux.intel.com; Tian, Kevin <kevin.tian@intel.com>; Lv,
> Zhiyuan <zhiyuan.lv@intel.com>
> Subject: Re: [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of
> GVT-g
>
> On Tue, May 17, 2016 at 04:19:03AM -0400, Zhi Wang wrote:
> > +config DRM_I915_GVT
> > + bool "Intel GVT-g host driver"
> > + depends on DRM_I915
> > + default n
> > + help
> > + Enabling GVT-g mediated graphics pass-through technique for
> Intel i915
> > + based integrated graphics card. With GVT-g, it's possible to
> have one
> > + integrated i915 device shared by multiple VMs. Performance
> critical
> > + operations such as aperture accesses and ring buffer
> operations
> > + are passed-through to VM, with a minimal set of conflicting
> resources
> > + (e.g. display settings) mediated by GVT host driver. The benefit
> of GVT
> > + is on both the performance, given that each VM could directly
> operate
> > + its aperture space and submit commands like running on native,
> and
> > + the feature completeness, given that a true GEN hardware is
> exposed.
>
> Just like that? No userspace support required? i.e. can it work with kvm or xen?
> Wants a comment on any possible danger (or why is it 'n' by default)?
>
Basically that text is only technical introduction. Or maybe we could discuss what we want here:
a. Basic technical introduction.
b. Need Xen and KVM
c. Possible danger as it's only preliminary for now.
i915 Kconfig introduction consists 3 parts:
a. Introduction
b. Userspace requirement
c. Limitiation
Can I follow that? :)
> > +#ifndef __GVT_DEBUG_H__
> > +#define __GVT_DEBUG_H__
> > +
> > +#define gvt_info(fmt, args...) \
> > + DRM_INFO("gvt: "fmt, ##args)
> > +
> > +#define gvt_err(fmt, args...) \
> > + DRM_ERROR("gvt: "fmt, ##args)
>
> I think it is fair to say that neither of these will look nice in user-facing
> messages.
>
Then how about [drm][gvt]? :)
> > +
> > +#define gvt_dbg_core(fmt, args...) \
> > + DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/i915/gvt/gvt.c
> > b/drivers/gpu/drm/i915/gvt/gvt.c new file mode 100644 index
> > 0000000..aa40357
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gvt/gvt.c
> > @@ -0,0 +1,205 @@
> > +/*
> > + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > +ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> > +DEALINGS IN THE
> > + * SOFTWARE.
> > + */
> > +
> > +#include <linux/types.h>
> > +#include <xen/xen.h>
> > +#include <linux/kthread.h>
> > +
> > +#include "gvt.h"
> > +
> > +struct intel_gvt_host intel_gvt_host;
> > +
> > +static const char * const supported_hypervisors[] = {
> > + [INTEL_GVT_HYPERVISOR_XEN] = "XEN",
> > + [INTEL_GVT_HYPERVISOR_KVM] = "KVM",
> > +};
> > +
> > +#define MB(x) (x * 1024ULL * 1024ULL) #define GB(x) (x * MB(1024))
> > +
> > +/*
> > + * The layout of BAR0 in BDW:
> > + * |< - MMIO 2MB ->|<- Reserved 6MB ->|<- MAX GTT 8MB->|
> > + *
> > + * GTT offset in BAR0 starts from 8MB to 16MB, and
> > + * Whatever GTT size is configured in BIOS,
> > + * the size of BAR0 is always 16MB. The actual configured
> > + * GTT size can be found in GMCH_CTRL.
> > + */
> > +static struct intel_gvt_device_info broadwell_device_info = {
> > + .max_gtt_gm_sz = GB(4), /* 4GB */
> > + .gtt_start_offset = MB(8), /* 8MB */
> > + .max_gtt_size = MB(8), /* 8MB */
> > + .gtt_entry_size = 8,
> > + .gtt_entry_size_shift = 3,
> > + .gmadr_bytes_in_cmd = 8,
> > + .mmio_size = MB(2), /* 2MB */
> > + .mmio_bar = 0, /* BAR 0 */
> > + .max_support_vgpu = 8,
>
> Too much superfluous detail upfront. It is hard to critique when you have no
> idea what it is for. At the moment, it looks like you are duplicating information
> we have elsewhere, and I'd rather not. (For starters, it makes GVT a bigger
> maintainance burden.)
>
OK. Then I think I should remove most them in the first path and add them in the later patch. And do you want me to merge these HW descriptions into i915_device_info? Some of them might not be used by i915 driver itself. That's why I keep a dedicated data structure here.
> > +/**
> > + * intel_gvt_destroy_device - destroy a GVT device
> > + * @gvt_device: gvt device
> > + *
> > + * This function is called at the driver unloading stage, to destroy
> > +a
> > + * GVT device and free the related resources.
> > + *
> > + */
> > +void intel_gvt_destroy_device(void *device)
>
> This should not be void *. You can forward declare struct intel_gvt such that the
> core has an opaque pointer.
>
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 72f0b02..7d0b8d3 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1703,6 +1703,10 @@ struct i915_workarounds {
> > u32 hw_whitelist_count[I915_NUM_ENGINES];
> > };
> >
> > +struct i915_gvt {
> > + void *gvt;
>
> As before. No void * here.
>
Let me think an approach to remove the "void *" here. How about we do like this:
struct a{
Struct b;
};
Let i915 take only struct b, then in gvt we do container_of() so that we don't need to expose the declaration of struct a to i915? :)
> > +};
>
> > +struct gvt_kernel_params {
> > + bool enable;
> > +};
> > +
> > +extern struct gvt_kernel_params gvt_kparams;
>
> No. Just make room for them inside i915_params. Module parameters deserve
> extra scrutiny as they are (soft) ABI (even if we think users shouldn't be using
> them).
OK. Will do.
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g
2016-05-20 12:00 ` Chris Wilson
@ 2016-05-20 12:19 ` Wang, Zhi A
0 siblings, 0 replies; 30+ messages in thread
From: Wang, Zhi A @ 2016-05-20 12:19 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx@lists.freedesktop.org, Lv, Zhiyuan
> -----Original Message-----
> From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> Sent: Friday, May 20, 2016 3:01 PM
> To: Wang, Zhi A <zhi.a.wang@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; tvrtko.ursulin@linux.intel.com;
> joonas.lahtinen@linux.intel.com; Tian, Kevin <kevin.tian@intel.com>; Lv,
> Zhiyuan <zhiyuan.lv@intel.com>; Niu, Bing <bing.niu@intel.com>
> Subject: Re: [PATCH 4/9] drm/i915: Introduce host graphics memory partition
> for GVT-g
>
> On Tue, May 17, 2016 at 04:19:04AM -0400, Zhi Wang wrote:
> > From: Bing Niu <bing.niu@intel.com>
> >
> > This patch introduces host graphics memory partition when GVT-g is
> > enabled.
> >
> > Under GVT-g, i915 host driver only owned limited graphics resources,
> > others are managed by GVT-g resource allocator and kept for other vGPUs.
>
> Strong justification required for why the user is expected to get these right via
> module parameters.
>
Sure, will add more comments in both code and patches about that.
> > +/*
> > + * Under GVT-g, i915 host driver only owned limited graphics
> > +resources,
> > + * others are managed by GVT-g resource allocator and kept for other
> vGPUs.
> > + *
> > + * For graphics memory space partition, a typical layout looks like:
> > + *
> > + * +-------+-----------------------+------+-----------------------+
> > + * |* Host | *GVT-g Resource |* Host| *GVT-g Resource |
> > + * | Owned | Allocator Managed | Owned| Allocator Managed |
> > + * | | | |
> |
> > + * +---------------+-------+----------------------+-------+-------+
> > + * | | | | | | | |
> |
> > + * | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 |
> > + * | | | | | | | |
> |
> > + * +-------+-------+-------+--------------+-------+-------+-------+
> > + * | Aperture | Hidden
> |
> > + * +-------------------------------+------------------------------+
> > + * | GGTT memory space
> |
> > + * +--------------------------------------------------------------+
> > + */
> > struct i915_gvt {
> > void *gvt;
> > + u64 low_gm_size;
> > + u64 high_gm_size;
> > };
> >
> > struct i915_virtual_gpu {
> > diff --git a/drivers/gpu/drm/i915/i915_vgpu.c
> > b/drivers/gpu/drm/i915/i915_vgpu.c
> > index 5312816..9382f04 100644
> > --- a/drivers/gpu/drm/i915/i915_vgpu.c
> > +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> > @@ -189,13 +189,24 @@ int intel_vgt_balloon(struct drm_i915_private
> *dev_priv)
> > unsigned long unmappable_base, unmappable_size, unmappable_end;
> > int ret;
> >
> > - if (!intel_vgpu_active(dev_priv))
> > + if (!intel_vgpu_active(dev_priv) && !intel_gvt_active(dev_priv))
> > return 0;
> >
> > - mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
> > - mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
> > - unmappable_base =
> I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
> > - unmappable_size =
> I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
> > + if (intel_gvt_active(dev_priv)) {
> > + mappable_base = 0;
> > + mappable_size = dev_priv->gvt.low_gm_size;
> > + unmappable_base = dev_priv->ggtt.mappable_end;
> > + unmappable_size = dev_priv->gvt.high_gm_size;
> > + } else if (intel_vgpu_active(dev_priv)) {
> > + mappable_base = I915_READ(
> > + vgtif_reg(avail_rs.mappable_gmadr.base));
> > + mappable_size = I915_READ(
> > + vgtif_reg(avail_rs.mappable_gmadr.size));
> > + unmappable_base = I915_READ(
> > + vgtif_reg(avail_rs.nonmappable_gmadr.base));
> > + unmappable_size = I915_READ(
> > + vgtif_reg(avail_rs.nonmappable_gmadr.size));
> > + }
> else
> return 0;
>
> and lose the early return.
OK.
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 5/9] drm/i915: Make ring buffer size configurable
2016-05-20 12:01 ` Chris Wilson
@ 2016-05-20 12:20 ` Wang, Zhi A
0 siblings, 0 replies; 30+ messages in thread
From: Wang, Zhi A @ 2016-05-20 12:20 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx@lists.freedesktop.org, Lv, Zhiyuan
Thanks. Will do. :)
> -----Original Message-----
> From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> Sent: Friday, May 20, 2016 3:02 PM
> To: Wang, Zhi A <zhi.a.wang@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; tvrtko.ursulin@linux.intel.com;
> joonas.lahtinen@linux.intel.com; Tian, Kevin <kevin.tian@intel.com>; Lv,
> Zhiyuan <zhiyuan.lv@intel.com>
> Subject: Re: [PATCH 5/9] drm/i915: Make ring buffer size configurable
>
> On Tue, May 17, 2016 at 04:19:05AM -0400, Zhi Wang wrote:
> > This patch introduces an option for configuring ring buffer size
> > during context creation. If no ring buffer size is specified, the
> > default size
> > (4 * PAGE_SIZE) will be used.
> >
> > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++--
> > 2 files changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index ea04352..cc83f2d 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -883,6 +883,7 @@ struct intel_context {
> > uint32_t *lrc_reg_state;
> > bool initialised;
> > } engine[I915_NUM_ENGINES];
> > + u32 ring_buffer_size;
> >
> > struct list_head link;
> > };
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index db10c96..d52c806 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -2495,7 +2495,7 @@ static int execlists_context_deferred_alloc(struct
> intel_context *ctx,
> > struct intel_engine_cs *engine) {
> > struct drm_i915_gem_object *ctx_obj;
> > - uint32_t context_size;
> > + uint32_t context_size, ring_buffer_size;
> > struct intel_ringbuffer *ringbuf;
> > int ret;
> >
> > @@ -2513,7 +2513,11 @@ static int execlists_context_deferred_alloc(struct
> intel_context *ctx,
> > return PTR_ERR(ctx_obj);
> > }
> >
> > - ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
> > + ring_buffer_size = ctx->ring_buffer_size;
> > + if (!ring_buffer_size)
> > + ring_buffer_size = 4 * PAGE_SIZE;
>
> Just don't let it be zero (during construction).
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 6/9] drm/i915: Generate addressing mode bit from flag in context.
2016-05-20 12:03 ` Chris Wilson
@ 2016-05-20 12:23 ` Wang, Zhi A
0 siblings, 0 replies; 30+ messages in thread
From: Wang, Zhi A @ 2016-05-20 12:23 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx@lists.freedesktop.org, Lv, Zhiyuan
But the corresponding definition about desc.addressing_mode is in intel_lrc.c. And when we want to generate these bits in i915_gem_context.c we can't not reference them. Do you want me to move
define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
#define GEN8_CTX_ADDRESSING_MODE(ctx) \
(ctx->use_48bit_address_space_mode ? \
LEGACY_64B_CONTEXT :\
LEGACY_32B_CONTEXT)
to intel_lrc.h?
Thanks,
Zhi.
> -----Original Message-----
> From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> Sent: Friday, May 20, 2016 3:04 PM
> To: Wang, Zhi A <zhi.a.wang@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; tvrtko.ursulin@linux.intel.com;
> joonas.lahtinen@linux.intel.com; Tian, Kevin <kevin.tian@intel.com>; Lv,
> Zhiyuan <zhiyuan.lv@intel.com>
> Subject: Re: [PATCH 6/9] drm/i915: Generate addressing mode bit from flag in
> context.
>
> On Tue, May 17, 2016 at 04:19:06AM -0400, Zhi Wang wrote:
> > Previously the addressing mode bit in context descriptor is generated
> > from context PPGTT. As we allow context could be used without PPGTT,
> > and we still need to know the addressing mode during context
> > submission, a flag is introduced.
> >
> > And the addressing mode bit will be generated from this flag.
> >
> > v5:
> >
> > - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)
> >
> > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
> > drivers/gpu/drm/i915/intel_lrc.c | 9 +++++----
> > 3 files changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index cc83f2d..91f69e5 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -884,6 +884,7 @@ struct intel_context {
> > bool initialised;
> > } engine[I915_NUM_ENGINES];
> > u32 ring_buffer_size;
> > + bool use_48bit_addressing_mode;
>
> A whole bool? You could put the desc.addressing_mode in there!
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g
2016-05-20 12:18 ` Wang, Zhi A
@ 2016-05-20 12:37 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2016-05-20 12:37 UTC (permalink / raw)
To: Wang, Zhi A; +Cc: intel-gfx@lists.freedesktop.org, Lv, Zhiyuan
On Fri, May 20, 2016 at 12:18:10PM +0000, Wang, Zhi A wrote:
> Thanks! See my replies below.
>
> > -----Original Message-----
> > From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> > Sent: Friday, May 20, 2016 2:49 PM
> > To: Wang, Zhi A <zhi.a.wang@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; tvrtko.ursulin@linux.intel.com;
> > joonas.lahtinen@linux.intel.com; Tian, Kevin <kevin.tian@intel.com>; Lv,
> > Zhiyuan <zhiyuan.lv@intel.com>
> > Subject: Re: [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of
> > GVT-g
> >
> > On Tue, May 17, 2016 at 04:19:03AM -0400, Zhi Wang wrote:
> > > +config DRM_I915_GVT
> > > + bool "Intel GVT-g host driver"
> > > + depends on DRM_I915
> > > + default n
> > > + help
> > > + Enabling GVT-g mediated graphics pass-through technique for
> > Intel i915
> > > + based integrated graphics card. With GVT-g, it's possible to
> > have one
> > > + integrated i915 device shared by multiple VMs. Performance
> > critical
> > > + operations such as aperture accesses and ring buffer
> > operations
> > > + are passed-through to VM, with a minimal set of conflicting
> > resources
> > > + (e.g. display settings) mediated by GVT host driver. The benefit
> > of GVT
> > > + is on both the performance, given that each VM could directly
> > operate
> > > + its aperture space and submit commands like running on native,
> > and
> > > + the feature completeness, given that a true GEN hardware is
> > exposed.
> >
> > Just like that? No userspace support required? i.e. can it work with kvm or xen?
> > Wants a comment on any possible danger (or why is it 'n' by default)?
> >
> Basically that text is only technical introduction. Or maybe we could discuss what we want here:
> a. Basic technical introduction.
> b. Need Xen and KVM
> c. Possible danger as it's only preliminary for now.
>
> i915 Kconfig introduction consists 3 parts:
> a. Introduction
> b. Userspace requirement
> c. Limitiation
>
> Can I follow that? :)
I'm never going to argue against giving good advice to the reader. Even
if it is "for further details please see 01.org/blah"
> > > +#ifndef __GVT_DEBUG_H__
> > > +#define __GVT_DEBUG_H__
> > > +
> > > +#define gvt_info(fmt, args...) \
> > > + DRM_INFO("gvt: "fmt, ##args)
> > > +
> > > +#define gvt_err(fmt, args...) \
> > > + DRM_ERROR("gvt: "fmt, ##args)
> >
> > I think it is fair to say that neither of these will look nice in user-facing
> > messages.
> >
>
> Then how about [drm][gvt]? :)
Just a comment to say to hesitate before using anything above DRM_DEBUG
and ask yourself "is this the right way to provide this information to
the user, is it as clear/useful as possible?"
> > > +static struct intel_gvt_device_info broadwell_device_info = {
> > > + .max_gtt_gm_sz = GB(4), /* 4GB */
> > > + .gtt_start_offset = MB(8), /* 8MB */
> > > + .max_gtt_size = MB(8), /* 8MB */
> > > + .gtt_entry_size = 8,
> > > + .gtt_entry_size_shift = 3,
> > > + .gmadr_bytes_in_cmd = 8,
> > > + .mmio_size = MB(2), /* 2MB */
> > > + .mmio_bar = 0, /* BAR 0 */
> > > + .max_support_vgpu = 8,
> >
> > Too much superfluous detail upfront. It is hard to critique when you have no
> > idea what it is for. At the moment, it looks like you are duplicating information
> > we have elsewhere, and I'd rather not. (For starters, it makes GVT a bigger
> > maintainance burden.)
> >
> OK. Then I think I should remove most them in the first path and add them in the later patch. And do you want me to merge these HW descriptions into i915_device_info? Some of them might not be used by i915 driver itself. That's why I keep a dedicated data structure here.
It's going to be on a case by case basis, but I would rather have hw
descriptions in core.
> > > +/**
> > > + * intel_gvt_destroy_device - destroy a GVT device
> > > + * @gvt_device: gvt device
> > > + *
> > > + * This function is called at the driver unloading stage, to destroy
> > > +a
> > > + * GVT device and free the related resources.
> > > + *
> > > + */
> > > +void intel_gvt_destroy_device(void *device)
> >
> > This should not be void *. You can forward declare struct intel_gvt such that the
> > core has an opaque pointer.
> >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index 72f0b02..7d0b8d3 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1703,6 +1703,10 @@ struct i915_workarounds {
> > > u32 hw_whitelist_count[I915_NUM_ENGINES];
> > > };
> > >
> > > +struct i915_gvt {
> > > + void *gvt;
> >
> > As before. No void * here.
> >
> Let me think an approach to remove the "void *" here. How about we do like this:
> struct a{
> Struct b;
> };
>
> Let i915 take only struct b, then in gvt we do container_of() so that we don't need to expose the declaration of struct a to i915? :)
That's one approach. For starters you can just
struct intel_gvt;
struct i915_gvt {
struct intel_gvt *gvt;
};
But I wouldn't worry about encapsulation too much. You are only ever an
include away from us getting the innermost details of your structs.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2016-05-20 12:37 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-05-17 8:19 [PATCH 0/9] Introduce the implementation of GVT context Zhi Wang
2016-05-17 8:19 ` [PATCH 1/9] drm/i915: Factor out i915_pvinfo.h Zhi Wang
2016-05-17 8:19 ` [PATCH 2/9] drm/i915/gvt: Fold vGPU active check into inner functions Zhi Wang
2016-05-18 10:54 ` Tvrtko Ursulin
2016-05-20 10:27 ` Wang, Zhi A
2016-05-17 8:19 ` [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g Zhi Wang
2016-05-18 11:22 ` Tvrtko Ursulin
2016-05-20 10:57 ` Wang, Zhi A
2016-05-20 11:49 ` Chris Wilson
2016-05-20 12:18 ` Wang, Zhi A
2016-05-20 12:37 ` Chris Wilson
2016-05-17 8:19 ` [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g Zhi Wang
2016-05-20 12:00 ` Chris Wilson
2016-05-20 12:19 ` Wang, Zhi A
2016-05-17 8:19 ` [PATCH 5/9] drm/i915: Make ring buffer size configurable Zhi Wang
2016-05-20 12:01 ` Chris Wilson
2016-05-20 12:20 ` Wang, Zhi A
2016-05-17 8:19 ` [PATCH 6/9] drm/i915: Generate addressing mode bit from flag in context Zhi Wang
2016-05-20 12:03 ` Chris Wilson
2016-05-20 12:23 ` Wang, Zhi A
2016-05-17 8:19 ` [PATCH 7/9] drm/i915: Introduce execlist context status change notification Zhi Wang
2016-05-17 10:51 ` Tvrtko Ursulin
2016-05-17 15:18 ` Wang, Zhi A
2016-05-20 11:16 ` Chris Wilson
2016-05-20 11:42 ` Wang, Zhi A
2016-05-17 8:19 ` [PATCH 8/9] drm/i915: Support context single submission Zhi Wang
2016-05-20 12:04 ` Chris Wilson
2016-05-17 8:19 ` [PATCH 9/9] drm/i915: Introduce GVT context creation API Zhi Wang
2016-05-20 12:06 ` Chris Wilson
2016-05-17 8:56 ` ✗ Ro.CI.BAT: failure for Introduce the implementation of GVT context (rev2) Patchwork
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