Re: [PATCH 04/11] drm/i915: Support for GuC interrupts

Tvrtko Ursulin
2016-06-28T10:03:30Z

On 27/06/16 13:16, akash.goel@intel.com wrote:
> From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>
> There are certain types of interrupts which Host can recieve from GuC.
> GuC ukernel sends an interrupt to Host for certain events, like for
> example retrieve/consume the logs generated by ukernel.
> This patch adds support to receive interrupts from GuC but currently
> enables & partially handles only the interrupt sent by GuC ukernel.
> Future patches will add support for handling other interrupt types.
>
> v2: Use common low level routines for PM IER/IIR programming (Chris)
> Rename interrupt functions to gen9_xxx from gen8_xxx (Chris)
> Replace disabling of wake ref asserts with rpm get/put (Chris)
>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_guc_submission.c | 5 ++
> drivers/gpu/drm/i915/i915_irq.c | 95 ++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 11 ++++
> drivers/gpu/drm/i915/intel_drv.h | 3 +
> drivers/gpu/drm/i915/intel_guc.h | 5 ++
> drivers/gpu/drm/i915/intel_guc_loader.c | 4 ++
> 7 files changed, 120 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 85a7103..20c701c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1808,6 +1808,7 @@ struct drm_i915_private {
> u32 pm_irq_mask;
> u32 pm_ier_mask;
> u32 pm_rps_events;
> + u32 guc_events;
> u32 pipestat_irq_mask[I915_MAX_PIPES];
>
> struct i915_hotplug hotplug;
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 28a810f..8105ddd 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1038,6 +1038,8 @@ int intel_guc_suspend(struct drm_device *dev)
> if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> return 0;
>
> + gen9_disable_guc_interrupts(dev_priv);
> +
> ctx = dev_priv->kernel_context;
>
> data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
> @@ -1064,6 +1066,9 @@ int intel_guc_resume(struct drm_device *dev)
> if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> return 0;
>
> + if (i915.guc_log_level >= 0)
> + gen9_enable_guc_interrupts(dev_priv);
> +
> ctx = dev_priv->kernel_context;
>
> data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 7316ab4..3043e45 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -170,6 +170,7 @@ static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
> } while (0)
>
> static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
> +static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
>
> /* For display hotplug interrupt */
> static inline void
> @@ -422,6 +423,42 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
> synchronize_irq(dev_priv->dev->irq);
> }
>
> +void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
> +{
> + spin_lock_irq(&dev_priv->irq_lock);
> + gen6_reset_pm_interrupts(dev_priv, dev_priv->guc_events);
> + spin_unlock_irq(&dev_priv->irq_lock);
> +}
> +
> +void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
> +{
> + spin_lock_irq(&dev_priv->irq_lock);
> + if (!dev_priv->guc.interrupts_enabled) {
> + WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) &
> + dev_priv->guc_events);
> + dev_priv->guc.interrupts_enabled = true;
> + gen6_enable_pm_interrupts(dev_priv, dev_priv->guc_events);
> + }
> + spin_unlock_irq(&dev_priv->irq_lock);
> +}
> +
> +void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
> +{
> + spin_lock_irq(&dev_priv->irq_lock);
> + dev_priv->guc.interrupts_enabled = false;
> + spin_unlock_irq(&dev_priv->irq_lock);
> +
> + cancel_work_sync(&dev_priv->guc.events_work);
> +
> + spin_lock_irq(&dev_priv->irq_lock);
> +
> + gen6_disable_pm_interrupts(dev_priv, dev_priv->guc_events);
> +
> + spin_unlock_irq(&dev_priv->irq_lock);
> +
> + synchronize_irq(dev_priv->dev->irq);
> +}
> +
> /**
> * bdw_update_port_irq - update DE port interrupt
> * @dev_priv: driver private
> @@ -1196,6 +1233,33 @@ out:
> ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
> }
>
> +static void gen9_guc2host_events_work(struct work_struct *work)
> +{
> + struct drm_i915_private *dev_priv =
> + container_of(work, struct drm_i915_private, guc.events_work);
> +
> + spin_lock_irq(&dev_priv->irq_lock);
> + /* Speed up work cancelation during disabling guc interrupts. */
> + if (!dev_priv->guc.interrupts_enabled) {
> + spin_unlock_irq(&dev_priv->irq_lock);
> + return;
> + }
> +
> + /* Though this work item gets synced during rpm suspend, but still need
> + * a rpm get/put to avoid the warning, as it could get executed in a
> + * window, where rpm ref count has dropped to zero but rpm suspend has
> + * not kicked in. Generally device is expected to be active only at this
> + * time so get/put should be really quick.
> + */
> + intel_runtime_pm_get(dev_priv);
> +
> + gen6_enable_pm_irq(dev_priv, GEN9_GUC_TO_HOST_INT_EVENT);
> + spin_unlock_irq(&dev_priv->irq_lock);
> +
> + /* TODO: Handle the events for which GuC interrupted host */
> +
> + intel_runtime_pm_put(dev_priv);
> +}
>
> /**
> * ivybridge_parity_work - Workqueue called when a parity error interrupt
> @@ -1371,11 +1435,13 @@ static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
> DRM_ERROR("The master control interrupt lied (GT3)!\n");
> }
>
> - if (master_ctl & GEN8_GT_PM_IRQ) {
> + if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
> - if (gt_iir[2] & dev_priv->pm_rps_events) {
> + if (gt_iir[2] & (dev_priv->pm_rps_events |
> + dev_priv->guc_events)) {
> I915_WRITE_FW(GEN8_GT_IIR(2),
> - gt_iir[2] & dev_priv->pm_rps_events);
> + gt_iir[2] & (dev_priv->pm_rps_events |
> + dev_priv->guc_events));
> ret = IRQ_HANDLED;
> } else
> DRM_ERROR("The master control interrupt lied (PM)!\n");
> @@ -1407,6 +1473,9 @@ static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
>
> if (gt_iir[2] & dev_priv->pm_rps_events)
> gen6_rps_irq_handler(dev_priv, gt_iir[2]);
> +
> + if (gt_iir[2] & dev_priv->guc_events)
> + gen9_guc_irq_handler(dev_priv, gt_iir[2]);
> }
>
> static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
> @@ -1653,6 +1722,20 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
> }
> }
>
> +static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
> +{
> + if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
> + spin_lock(&dev_priv->irq_lock);
> + if (dev_priv->guc.interrupts_enabled) {

So it is expected interrupts will always be enabled when
i915.guc_log_level is set, correct?

Also do you need to check against dev_priv->guc.interrupts_enabled at
all then? Or from an opposite angle, would you instead need to log the
fact unexpected interrupt was received here?

> + /* Process all the GuC to Host events in bottom half */
> + gen6_disable_pm_irq(dev_priv,
> + GEN9_GUC_TO_HOST_INT_EVENT);

Why it is important to disable the interrupt here? Not for the queue
work I think.

Also, is it safe with regards to potentially losing the interrupt?

> + queue_work(dev_priv->wq, &dev_priv->guc.events_work);

Because dev_priv->wq is a one a time in order wq so if something else is
running on it and taking time, can that also be a cause of dropping an
interrupt or being late with sending the flush signal to the guc and so
losing some logs?

> + }
> + spin_unlock(&dev_priv->irq_lock);
> + }
> +}
> +
> static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> @@ -3809,7 +3892,7 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
> /*
> * RPS interrupts will get enabled/disabled on demand when RPS itself
> - * is enabled/disabled.
> + * is enabled/disabled. Same wil be the case for GuC interrupts.
> */
> GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
> GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
> @@ -4594,6 +4677,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>
> INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
> INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
> + INIT_WORK(&dev_priv->guc.events_work, gen9_guc2host_events_work);
> +
> + if (HAS_GUC_UCODE(dev))
> + dev_priv->guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
>
> /* Let's track the enabled rps events */
> if (IS_VALLEYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c6bfbf8..4441918 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5963,6 +5963,7 @@ enum {
> #define GEN8_DE_PIPE_A_IRQ (1<<16)
> #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
> #define GEN8_GT_VECS_IRQ (1<<6)
> +#define GEN8_GT_GUC_IRQ (1<<5)
> #define GEN8_GT_PM_IRQ (1<<4)
> #define GEN8_GT_VCS2_IRQ (1<<3)
> #define GEN8_GT_VCS1_IRQ (1<<2)
> @@ -5974,6 +5975,16 @@ enum {
> #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
> #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
>
> +#define GEN9_GUC_TO_HOST_INT_EVENT (1<<31)
> +#define GEN9_GUC_EXEC_ERROR_EVENT (1<<30)
> +#define GEN9_GUC_DISPLAY_EVENT (1<<29)
> +#define GEN9_GUC_SEMA_SIGNAL_EVENT (1<<28)
> +#define GEN9_GUC_IOMMU_MSG_EVENT (1<<27)
> +#define GEN9_GUC_DB_RING_EVENT (1<<26)
> +#define GEN9_GUC_DMA_DONE_EVENT (1<<25)
> +#define GEN9_GUC_FATAL_ERROR_EVENT (1<<24)
> +#define GEN9_GUC_NOTIFICATION_EVENT (1<<23)
> +
> #define GEN8_RCS_IRQ_SHIFT 0
> #define GEN8_BCS_IRQ_SHIFT 16
> #define GEN8_VCS1_IRQ_SHIFT 0
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 2a013fc..6966ffe 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1083,6 +1083,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> unsigned int pipe_mask);
> void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
> unsigned int pipe_mask);
> +void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
> +void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
> +void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
>
> /* intel_crt.c */
> void intel_crt_init(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 3e3e743..ae787e2 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -126,6 +126,11 @@ struct intel_guc {
> struct intel_guc_fw guc_fw;
> uint32_t log_flags;
> struct drm_i915_gem_object *log_obj;
> + /*
> + * work, interrupts_enabled are protected by dev_priv->irq_lock
> + */
> + struct work_struct events_work;
> + bool interrupts_enabled;
>
> struct drm_i915_gem_object *ads_obj;
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index db3c897..fcf36a2 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -448,6 +448,7 @@ int intel_guc_setup(struct drm_device *dev)
> }
>
> direct_interrupts_to_host(dev_priv);
> + gen9_reset_guc_interrupts(dev_priv);
>
> guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
>
> @@ -494,6 +495,9 @@ int intel_guc_setup(struct drm_device *dev)
> intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
>
> if (i915.enable_guc_submission) {
> + if (i915.guc_log_level >= 0)
> + gen9_enable_guc_interrupts(dev_priv);
> +
> err = i915_guc_submission_enable(dev_priv);
> if (err)
> goto fail;
>

Regards,

Tvrtko