From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: tim.gore@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
Date: Mon, 4 Jul 2016 17:59:42 +0100 [thread overview]
Message-ID: <577A95FE.8040206@linux.intel.com> (raw)
In-Reply-To: <1467639496-34846-1-git-send-email-tim.gore@intel.com>
On 04/07/2016 14:38, tim.gore@intel.com wrote:
> From: Tim Gore <tim.gore@intel.com>
>
> This patch applies WaMediaPoolStateCmdInWABB which fixes
> a problem with the restoration of thread counts on resuming
> from RC6.
>
> Signed-off-by: Tim Gore <tim.gore@intel.com>
suggest adding hsd ref# to commit msg.
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 676b532..017b25c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1296,6 +1296,31 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
> wa_ctx_emit(batch, index, 0);
> wa_ctx_emit(batch, index, 0);
> }
> +
> + /* WaMediaPoolStateCmdInWABB:bxt */
> + if (HAS_POOLED_EU(engine->i915)) {
> + /*
> + * EU pool configuration is setup along with golden context
> + * during context initialization. This value depends on
> + * device type (2x6 or 3x6) and needs to be updated based
> + * on which subslice is disabled especially for 2x6
> + * devices, however it is safe to load default
> + * configuration of 3x6 device instead of masking off
> + * corresponding bits because HW ignores bits of a disabled
> + * subslice and drops down to appropriate config. Please
> + * see render_state_setup() in i915_gem_render_state.c for
> + * possible configurations, to avoid duplication they are
> + * not shown here again.
> + */
> + u32 eu_pool_config = 0x00777000;
> + wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
> + wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
> + wa_ctx_emit(batch, index, eu_pool_config);
> + wa_ctx_emit(batch, index, 0);
> + wa_ctx_emit(batch, index, 0);
> + wa_ctx_emit(batch, index, 0);
> + }
> +
> /* Pad to end of cacheline */
> while (index % CACHELINE_DWORDS)
> wa_ctx_emit(batch, index, MI_NOOP);
>
looks good to me,
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
regards
Arun
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prev parent reply other threads:[~2016-07-04 16:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-04 13:38 [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB tim.gore
2016-07-04 14:07 ` ✗ Ro.CI.BAT: failure for " Patchwork
2016-07-04 16:59 ` Arun Siluvery [this message]
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