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* [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
@ 2016-07-04 13:38 tim.gore
  2016-07-04 14:07 ` ✗ Ro.CI.BAT: failure for " Patchwork
  2016-07-04 16:59 ` [PATCH] " Arun Siluvery
  0 siblings, 2 replies; 3+ messages in thread
From: tim.gore @ 2016-07-04 13:38 UTC (permalink / raw)
  To: intel-gfx

From: Tim Gore <tim.gore@intel.com>

This patch applies WaMediaPoolStateCmdInWABB which fixes
a problem with the restoration of thread counts on resuming
from RC6.

Signed-off-by: Tim Gore <tim.gore@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 676b532..017b25c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1296,6 +1296,31 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
 		wa_ctx_emit(batch, index, 0);
 		wa_ctx_emit(batch, index, 0);
 	}
+
+	/* WaMediaPoolStateCmdInWABB:bxt */
+	if (HAS_POOLED_EU(engine->i915)) {
+		/*
+		 * EU pool configuration is setup along with golden context
+		 * during context initialization. This value depends on
+		 * device type (2x6 or 3x6) and needs to be updated based
+		 * on which subslice is disabled especially for 2x6
+		 * devices, however it is safe to load default
+		 * configuration of 3x6 device instead of masking off
+		 * corresponding bits because HW ignores bits of a disabled
+		 * subslice and drops down to appropriate config. Please
+		 * see render_state_setup() in i915_gem_render_state.c for
+		 * possible configurations, to avoid duplication they are
+		 * not shown here again.
+		 */
+		u32 eu_pool_config = 0x00777000;
+		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
+		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
+		wa_ctx_emit(batch, index, eu_pool_config);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+	}
+
 	/* Pad to end of cacheline */
 	while (index % CACHELINE_DWORDS)
 		wa_ctx_emit(batch, index, MI_NOOP);
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* ✗ Ro.CI.BAT: failure for drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
  2016-07-04 13:38 [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB tim.gore
@ 2016-07-04 14:07 ` Patchwork
  2016-07-04 16:59 ` [PATCH] " Arun Siluvery
  1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2016-07-04 14:07 UTC (permalink / raw)
  To: tim.gore; +Cc: intel-gfx

== Series Details ==

Series: drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
URL   : https://patchwork.freedesktop.org/series/9467/
State : failure

== Summary ==

Series 9467v1 drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
http://patchwork.freedesktop.org/api/1.0/series/9467/revisions/1/mbox

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-wb:
                pass       -> DMESG-FAIL (fi-skl-i5-6260u)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> FAIL       (ro-bdw-i7-5600u)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                dmesg-warn -> SKIP       (ro-bdw-i5-5250u)

fi-kbl-qkkr      total:231  pass:91   dwarn:21  dfail:3   fail:59  skip:57 
fi-skl-i5-6260u  total:231  pass:203  dwarn:0   dfail:1   fail:2   skip:25 
fi-skl-i7-6700k  total:103  pass:79   dwarn:0   dfail:0   fail:0   skip:23 
fi-snb-i7-2600   total:231  pass:176  dwarn:0   dfail:0   fail:2   skip:53 
ro-bdw-i5-5250u  total:229  pass:204  dwarn:1   dfail:1   fail:0   skip:23 
ro-bdw-i7-5600u  total:229  pass:189  dwarn:0   dfail:1   fail:1   skip:38 
ro-byt-n2820     total:229  pass:180  dwarn:0   dfail:1   fail:3   skip:45 
ro-hsw-i3-4010u  total:229  pass:197  dwarn:0   dfail:1   fail:0   skip:31 
ro-hsw-i7-4770r  total:229  pass:197  dwarn:0   dfail:1   fail:0   skip:31 
ro-ilk-i7-620lm  total:229  pass:157  dwarn:0   dfail:1   fail:1   skip:70 
ro-ilk1-i5-650   total:224  pass:157  dwarn:0   dfail:1   fail:1   skip:65 
ro-ivb-i7-3770   total:229  pass:188  dwarn:0   dfail:1   fail:0   skip:40 
ro-skl3-i5-6260u total:229  pass:112  dwarn:3   dfail:2   fail:74  skip:38 
ro-snb-i7-2620M  total:229  pass:179  dwarn:0   dfail:1   fail:1   skip:48 
ro-bdw-i7-5557U failed to connect after reboot
ro-bsw-n3050 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1402/

54c86e3 drm-intel-nightly: 2016y-07m-04d-11h-55m-58s UTC integration manifest
42110dd drm/i915:gen9: implement WaMediaPoolStateCmdInWABB

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^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
  2016-07-04 13:38 [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB tim.gore
  2016-07-04 14:07 ` ✗ Ro.CI.BAT: failure for " Patchwork
@ 2016-07-04 16:59 ` Arun Siluvery
  1 sibling, 0 replies; 3+ messages in thread
From: Arun Siluvery @ 2016-07-04 16:59 UTC (permalink / raw)
  To: tim.gore, intel-gfx

On 04/07/2016 14:38, tim.gore@intel.com wrote:
> From: Tim Gore <tim.gore@intel.com>
>
> This patch applies WaMediaPoolStateCmdInWABB which fixes
> a problem with the restoration of thread counts on resuming
> from RC6.
>
> Signed-off-by: Tim Gore <tim.gore@intel.com>

suggest adding hsd ref# to commit msg.

> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 676b532..017b25c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1296,6 +1296,31 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
>   		wa_ctx_emit(batch, index, 0);
>   		wa_ctx_emit(batch, index, 0);
>   	}
> +
> +	/* WaMediaPoolStateCmdInWABB:bxt */
> +	if (HAS_POOLED_EU(engine->i915)) {
> +		/*
> +		 * EU pool configuration is setup along with golden context
> +		 * during context initialization. This value depends on
> +		 * device type (2x6 or 3x6) and needs to be updated based
> +		 * on which subslice is disabled especially for 2x6
> +		 * devices, however it is safe to load default
> +		 * configuration of 3x6 device instead of masking off
> +		 * corresponding bits because HW ignores bits of a disabled
> +		 * subslice and drops down to appropriate config. Please
> +		 * see render_state_setup() in i915_gem_render_state.c for
> +		 * possible configurations, to avoid duplication they are
> +		 * not shown here again.
> +		 */
> +		u32 eu_pool_config = 0x00777000;
> +		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
> +		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
> +		wa_ctx_emit(batch, index, eu_pool_config);
> +		wa_ctx_emit(batch, index, 0);
> +		wa_ctx_emit(batch, index, 0);
> +		wa_ctx_emit(batch, index, 0);
> +	}
> +
>   	/* Pad to end of cacheline */
>   	while (index % CACHELINE_DWORDS)
>   		wa_ctx_emit(batch, index, MI_NOOP);
>

looks good to me,
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>

regards
Arun

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^ permalink raw reply	[flat|nested] 3+ messages in thread
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2016-07-04 13:38 [PATCH] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB tim.gore
2016-07-04 14:07 ` ✗ Ro.CI.BAT: failure for " Patchwork
2016-07-04 16:59 ` [PATCH] " Arun Siluvery

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