[PATCH] drm/i915: Enable FBC for non X-tiled FBs

[PATCH] drm/i915: Enable FBC for non X-tiled FBs

[Praveen Paneri]

FBC is only enabled for X-tiled framebuffers but there are
quite a few cases where we tend to use Y-tiled framebuffers.
So enabling it for non X-tiled framebuffers.

Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 ++
 drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc843f9..9d7a376 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2506,6 +2506,8 @@ enum skl_disp_power_wells {
 #define  BDW_FBC_COMPRESSION_MASK	0xfff
 
 #define FBC_LL_SIZE		(1536)
+#define FBC_YSTRIDE		_MMIO(0x4208c)
+#define   FBC_STRIDE_OVERRIDE	(1<<13)
 
 #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
 #define   FBC_LLC_FULLY_OPEN	(1<<30)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 17d418b..0ac9889 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -301,6 +301,14 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 	u32 dpfc_ctl;
 	int threshold = dev_priv->fbc.threshold;
 
+	if (INTEL_GEN(dev_priv) >= 9 &&
+	    i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
+		struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
+		int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
+					      (32 * threshold)) * 8;
+		I915_WRITE(FBC_YSTRIDE, FBC_STRIDE_OVERRIDE | cfb_stride);
+	}
+
 	dpfc_ctl = 0;
 	if (IS_IVYBRIDGE(dev_priv))
 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
-- 
1.9.1

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✗ Fi.CI.BAT: failure for drm/i915: Enable FBC for non X-tiled FBs

[Patchwork]

== Series Details ==

Series: drm/i915: Enable FBC for non X-tiled FBs
URL   : https://patchwork.freedesktop.org/series/21264/
State : failure

== Summary ==

  CC [M]  drivers/gpu/drm/i915/i915_vgpu.o
  CC [M]  drivers/gpu/drm/i915/i915_perf.o
  CC [M]  drivers/gpu/drm/i915/i915_oa_hsw.o
  CC [M]  drivers/gpu/drm/i915/intel_gvt.o
  CC [M]  drivers/gpu/drm/i915/gvt/gvt.o
  CC [M]  drivers/gpu/drm/i915/gvt/aperture_gm.o
  LD      net/key/built-in.o
  CC [M]  drivers/gpu/drm/i915/gvt/handlers.o
  CC [M]  drivers/gpu/drm/i915/gvt/vgpu.o
  CC [M]  drivers/gpu/drm/i915/gvt/trace_points.o
  LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
  CC [M]  drivers/gpu/drm/i915/gvt/firmware.o
  CC [M]  drivers/gpu/drm/i915/gvt/interrupt.o
  CC [M]  drivers/gpu/drm/i915/gvt/gtt.o
  CC [M]  drivers/gpu/drm/i915/gvt/cfg_space.o
  CC [M]  drivers/gpu/drm/i915/gvt/mmio.o
  CC [M]  drivers/gpu/drm/i915/gvt/opregion.o
  CC [M]  drivers/gpu/drm/i915/gvt/edid.o
  CC [M]  drivers/gpu/drm/i915/gvt/display.o
  LD      drivers/usb/gadget/libcomposite.o
  CC [M]  drivers/gpu/drm/i915/gvt/execlist.o
  CC [M]  drivers/gpu/drm/i915/gvt/scheduler.o
  CC [M]  drivers/gpu/drm/i915/gvt/sched_policy.o
  CC [M]  drivers/gpu/drm/i915/gvt/render.o
  CC [M]  drivers/gpu/drm/i915/gvt/cmd_parser.o
  CC [M]  drivers/gpu/drm/i915/intel_lpe_audio.o
  LD      net/netlink/built-in.o
  LD      drivers/usb/gadget/udc/udc-core.o
  LD      lib/raid6/raid6_pq.o
  LD      drivers/usb/gadget/udc/built-in.o
  LD      drivers/usb/gadget/built-in.o
  LD      lib/raid6/built-in.o
  LD      kernel/sched/built-in.o
  LD      drivers/pci/pcie/aer/aerdriver.o
  LD      drivers/pci/pcie/aer/built-in.o
  LD      kernel/built-in.o
  LD      drivers/pci/pcie/built-in.o
  LD      drivers/pci/built-in.o
  LD      drivers/video/console/built-in.o
  LD      drivers/video/built-in.o
  LD [M]  sound/pci/hda/snd-hda-codec-generic.o
  LD      sound/pci/built-in.o
  LD      drivers/gpu/drm/drm.o
  LD      drivers/scsi/sd_mod.o
  LD      drivers/scsi/built-in.o
  LD      sound/built-in.o
drivers/gpu/drm/i915/intel_fbc.c: In function ‘gen7_fbc_activate’:
drivers/gpu/drm/i915/intel_fbc.c:305:33: error: ‘cache’ undeclared (first use in this function)
      i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
                                 ^
drivers/gpu/drm/i915/intel_fbc.c:305:33: note: each undeclared identifier is reported only once for each function it appears in
  LD      net/unix/unix.o
  LD      net/unix/built-in.o
scripts/Makefile.build:294: recipe for target 'drivers/gpu/drm/i915/intel_fbc.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_fbc.o] Error 1
make[4]: *** Waiting for unfinished jobs....
  LD [M]  drivers/net/ethernet/intel/igb/igb.o
  LD      drivers/usb/core/usbcore.o
  LD      drivers/tty/serial/8250/8250_base.o
  LD      drivers/usb/core/built-in.o
  LD      drivers/tty/serial/8250/built-in.o
  LD      drivers/tty/serial/built-in.o
  LD      lib/lz4/built-in.o
  LD      drivers/md/md-mod.o
  LD      drivers/md/built-in.o
  LD      net/packet/built-in.o
  LD      drivers/tty/vt/built-in.o
  LD      drivers/tty/built-in.o
  LD      net/ipv6/ipv6.o
  LD      net/xfrm/built-in.o
  LD      net/ipv6/built-in.o
  AR      lib/lib.a
  EXPORTS lib/lib-ksyms.o
  CC      arch/x86/kernel/cpu/capflags.o
  LD      arch/x86/kernel/cpu/built-in.o
  LD      arch/x86/kernel/built-in.o
  LD      drivers/usb/host/xhci-hcd.o
  LD [M]  drivers/net/ethernet/intel/e1000e/e1000e.o
  LD      lib/built-in.o
  LD      drivers/usb/host/built-in.o
  LD      drivers/usb/built-in.o
  LD      arch/x86/built-in.o
  LD      fs/btrfs/btrfs.o
  LD      fs/btrfs/built-in.o
  LD      fs/ext4/ext4.o
  LD      fs/ext4/built-in.o
  LD      fs/built-in.o
  LD      net/core/built-in.o
  LD      net/ipv4/built-in.o
  LD      net/built-in.o
  LD      drivers/net/ethernet/built-in.o
  LD      drivers/net/built-in.o
scripts/Makefile.build:553: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:553: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:553: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1002: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[PATCH v2] drm/i915: Enable FBC for non X-tiled FBs

[Praveen Paneri]

FBC is only enabled for X-tiled framebuffers but there are
quite a few cases where we tend to use Y-tiled framebuffers.
So enabling it for non X-tiled framebuffers.

v2: Minor fix for a build error

Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 ++
 drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d88c35..ba398d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2506,6 +2506,8 @@ enum skl_disp_power_wells {
 #define  BDW_FBC_COMPRESSION_MASK	0xfff
 
 #define FBC_LL_SIZE		(1536)
+#define FBC_YSTRIDE		_MMIO(0x4208c)
+#define   FBC_STRIDE_OVERRIDE	(1<<13)
 
 #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
 #define   FBC_LLC_FULLY_OPEN	(1<<30)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index ded2add..d17b007 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -298,9 +298,17 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 {
 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+	struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
 	u32 dpfc_ctl;
 	int threshold = dev_priv->fbc.threshold;
 
+	if (INTEL_GEN(dev_priv) >= 9 &&
+	    i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
+		int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
+					      (32 * threshold)) * 8;
+		I915_WRITE(FBC_YSTRIDE, FBC_STRIDE_OVERRIDE | cfb_stride);
+	}
+
 	dpfc_ctl = 0;
 	if (IS_IVYBRIDGE(dev_priv))
 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
-- 
1.9.1

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✗ Fi.CI.BAT: failure for drm/i915: Enable FBC for non X-tiled FBs (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable FBC for non X-tiled FBs (rev2)
URL   : https://patchwork.freedesktop.org/series/21264/
State : failure

== Summary ==

Series 21264v2 drm/i915: Enable FBC for non X-tiled FBs
https://patchwork.freedesktop.org/api/1.0/series/21264/revisions/2/mbox/

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                pass       -> INCOMPLETE (fi-skl-6770hq) fdo#100130
        Subgroup basic-uc-pro-default:
                pass       -> INCOMPLETE (fi-skl-6260u)
                pass       -> INCOMPLETE (fi-skl-6700hq) fdo#100130
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2520m)

fdo#100130 https://bugs.freedesktop.org/show_bug.cgi?id=100130

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 452s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 526s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 511s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 549s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 498s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 498s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 437s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 482s
fi-skl-6260u     total:53   pass:51   dwarn:0   dfail:0   fail:0   skip:1   time: 0s
fi-skl-6700hq    total:53   pass:45   dwarn:0   dfail:0   fail:0   skip:7   time: 0s
fi-skl-6770hq    total:51   pass:49   dwarn:0   dfail:0   fail:0   skip:1   time: 0s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 550s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 418s

c641417b70c6b78efca29ae732d7cbf5716ac6d5 drm-tip: 2017y-03m-14d-16h-04m-56s UTC integration manifest
0d8a919 drm/i915: Enable FBC for non X-tiled FBs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4176/
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✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable FBC for non X-tiled FBs (rev2)
URL   : https://patchwork.freedesktop.org/series/21264/
State : success

== Summary ==

Series 21264v2 drm/i915: Enable FBC for non X-tiled FBs
https://patchwork.freedesktop.org/api/1.0/series/21264/revisions/2/mbox/

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                pass       -> INCOMPLETE (fi-skl-6770hq) fdo#100130
        Subgroup basic-uc-pro-default:
                pass       -> INCOMPLETE (fi-skl-6700hq) fdo#100130
                pass       -> INCOMPLETE (fi-skl-6260u) fdo#100130
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2520m)

fdo#100130 https://bugs.freedesktop.org/show_bug.cgi?id=100130

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 452s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 526s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 511s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 549s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 498s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 498s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 437s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 482s
fi-skl-6260u     total:53   pass:51   dwarn:0   dfail:0   fail:0   skip:1   time: 0s
fi-skl-6700hq    total:53   pass:45   dwarn:0   dfail:0   fail:0   skip:7   time: 0s
fi-skl-6770hq    total:51   pass:49   dwarn:0   dfail:0   fail:0   skip:1   time: 0s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 550s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 418s

c641417b70c6b78efca29ae732d7cbf5716ac6d5 drm-tip: 2017y-03m-14d-16h-04m-56s UTC integration manifest
0d8a919 drm/i915: Enable FBC for non X-tiled FBs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4176/
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Re: [PATCH] drm/i915: Enable FBC for non X-tiled FBs

[Ville Syrjälä]

On Wed, Mar 15, 2017 at 12:29:35PM +0530, Praveen Paneri wrote:
> FBC is only enabled for X-tiled framebuffers but there are
> quite a few cases where we tend to use Y-tiled framebuffers.
> So enabling it for non X-tiled framebuffers.

This patch doesn't actuall enable anything. In fact to me it looks like
we're already allowing Y tiling + FBC, so the commit message/subject should
likely say that you're fixing something.

Unless I'm missing some magic check somewhere that still prevents
Y tiled + FBC. But then this patch wouldn't be sufficient either.

> 
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
>  drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cc843f9..9d7a376 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2506,6 +2506,8 @@ enum skl_disp_power_wells {
>  #define  BDW_FBC_COMPRESSION_MASK	0xfff
>  
>  #define FBC_LL_SIZE		(1536)
> +#define FBC_YSTRIDE		_MMIO(0x4208c)
> +#define   FBC_STRIDE_OVERRIDE	(1<<13)

These defines shouldn't be in the middle of the FBC1 register defines.
The register should also be called CHICKEN_MISC_1, so the defines
should live next to the other CHICKEN_MISC register defines.

>  
>  #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
>  #define   FBC_LLC_FULLY_OPEN	(1<<30)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 17d418b..0ac9889 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -301,6 +301,14 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>  	u32 dpfc_ctl;
>  	int threshold = dev_priv->fbc.threshold;
>  
> +	if (INTEL_GEN(dev_priv) >= 9 &&

AFAICS IS_GEN9() would be better.

> +	    i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
> +		struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
> +		int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
> +					      (32 * threshold)) * 8;

Are we taking this compressed stride alignment requirement into account
when we allocate the cfb?

> +		I915_WRITE(FBC_YSTRIDE, FBC_STRIDE_OVERRIDE | cfb_stride);
> +	}
> +
>  	dpfc_ctl = 0;
>  	if (IS_IVYBRIDGE(dev_priv))
>  		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH] drm/i915: Enable FBC for non X-tiled FBs

[Praveen Paneri]

Hi Ville,

On Wednesday 15 March 2017 03:53 PM, Ville Syrjälä wrote:
> On Wed, Mar 15, 2017 at 12:29:35PM +0530, Praveen Paneri wrote:
>> FBC is only enabled for X-tiled framebuffers but there are
>> quite a few cases where we tend to use Y-tiled framebuffers.
>> So enabling it for non X-tiled framebuffers.
>
> This patch doesn't actuall enable anything. In fact to me it looks like
> we're already allowing Y tiling + FBC, so the commit message/subject should
> likely say that you're fixing something.
>
I agree! I can rename the patch as
Fix FBC Stride programming for Y-tiled FBs
> Unless I'm missing some magic check somewhere that still prevents
> Y tiled + FBC. But then this patch wouldn't be sufficient either.
We had a check to activate FBC only for X-tiled buffers but that has 
been removed by this patch.
https://patchwork.kernel.org/patch/9546759/

With this change, we don't know what would happen in case of Y-tiled 
buffer as it is suggested that Stride for Y-tiled buffers must be 
programmed by SW (Probably a HW bug/limitation).

>
>>
>> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h  | 2 ++
>>   drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
>>   2 files changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index cc843f9..9d7a376 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2506,6 +2506,8 @@ enum skl_disp_power_wells {
>>   #define  BDW_FBC_COMPRESSION_MASK	0xfff
>>
>>   #define FBC_LL_SIZE		(1536)
>> +#define FBC_YSTRIDE		_MMIO(0x4208c)
>> +#define   FBC_STRIDE_OVERRIDE	(1<<13)
>
> These defines shouldn't be in the middle of the FBC1 register defines.
> The register should also be called CHICKEN_MISC_1, so the defines
> should live next to the other CHICKEN_MISC register defines.
Will fix this
>
>>
>>   #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
>>   #define   FBC_LLC_FULLY_OPEN	(1<<30)
>> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
>> index 17d418b..0ac9889 100644
>> --- a/drivers/gpu/drm/i915/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/intel_fbc.c
>> @@ -301,6 +301,14 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>>   	u32 dpfc_ctl;
>>   	int threshold = dev_priv->fbc.threshold;
>>
>> +	if (INTEL_GEN(dev_priv) >= 9 &&
>
> AFAICS IS_GEN9() would be better.
Yes!
>
>> +	    i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
>> +		struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
>> +		int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
>> +					      (32 * threshold)) * 8;
>
> Are we taking this compressed stride alignment requirement into account
> when we allocate the cfb?
cfb size is calculated as (line * cache->fb.stride) but cfb is allocated 
as per the original FB size (threshold = 1) where stride would be higher 
than what is calculated here. Would we still need to take care of the 
alignment?

Thanks,
Praveen
>
>> +		I915_WRITE(FBC_YSTRIDE, FBC_STRIDE_OVERRIDE | cfb_stride);
>> +	}
>> +
>>   	dpfc_ctl = 0;
>>   	if (IS_IVYBRIDGE(dev_priv))
>>   		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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[PATCH v3] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Praveen Paneri]

When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
surfaces on gen9, the cfb stride must be programmed by SW as

cfb_stride = ceiling[(at least plane width in pixels)/
		     (32 * compression limit factor)] * 8

v2: Minor fix for a build error

v3: Fixed subject, register name and platform check (Ville)

Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d88c35..f4f0cb5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6506,6 +6506,9 @@ enum {
 #define  GLK_CL1_PWR_DOWN	(1 << 11)
 #define  GLK_CL2_PWR_DOWN	(1 << 12)
 
+#define CHICKEN_MISC_4		_MMIO(0x4208c)
+#define   FBC_STRIDE_OVERRIDE	(1<<13)
+
 #define _CHICKEN_PIPESL_1_A	0x420b0
 #define _CHICKEN_PIPESL_1_B	0x420b4
 #define  HSW_FBCQ_DIS			(1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index ded2add..e7f259f 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -298,9 +298,17 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 {
 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+	struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
 	u32 dpfc_ctl;
 	int threshold = dev_priv->fbc.threshold;
 
+	if (IS_GEN9(dev_priv) &&
+	    i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
+		int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
+					      (32 * threshold)) * 8;
+		I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE | cfb_stride);
+	}
+
 	dpfc_ctl = 0;
 	if (IS_IVYBRIDGE(dev_priv))
 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
-- 
1.9.1

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✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable FBC for non X-tiled FBs (rev3)
URL   : https://patchwork.freedesktop.org/series/21264/
State : success

== Summary ==

Series 21264v3 drm/i915: Enable FBC for non X-tiled FBs
https://patchwork.freedesktop.org/api/1.0/series/21264/revisions/3/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> DMESG-WARN (fi-bxt-t5700) fdo#100125

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 465s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 585s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 538s
fi-bxt-t5700     total:278  pass:257  dwarn:1   dfail:0   fail:0   skip:20  time: 550s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 500s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 435s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 432s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 435s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 507s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 498s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 484s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 598s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 484s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 522s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 550s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 417s
fi-byt-j1900 failed to collect. IGT log at Patchwork_4199/fi-byt-j1900/igt.log
fi-kbl-7500u failed to connect after reboot

10fb1e7b1a08adce1b8db7186c5eb28dea8a2b97 drm-tip: 2017y-03m-16d-10h-44m-23s UTC integration manifest
440ada4 drm/i915: Fix FBC cfb stride programming for non X-tiled FB

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4199/
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Re: [PATCH v3] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Paulo Zanoni]

Em Qui, 2017-03-16 às 17:38 +0530, Praveen Paneri escreveu:
> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
> surfaces on gen9, the cfb stride must be programmed by SW as
> 
> cfb_stride = ceiling[(at least plane width in pixels)/
> 		     (32 * compression limit factor)] * 8
> 
> v2: Minor fix for a build error
> 
> v3: Fixed subject, register name and platform check (Ville)
> 
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
>  drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5d88c35..f4f0cb5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6506,6 +6506,9 @@ enum {
>  #define  GLK_CL1_PWR_DOWN	(1 << 11)
>  #define  GLK_CL2_PWR_DOWN	(1 << 12)
>  
> +#define CHICKEN_MISC_4		_MMIO(0x4208c)
> +#define   FBC_STRIDE_OVERRIDE	(1<<13)
> +
>  #define _CHICKEN_PIPESL_1_A	0x420b0
>  #define _CHICKEN_PIPESL_1_B	0x420b4
>  #define  HSW_FBCQ_DIS			(1 << 22)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index ded2add..e7f259f 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -298,9 +298,17 @@ static bool ilk_fbc_is_active(struct
> drm_i915_private *dev_priv)
>  static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> +	struct intel_fbc_state_cache *cache = &dev_priv-
> >fbc.state_cache;
>  	u32 dpfc_ctl;
>  	int threshold = dev_priv->fbc.threshold;
>  

Please add:

/* Display WA #0529: skl, kbl, bxt, glk. */

(and if you find the real name of the WA, please also add it)

I wanted to give this patch a try with kms_frontbuffer_tracking, but I
just couldn't find your IGT patch where Y tiling support is added to
it. I can see your patches that touch lib/igt_draw and kms_draw_crc,
but no patches testing kms_frontbuffer_tracking. Can you please send me
the patchwork link?

The corollary of the paragraph above is the question: do we maintain
the same pass rate as X tiling when we test it against Y tiling now?

My original goal was to block FBC Y tiling support until we added the
IGT stuff, but I see it was already enabled by someone even though we
didn't have the missing WA nor the IGT stuff... Oh, well....

> +	if (IS_GEN9(dev_priv) &&
> +	    i915_gem_object_get_tiling(cache->vma->obj) !=
> I915_TILING_X) {
> +		int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
> +					      (32 * threshold)) * 8;
> +		I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE |
> cfb_stride);
> +	}
> +
>  	dpfc_ctl = 0;
>  	if (IS_IVYBRIDGE(dev_priv))
>  		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
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Re: [PATCH] drm/i915: Enable FBC for non X-tiled FBs

[Ville Syrjälä]

On Thu, Mar 16, 2017 at 05:07:26PM +0530, Praveen Paneri wrote:
> Hi Ville,
> 
> On Wednesday 15 March 2017 03:53 PM, Ville Syrjälä wrote:
> > On Wed, Mar 15, 2017 at 12:29:35PM +0530, Praveen Paneri wrote:
> >> FBC is only enabled for X-tiled framebuffers but there are
> >> quite a few cases where we tend to use Y-tiled framebuffers.
> >> So enabling it for non X-tiled framebuffers.
> >
> > This patch doesn't actuall enable anything. In fact to me it looks like
> > we're already allowing Y tiling + FBC, so the commit message/subject should
> > likely say that you're fixing something.
> >
> I agree! I can rename the patch as
> Fix FBC Stride programming for Y-tiled FBs
> > Unless I'm missing some magic check somewhere that still prevents
> > Y tiled + FBC. But then this patch wouldn't be sufficient either.
> We had a check to activate FBC only for X-tiled buffers but that has 
> been removed by this patch.
> https://patchwork.kernel.org/patch/9546759/
> 
> With this change, we don't know what would happen in case of Y-tiled 
> buffer as it is suggested that Stride for Y-tiled buffers must be 
> programmed by SW (Probably a HW bug/limitation).
> 
> >
> >>
> >> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_reg.h  | 2 ++
> >>   drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
> >>   2 files changed, 10 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index cc843f9..9d7a376 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -2506,6 +2506,8 @@ enum skl_disp_power_wells {
> >>   #define  BDW_FBC_COMPRESSION_MASK	0xfff
> >>
> >>   #define FBC_LL_SIZE		(1536)
> >> +#define FBC_YSTRIDE		_MMIO(0x4208c)
> >> +#define   FBC_STRIDE_OVERRIDE	(1<<13)
> >
> > These defines shouldn't be in the middle of the FBC1 register defines.
> > The register should also be called CHICKEN_MISC_1, so the defines
> > should live next to the other CHICKEN_MISC register defines.
> Will fix this
> >
> >>
> >>   #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
> >>   #define   FBC_LLC_FULLY_OPEN	(1<<30)
> >> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> >> index 17d418b..0ac9889 100644
> >> --- a/drivers/gpu/drm/i915/intel_fbc.c
> >> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> >> @@ -301,6 +301,14 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
> >>   	u32 dpfc_ctl;
> >>   	int threshold = dev_priv->fbc.threshold;
> >>
> >> +	if (INTEL_GEN(dev_priv) >= 9 &&
> >
> > AFAICS IS_GEN9() would be better.
> Yes!
> >
> >> +	    i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
> >> +		struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
> >> +		int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
> >> +					      (32 * threshold)) * 8;
> >
> > Are we taking this compressed stride alignment requirement into account
> > when we allocate the cfb?
> cfb size is calculated as (line * cache->fb.stride) but cfb is allocated 
> as per the original FB size (threshold = 1) where stride would be higher 
> than what is calculated here. Would we still need to take care of the 
> alignment?

I don't know. The cfb allocation code is too hard to follow so I've
decided not to even try.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v3] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Praveen Paneri]

On Fri, Mar 17, 2017 at 1:24 AM, Paulo Zanoni <paulo.r.zanoni@intel.com> wrote:
> Em Qui, 2017-03-16 às 17:38 +0530, Praveen Paneri escreveu:
>> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
>> surfaces on gen9, the cfb stride must be programmed by SW as
>>
>> cfb_stride = ceiling[(at least plane width in pixels)/
>>                    (32 * compression limit factor)] * 8
>>
>> v2: Minor fix for a build error
>>
>> v3: Fixed subject, register name and platform check (Ville)
>>
>> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
>>  drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
>>  2 files changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 5d88c35..f4f0cb5 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6506,6 +6506,9 @@ enum {
>>  #define  GLK_CL1_PWR_DOWN    (1 << 11)
>>  #define  GLK_CL2_PWR_DOWN    (1 << 12)
>>
>> +#define CHICKEN_MISC_4               _MMIO(0x4208c)
>> +#define   FBC_STRIDE_OVERRIDE        (1<<13)
>> +
>>  #define _CHICKEN_PIPESL_1_A  0x420b0
>>  #define _CHICKEN_PIPESL_1_B  0x420b4
>>  #define  HSW_FBCQ_DIS                        (1 << 22)
>> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
>> b/drivers/gpu/drm/i915/intel_fbc.c
>> index ded2add..e7f259f 100644
>> --- a/drivers/gpu/drm/i915/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/intel_fbc.c
>> @@ -298,9 +298,17 @@ static bool ilk_fbc_is_active(struct
>> drm_i915_private *dev_priv)
>>  static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>>  {
>>       struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
>> +     struct intel_fbc_state_cache *cache = &dev_priv-
>> >fbc.state_cache;
>>       u32 dpfc_ctl;
>>       int threshold = dev_priv->fbc.threshold;
>>
>
> Please add:
>
> /* Display WA #0529: skl, kbl, bxt, glk. */
>
> (and if you find the real name of the WA, please also add it)
>
> I wanted to give this patch a try with kms_frontbuffer_tracking, but I
> just couldn't find your IGT patch where Y tiling support is added to
> it. I can see your patches that touch lib/igt_draw and kms_draw_crc,
> but no patches testing kms_frontbuffer_tracking. Can you please send me
> the patchwork link?
It was just lying in my PC. I wasn't sure about the last patch for kms_fbc_crc.
Nevertheless just posted the series here
https://patchwork.kernel.org/patch/9631479/
Plz review.

>
> The corollary of the paragraph above is the question: do we maintain
> the same pass rate as X tiling when we test it against Y tiling now?
Yes we do :)
>
> My original goal was to block FBC Y tiling support until we added the
> IGT stuff, but I see it was already enabled by someone even though we
> didn't have the missing WA nor the IGT stuff... Oh, well....
Anyway! hopefully we will catch-up and fix this soon
Thanks,
Praveen
>
>> +     if (IS_GEN9(dev_priv) &&
>> +         i915_gem_object_get_tiling(cache->vma->obj) !=
>> I915_TILING_X) {
>> +             int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
>> +                                           (32 * threshold)) * 8;
>> +             I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE |
>> cfb_stride);
>> +     }
>> +
>>       dpfc_ctl = 0;
>>       if (IS_IVYBRIDGE(dev_priv))
>>               dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
> _______________________________________________
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Re: [PATCH] drm/i915: Enable FBC for non X-tiled FBs

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 2942 bytes --]

Hi Praveen,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.11-rc2 next-20170310]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Praveen-Paneri/drm-i915-Enable-FBC-for-non-X-tiled-FBs/20170318-084727
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x003-201711 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All error/warnings (new ones prefixed by >>):

   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/async.h:15,
                    from drivers/gpu/drm/i915/intel_drv.h:28,
                    from drivers/gpu/drm/i915/intel_fbc.c:41:
   drivers/gpu/drm/i915/intel_fbc.c: In function 'gen7_fbc_activate':
>> drivers/gpu/drm/i915/intel_fbc.c:305:33: error: 'cache' undeclared (first use in this function)
         i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
                                    ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_fbc.c:304:2: note: in expansion of macro 'if'
     if (INTEL_GEN(dev_priv) >= 9 &&
     ^~
   drivers/gpu/drm/i915/intel_fbc.c:305:33: note: each undeclared identifier is reported only once for each function it appears in
         i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
                                    ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_fbc.c:304:2: note: in expansion of macro 'if'
     if (INTEL_GEN(dev_priv) >= 9 &&
     ^~

vim +/cache +305 drivers/gpu/drm/i915/intel_fbc.c

   298	static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
   299	{
   300		struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
   301		u32 dpfc_ctl;
   302		int threshold = dev_priv->fbc.threshold;
   303	
 > 304		if (INTEL_GEN(dev_priv) >= 9 &&
 > 305		    i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
   306			struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
   307			int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
   308						      (32 * threshold)) * 8;

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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[PATCH v4] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Praveen Paneri]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 2069 bytes --]

When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
surfaces on gen9, the cfb stride must be programmed by SW as

cfb_stride = ceiling[(at least plane width in pixels)/
		     (32 * compression limit factor)] * 8

v2: Minor fix for a build error

v3: Fixed subject, register name and platform check (Ville)

v4: Added WA details in comment (Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_fbc.c | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04c8f69..4adf2e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6504,6 +6504,9 @@ enum {
 #define  GLK_CL1_PWR_DOWN	(1 << 11)
 #define  GLK_CL2_PWR_DOWN	(1 << 12)
 
+#define CHICKEN_MISC_4		_MMIO(0x4208c)
+#define   FBC_STRIDE_OVERRIDE	(1<<13)
+
 #define _CHICKEN_PIPESL_1_A	0x420b0
 #define _CHICKEN_PIPESL_1_B	0x420b4
 #define  HSW_FBCQ_DIS			(1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index ded2add..1183633 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -298,9 +298,18 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 {
 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+	struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
 	u32 dpfc_ctl;
 	int threshold = dev_priv->fbc.threshold;
 
+	/* Display WA #0529: skl, kbl, bxt, glk */
+	if (IS_GEN9(dev_priv) &&
+	    i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
+		int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
+					      (32 * threshold)) * 8;
+		I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE | cfb_stride);
+	}
+
 	dpfc_ctl = 0;
 	if (IS_IVYBRIDGE(dev_priv))
 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
-- 
1.9.1


[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable FBC for non X-tiled FBs (rev4)
URL   : https://patchwork.freedesktop.org/series/21264/
State : success

== Summary ==

Series 21264v4 drm/i915: Enable FBC for non X-tiled FBs
https://patchwork.freedesktop.org/api/1.0/series/21264/revisions/4/mbox/

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 460s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time: 466s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 590s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 540s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 559s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 506s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 509s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 437s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 431s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 438s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 516s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 491s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 485s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 476s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 600s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 493s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 520s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time: 456s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 550s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 414s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC integration manifest
e61d48d drm/i915: Fix FBC cfb stride programming for non X-tiled FB

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4292/
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Re: [PATCH v4] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Paulo Zanoni]

Em Sex, 2017-03-24 às 17:12 +0530, Praveen Paneri escreveu:
> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
> surfaces on gen9, the cfb stride must be programmed by SW as
> 
> cfb_stride = ceiling[(at least plane width in pixels)/
> 		     (32 * compression limit factor)] * 8
> 
> v2: Minor fix for a build error
> 
> v3: Fixed subject, register name and platform check (Ville)
> 
> v4: Added WA details in comment (Paulo)
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 3 +++
>  drivers/gpu/drm/i915/intel_fbc.c | 9 +++++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 04c8f69..4adf2e6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6504,6 +6504,9 @@ enum {
>  #define  GLK_CL1_PWR_DOWN	(1 << 11)
>  #define  GLK_CL2_PWR_DOWN	(1 << 12)
>  
> +#define CHICKEN_MISC_4		_MMIO(0x4208c)
> +#define   FBC_STRIDE_OVERRIDE	(1<<13)
> +
>  #define _CHICKEN_PIPESL_1_A	0x420b0
>  #define _CHICKEN_PIPESL_1_B	0x420b4
>  #define  HSW_FBCQ_DIS			(1 << 22)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index ded2add..1183633 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -298,9 +298,18 @@ static bool ilk_fbc_is_active(struct
> drm_i915_private *dev_priv)
>  static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> +	struct intel_fbc_state_cache *cache = &dev_priv-
> >fbc.state_cache;

Please take a look at b183b3f14395. We need to store the calculated
stride value in reg_params so the stride value can actually be taken
into consideration when comparing different FBC configurations.


>  	u32 dpfc_ctl;
>  	int threshold = dev_priv->fbc.threshold;
>  
> +	/* Display WA #0529: skl, kbl, bxt, glk */
> +	if (IS_GEN9(dev_priv) &&

AFAIU, this WA shouldn't be applied for GLK.


> +	    i915_gem_object_get_tiling(cache->vma->obj) !=
> I915_TILING_X) {
> +		int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
> +					      (32 * threshold)) * 8;
> +		I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE |
> cfb_stride);

We need to zero those bits when we're not using Y tiling. I mean, at
least bit 13.

Also, CHICKEN_MISC_4 contains other fields not touched here, so we
should probably do a read-modify-write on it, preserving everything
we're not touching.

Thanks,
Paulo


> +	}
> +
>  	dpfc_ctl = 0;
>  	if (IS_IVYBRIDGE(dev_priv))
>  		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
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[PATCH v5] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Praveen Paneri]

When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
surfaces on gen9, the cfb stride must be programmed by SW as

cfb_stride = ceiling[(at least plane width in pixels)/
		     (32 * compression limit factor)] * 8

v2: Minor fix for a build error
v3: Fixed subject, register name and platform check (Ville)
v4: Added WA details in comment (Paulo)
v5:
 - Read modified reg write to preserve other bit values (Paulo)
 - Store modified stride value in reg_params (Paulo)
 - Keep GLK out of the WA (Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_fbc.c | 19 +++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c712d01..9e65f34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6710,6 +6710,9 @@ enum {
 #define CHICKEN_MISC_2		_MMIO(0x42084)
 #define  COMP_PWR_DOWN		(1 << 23)
 
+#define CHICKEN_MISC_4		_MMIO(0x4208c)
+#define   FBC_STRIDE_OVERRIDE	(1<<13)
+
 #define _CHICKEN_PIPESL_1_A	0x420b0
 #define _CHICKEN_PIPESL_1_B	0x420b4
 #define  HSW_FBCQ_DIS			(1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 860b8c2..251d3f4 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -288,9 +288,28 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 {
 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+	struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
 	u32 dpfc_ctl;
 	int threshold = dev_priv->fbc.threshold;
 
+	/* Display WA #0529: skl, kbl, bxt but not for glk*/
+	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
+		u32 chicken_misc4 = I915_READ(CHICKEN_MISC_4);
+
+		if (i915_gem_object_get_tiling(cache->vma->obj)
+				!= I915_TILING_X) {
+			int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
+					 (32 * threshold)) * 8;
+			params->fb.stride = cfb_stride;
+
+			I915_WRITE(CHICKEN_MISC_4, chicken_misc4 |
+					FBC_STRIDE_OVERRIDE | cfb_stride);
+		} else {
+			I915_WRITE(CHICKEN_MISC_4, chicken_misc4 &
+					~FBC_STRIDE_OVERRIDE);
+		}
+	}
+
 	dpfc_ctl = 0;
 	if (IS_IVYBRIDGE(dev_priv))
 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
-- 
1.9.1

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✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable FBC for non X-tiled FBs (rev5)
URL   : https://patchwork.freedesktop.org/series/21264/
State : success

== Summary ==

Series 21264v5 drm/i915: Enable FBC for non X-tiled FBs
https://patchwork.freedesktop.org/api/1.0/series/21264/revisions/5/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                pass       -> DMESG-WARN (fi-byt-n2820) fdo#101705

fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:443s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:429s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:355s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:532s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:510s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:491s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:487s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:594s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:441s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:412s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:412s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:494s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:494s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:462s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:585s
fi-kbl-r         total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  time:577s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:564s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:455s
fi-skl-6700hq    total:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  time:586s
fi-skl-6700k     total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  time:465s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:472s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:432s
fi-skl-x1585l    total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:468s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:541s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:409s

10de1e17faaab452782e5a1baffd1b30a639a261 drm-tip: 2017y-07m-18d-10h-08m-42s UTC integration manifest
ee3e000 drm/i915: Fix FBC cfb stride programming for non X-tiled FB

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5226/
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Re: [PATCH v5] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Paulo Zanoni]

Em Qua, 2017-07-19 às 00:27 +0530, Praveen Paneri escreveu:
> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
> surfaces on gen9, the cfb stride must be programmed by SW as
> 
> cfb_stride = ceiling[(at least plane width in pixels)/
> 		     (32 * compression limit factor)] * 8
> 
> v2: Minor fix for a build error
> v3: Fixed subject, register name and platform check (Ville)
> v4: Added WA details in comment (Paulo)
> v5:
>  - Read modified reg write to preserve other bit values (Paulo)
>  - Store modified stride value in reg_params (Paulo)
>  - Keep GLK out of the WA (Paulo)
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
>  drivers/gpu/drm/i915/intel_fbc.c | 19 +++++++++++++++++++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c712d01..9e65f34 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6710,6 +6710,9 @@ enum {
>  #define CHICKEN_MISC_2		_MMIO(0x42084)
>  #define  COMP_PWR_DOWN		(1 << 23)
>  
> +#define CHICKEN_MISC_4		_MMIO(0x4208c)
> +#define   FBC_STRIDE_OVERRIDE	(1<<13)
> +
>  #define _CHICKEN_PIPESL_1_A	0x420b0
>  #define _CHICKEN_PIPESL_1_B	0x420b4
>  #define  HSW_FBCQ_DIS			(1 << 22)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index 860b8c2..251d3f4 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -288,9 +288,28 @@ static bool ilk_fbc_is_active(struct
> drm_i915_private *dev_priv)
>  static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> +	struct intel_fbc_state_cache *cache = &dev_priv-
> >fbc.state_cache;
>  	u32 dpfc_ctl;
>  	int threshold = dev_priv->fbc.threshold;
>  
> +	/* Display WA #0529: skl, kbl, bxt but not for glk*/
> +	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
> +		u32 chicken_misc4 = I915_READ(CHICKEN_MISC_4);
> +
> +		if (i915_gem_object_get_tiling(cache->vma->obj)

params->vma->obj


> +				!= I915_TILING_X) {
> +			int cfb_stride = DIV_ROUND_UP(cache-
> >plane.src_w,
> +					 (32 * threshold)) * 8;
> +			params->fb.stride = cfb_stride;

Setting this here is too late. We need to do this in the same place as
we generate the other params.

> +
> +			I915_WRITE(CHICKEN_MISC_4, chicken_misc4 |
> +					FBC_STRIDE_OVERRIDE |
> cfb_stride);

This code is forgetting to mask the values it's going to replace.

> +		} else {
> +			I915_WRITE(CHICKEN_MISC_4, chicken_misc4 &
> +					~FBC_STRIDE_OVERRIDE);
> +		}
> +	}
> +
>  	dpfc_ctl = 0;
>  	if (IS_IVYBRIDGE(dev_priv))
>  		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
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[PATCH v6] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Praveen Paneri]

When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
surfaces on gen9, the cfb stride must be programmed by SW as

cfb_stride = ceiling[(at least plane width in pixels)/
		     (32 * compression limit factor)] * 8

v2: Minor fix for a build error
v3: Fixed subject, register name and platform check (Ville)
v4: Added WA details in comment (Paulo)
v5:
 - Read modified reg write to preserve other bit values (Paulo)
 - Store modified stride value in reg_params (Paulo)
 - Keep GLK out of the WA (Paulo)
v6:
 - added additional field in reg_params for gen9_wa_cfb_stride (Paulo)
 - Used appropriate bit mask while writing the register (Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
 drivers/gpu/drm/i915/intel_fbc.c | 27 +++++++++++++++++++++++++++
 3 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 907603c..1d40a7c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1106,6 +1106,7 @@ struct intel_fbc {
 		} fb;
 
 		int cfb_size;
+		unsigned int gen9_wa_cfb_stride;
 	} params;
 
 	struct intel_fbc_work {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 56df86e..51cab2f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6801,6 +6801,10 @@ enum {
 #define  GLK_CL1_PWR_DOWN	(1 << 11)
 #define  GLK_CL0_PWR_DOWN	(1 << 10)
 
+#define CHICKEN_MISC_4		_MMIO(0x4208c)
+#define   FBC_STRIDE_OVERRIDE	(1<<13)
+#define   FBC_STRIDE_MASK	0x1FFF
+
 #define _CHICKEN_PIPESL_1_A	0x420b0
 #define _CHICKEN_PIPESL_1_B	0x420b4
 #define  HSW_FBCQ_DIS			(1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 860b8c2..21f6b33 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -291,6 +291,21 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 	u32 dpfc_ctl;
 	int threshold = dev_priv->fbc.threshold;
 
+	/* Display WA #0529: skl, kbl, bxt but not for glk*/
+	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
+		u32 chicken_misc4 = I915_READ(CHICKEN_MISC_4);
+
+		if (i915_gem_object_get_tiling(params->vma->obj)
+				!= I915_TILING_X) {
+                       I915_WRITE(CHICKEN_MISC_4, chicken_misc4 |
+                               FBC_STRIDE_OVERRIDE |
+                               (params->gen9_wa_cfb_stride & FBC_STRIDE_MASK));
+		} else {
+			I915_WRITE(CHICKEN_MISC_4, chicken_misc4 &
+				~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK));
+		}
+	}
+
 	dpfc_ctl = 0;
 	if (IS_IVYBRIDGE(dev_priv))
 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
@@ -865,6 +880,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
 	struct intel_fbc_state_cache *cache = &fbc->state_cache;
+	int threshold = dev_priv->fbc.threshold;
 
 	/* Since all our fields are integer types, use memset here so the
 	 * comparison function can rely on memcmp because the padding will be
@@ -880,6 +896,17 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 	params->fb.format = cache->fb.format;
 	params->fb.stride = cache->fb.stride;
 
+	/* Display WA #0529: skl, kbl, bxt but not for glk*/
+	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
+		/* calculate cfb stride for y-tiled mode */
+		if (i915_gem_object_get_tiling(params->vma->obj)
+				!= I915_TILING_X) {
+			int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
+					(32 * threshold)) * 8;
+			params->gen9_wa_cfb_stride = cfb_stride;
+		}
+	}
+
 	params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 }
 
-- 
1.9.1

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✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable FBC for non X-tiled FBs (rev6)
URL   : https://patchwork.freedesktop.org/series/21264/
State : success

== Summary ==

Series 21264v6 drm/i915: Enable FBC for non X-tiled FBs
https://patchwork.freedesktop.org/api/1.0/series/21264/revisions/6/mbox/

Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                fail       -> PASS       (fi-snb-2600) fdo#100215

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:448s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:429s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:358s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:546s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:515s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:528s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:506s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:602s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:448s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:424s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:420s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:507s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:482s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:476s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:586s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:590s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:524s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:463s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:473s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:483s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:438s
fi-skl-x1585l    total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:479s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:549s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:403s

a8f0812284aa77e62aba1e4b430ac3bc090f43d0 drm-tip: 2017y-08m-11d-07h-22m-37s UTC integration manifest
c08d90cbd2c0 drm/i915: Fix FBC cfb stride programming for non X-tiled FB

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5370/
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Re: [PATCH v6] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Paulo Zanoni]

Em Sex, 2017-08-11 às 00:00 +0530, Praveen Paneri escreveu:
> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
> surfaces on gen9, the cfb stride must be programmed by SW as
> 
> cfb_stride = ceiling[(at least plane width in pixels)/
> 		     (32 * compression limit factor)] * 8
> 
> v2: Minor fix for a build error
> v3: Fixed subject, register name and platform check (Ville)
> v4: Added WA details in comment (Paulo)
> v5:
>  - Read modified reg write to preserve other bit values (Paulo)
>  - Store modified stride value in reg_params (Paulo)
>  - Keep GLK out of the WA (Paulo)
> v6:
>  - added additional field in reg_params for gen9_wa_cfb_stride
> (Paulo)
>  - Used appropriate bit mask while writing the register (Paulo)
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>  drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
>  drivers/gpu/drm/i915/intel_fbc.c | 27 +++++++++++++++++++++++++++
>  3 files changed, 32 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 907603c..1d40a7c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1106,6 +1106,7 @@ struct intel_fbc {
>  		} fb;
>  
>  		int cfb_size;
> +		unsigned int gen9_wa_cfb_stride;
>  	} params;
>  
>  	struct intel_fbc_work {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 56df86e..51cab2f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6801,6 +6801,10 @@ enum {
>  #define  GLK_CL1_PWR_DOWN	(1 << 11)
>  #define  GLK_CL0_PWR_DOWN	(1 << 10)
>  
> +#define CHICKEN_MISC_4		_MMIO(0x4208c)
> +#define   FBC_STRIDE_OVERRIDE	(1<<13)

See the new comment at the top of this file. (1 << 13) is preferred.


> +#define   FBC_STRIDE_MASK	0x1FFF
> +
>  #define _CHICKEN_PIPESL_1_A	0x420b0
>  #define _CHICKEN_PIPESL_1_B	0x420b4
>  #define  HSW_FBCQ_DIS			(1 << 22)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index 860b8c2..21f6b33 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -291,6 +291,21 @@ static void gen7_fbc_activate(struct
> drm_i915_private *dev_priv)
>  	u32 dpfc_ctl;
>  	int threshold = dev_priv->fbc.threshold;
>  
> +	/* Display WA #0529: skl, kbl, bxt but not for glk*/

Don't need to list excluded platforms. Also, missing space before the
asterisk.


> +	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
> +		u32 chicken_misc4 = I915_READ(CHICKEN_MISC_4);

In our driver, variables with the name of register usually contain its
address. We generally use "val" for values.


> +
> +		if (i915_gem_object_get_tiling(params->vma->obj)
> +				!= I915_TILING_X) {
> +                       I915_WRITE(CHICKEN_MISC_4, chicken_misc4 |
> +                               FBC_STRIDE_OVERRIDE |
> +                               (params->gen9_wa_cfb_stride &
> FBC_STRIDE_MASK));

We're not masking the old value before overwriting it, eventually
everything is going to be 0xFFF if we keep changing the stride without
disabling it.


> +		} else {
> +			I915_WRITE(CHICKEN_MISC_4, chicken_misc4 &
> +				~(FBC_STRIDE_OVERRIDE |
> FBC_STRIDE_MASK));
> +		}
> +	}
> +

Major issue with spaces instead of tabs in the whole chunk above.


>  	dpfc_ctl = 0;
>  	if (IS_IVYBRIDGE(dev_priv))
>  		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
> @@ -865,6 +880,7 @@ static void intel_fbc_get_reg_params(struct
> intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_fbc *fbc = &dev_priv->fbc;
>  	struct intel_fbc_state_cache *cache = &fbc->state_cache;
> +	int threshold = dev_priv->fbc.threshold;
>  
>  	/* Since all our fields are integer types, use memset here
> so the
>  	 * comparison function can rely on memcmp because the
> padding will be
> @@ -880,6 +896,17 @@ static void intel_fbc_get_reg_params(struct
> intel_crtc *crtc,
>  	params->fb.format = cache->fb.format;
>  	params->fb.stride = cache->fb.stride;
>  
> +	/* Display WA #0529: skl, kbl, bxt but not for glk*/
> +	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
> +		/* calculate cfb stride for y-tiled mode */
> +		if (i915_gem_object_get_tiling(params->vma->obj)
> +				!= I915_TILING_X) {

We don't need the check here, it's already done in the other part of
the code.

Anyway, to save time on yet another iteration of this patch I went
ahead and fixed the styling issues and the masking problem and merged
the patch. Thanks for the patch!

> +			int cfb_stride = DIV_ROUND_UP(cache-
> >plane.src_w,
> +					(32 * threshold)) * 8;
> +			params->gen9_wa_cfb_stride = cfb_stride;
> +		}
> +	}
> +
>  	params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv,
> cache);
>  }
>  
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Re: [PATCH v6] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Praveen Paneri]

Hi Paulo,

Thank you for the review and fix-ups :)

regards,
Praveen

On Saturday 26 August 2017 06:19 AM, Paulo Zanoni wrote:
> Em Sex, 2017-08-11 às 00:00 +0530, Praveen Paneri escreveu:
>> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
>> surfaces on gen9, the cfb stride must be programmed by SW as
>>
>> cfb_stride = ceiling[(at least plane width in pixels)/
>> 		     (32 * compression limit factor)] * 8
>>
>> v2: Minor fix for a build error
>> v3: Fixed subject, register name and platform check (Ville)
>> v4: Added WA details in comment (Paulo)
>> v5:
>>  - Read modified reg write to preserve other bit values (Paulo)
>>  - Store modified stride value in reg_params (Paulo)
>>  - Keep GLK out of the WA (Paulo)
>> v6:
>>  - added additional field in reg_params for gen9_wa_cfb_stride
>> (Paulo)
>>  - Used appropriate bit mask while writing the register (Paulo)
>>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>>  drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
>>  drivers/gpu/drm/i915/intel_fbc.c | 27 +++++++++++++++++++++++++++
>>  3 files changed, 32 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 907603c..1d40a7c 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1106,6 +1106,7 @@ struct intel_fbc {
>>  		} fb;
>>
>>  		int cfb_size;
>> +		unsigned int gen9_wa_cfb_stride;
>>  	} params;
>>
>>  	struct intel_fbc_work {
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 56df86e..51cab2f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6801,6 +6801,10 @@ enum {
>>  #define  GLK_CL1_PWR_DOWN	(1 << 11)
>>  #define  GLK_CL0_PWR_DOWN	(1 << 10)
>>
>> +#define CHICKEN_MISC_4		_MMIO(0x4208c)
>> +#define   FBC_STRIDE_OVERRIDE	(1<<13)
>
> See the new comment at the top of this file. (1 << 13) is preferred.
>
>
>> +#define   FBC_STRIDE_MASK	0x1FFF
>> +
>>  #define _CHICKEN_PIPESL_1_A	0x420b0
>>  #define _CHICKEN_PIPESL_1_B	0x420b4
>>  #define  HSW_FBCQ_DIS			(1 << 22)
>> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
>> b/drivers/gpu/drm/i915/intel_fbc.c
>> index 860b8c2..21f6b33 100644
>> --- a/drivers/gpu/drm/i915/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/intel_fbc.c
>> @@ -291,6 +291,21 @@ static void gen7_fbc_activate(struct
>> drm_i915_private *dev_priv)
>>  	u32 dpfc_ctl;
>>  	int threshold = dev_priv->fbc.threshold;
>>
>> +	/* Display WA #0529: skl, kbl, bxt but not for glk*/
>
> Don't need to list excluded platforms. Also, missing space before the
> asterisk.
>
>
>> +	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
>> +		u32 chicken_misc4 = I915_READ(CHICKEN_MISC_4);
>
> In our driver, variables with the name of register usually contain its
> address. We generally use "val" for values.
>
>
>> +
>> +		if (i915_gem_object_get_tiling(params->vma->obj)
>> +				!= I915_TILING_X) {
>> +                       I915_WRITE(CHICKEN_MISC_4, chicken_misc4 |
>> +                               FBC_STRIDE_OVERRIDE |
>> +                               (params->gen9_wa_cfb_stride &
>> FBC_STRIDE_MASK));
>
> We're not masking the old value before overwriting it, eventually
> everything is going to be 0xFFF if we keep changing the stride without
> disabling it.
>
>
>> +		} else {
>> +			I915_WRITE(CHICKEN_MISC_4, chicken_misc4 &
>> +				~(FBC_STRIDE_OVERRIDE |
>> FBC_STRIDE_MASK));
>> +		}
>> +	}
>> +
>
> Major issue with spaces instead of tabs in the whole chunk above.
>
>
>>  	dpfc_ctl = 0;
>>  	if (IS_IVYBRIDGE(dev_priv))
>>  		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
>> @@ -865,6 +880,7 @@ static void intel_fbc_get_reg_params(struct
>> intel_crtc *crtc,
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>  	struct intel_fbc *fbc = &dev_priv->fbc;
>>  	struct intel_fbc_state_cache *cache = &fbc->state_cache;
>> +	int threshold = dev_priv->fbc.threshold;
>>
>>  	/* Since all our fields are integer types, use memset here
>> so the
>>  	 * comparison function can rely on memcmp because the
>> padding will be
>> @@ -880,6 +896,17 @@ static void intel_fbc_get_reg_params(struct
>> intel_crtc *crtc,
>>  	params->fb.format = cache->fb.format;
>>  	params->fb.stride = cache->fb.stride;
>>
>> +	/* Display WA #0529: skl, kbl, bxt but not for glk*/
>> +	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
>> +		/* calculate cfb stride for y-tiled mode */
>> +		if (i915_gem_object_get_tiling(params->vma->obj)
>> +				!= I915_TILING_X) {
>
> We don't need the check here, it's already done in the other part of
> the code.
>
> Anyway, to save time on yet another iteration of this patch I went
> ahead and fixed the styling issues and the masking problem and merged
> the patch. Thanks for the patch!
>
>> +			int cfb_stride = DIV_ROUND_UP(cache-
>>> plane.src_w,
>> +					(32 * threshold)) * 8;
>> +			params->gen9_wa_cfb_stride = cfb_stride;
>> +		}
>> +	}
>> +
>>  	params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv,
>> cache);
>>  }
>>
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