intel-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: vathsala nagaraju <vathsala.nagaraju@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>,
	rodrigo.vivi@intel.com, intel-gfx@lists.freedesktop.org
Cc: Puthikorn Voravootivat <puthik@chromium.org>,
	Maulik V Vaghela <maulik.v.vaghela@intel.com>
Subject: Re: [PATCH] drm/i915/psr: vbt change for psr
Date: Fri, 20 Apr 2018 12:00:57 +0530	[thread overview]
Message-ID: <5AD98921.9080306@intel.com> (raw)
In-Reply-To: <87y3hje2tf.fsf@intel.com>

On Thursday 19 April 2018 07:05 PM, Jani Nikula wrote:
> On Thu, 19 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>>
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to kbl and version 209+ to unblock google.
> This is an incredible mess.
>
>> Tested on skl(bdb version 203,without options) and
>> kabylake(bdb version 209,212) having new options.
>>
>> bspec 20131
>>
>> v2: (Jani and Rodrigo)
>>      move the 165 version check to intel_bios.c
>> v3: Jani
>>      move the abstraction to intel_bios
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>>
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++---
>>   drivers/gpu/drm/i915/intel_psr.c  | 26 ++++++++++++-------------
>>   2 files changed, 50 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index 702d3fa..8913dc8 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>   	}
>>   }
>>   
>> +static bool
>> +is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>> +{
>> +	if (bdb->version >= 209 && IS_KABYLAKE(dev_priv))
>> +		return true;
>> +	else
>> +		return false;
>> +}
>> +
>>   static void
>>   parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>>   {
>> @@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>   		DRM_DEBUG_KMS("No PSR BDB found.\n");
>>   		return;
>>   	}
>> -
>>   	psr_table = &psr->psr_table[panel_type];
>>   
>>   	dev_priv->vbt.psr.full_link = psr_table->full_link;
>> @@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>   		break;
>>   	}
>>   
>> -	dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> -	dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>> +	/*  new psr options    old decimal value interpretation
>> +	 *  0 [500 us]         > 1 [500 us ]
>> +	 *  1 [100 us]         > 0 [100 us ]
>> +	 *  2 [2.5 ms]         > 5 [2.5 ms ]
>> +	 *  3 [0   us]         = 0 [0   us ]
> The old decimal value stuff was wake up time in multiples of 100 us.
>
>> +	 */
>> +	if (!is_psr_options(dev_priv, bdb)) {
> You only use is_psr_options here once, please just open code the
> condition. Also reverse order to not need !something in the condition.
>
>> +		if (psr_table->tp1_wakeup_time > 5)
>> +			dev_priv->vbt.psr.tp1_wakeup_time = 2;
>> +		else if (psr_table->tp1_wakeup_time > 1)
>> +			dev_priv->vbt.psr.tp1_wakeup_time = 0;
>> +		else if (psr_table->tp1_wakeup_time > 0)
>> +			dev_priv->vbt.psr.tp1_wakeup_time = 1;
>> +		else
>> +			dev_priv->vbt.psr.tp1_wakeup_time = 3;
>> +
>> +		if (psr_table->tp2_tp3_wakeup_time > 5)
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2;
>> +		else if (psr_table->tp2_tp3_wakeup_time > 1)
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0;
>> +		else if (psr_table->tp1_wakeup_time > 0)
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1;
>> +		else
>> +			dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3;
>> +	} else {
>> +		dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
>> +		dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
>> +	}
>>   }
> Please rename dev_priv->vbt.psr tp1_wakeup_time and tp2_tp3_wakeup_time
> to have _us suffix, and actually assign the wakeup time in us
> there. Hide all the hideous, hideous VBT stuff behind that, and doesn't
> use magic numbers all over the place.
>
> The old format becomes wakeup_time_us = vbt_value * 100. The code should
> handle mismatches between the value and what the hardware can do (see
> below).
>
> The new format should just be a switch-case mapping values to us,
> whining about values other than 0..3 and defaulting to max in that case.
if we don't set anything in SRD_CTL/PSR2_CTL reg for those bits , by 
default it's 0 [which is 500 us]
instead of defaulting to max value which is 3[0us], should we just 
default to 0[500us]
>>   
>>   static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 69a5b27..95658ad 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>   	if (dev_priv->psr.link_standby)
>>   		val |= EDP_PSR_LINK_STANDBY;
>>   
>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -		val |= EDP_PSR_TP1_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> +	if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
>>   		val |= EDP_PSR_TP1_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
>>   		val |= EDP_PSR_TP1_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
>> +		val |= EDP_PSR_TP1_TIME_2500us;
>>   	else
>>   		val |= EDP_PSR_TP1_TIME_0us;
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>> +		val |=  EDP_PSR_TP2_TP3_TIME_500us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>>   		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>> +		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>>   	else
>>   		val |= EDP_PSR_TP2_TP3_TIME_0us;
> Rewrite these to round up the longer wait:
>
>          if (wakeup_time_us == 0)
> 		val |= EDP_PSR_TP2_TP3_TIME_0us;
> 	else if (wakeup_time_us <= 100)
> 		val |= EDP_PSR_TP2_TP3_TIME_100us;
> 	else if (wakeup_time_us <= 500)
> 		val |= EDP_PSR_TP2_TP3_TIME_500us;
> 	else
> 		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>
>>   
>> @@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>   
>>   	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>>   
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR2_TP2_TIME_2500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> +	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>>   		val |= EDP_PSR2_TP2_TIME_500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>>   		val |= EDP_PSR2_TP2_TIME_100;
>> +	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>> +		val |= EDP_PSR2_TP2_TIME_2500;
>>   	else
>>   		val |= EDP_PSR2_TP2_TIME_50;
> Same here.
>
> BR,
> Jani.
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-04-20  6:31 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-19  7:42 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
2018-04-19  8:08 ` ✓ Fi.CI.BAT: success for drm/i915/psr: vbt change for psr (rev3) Patchwork
2018-04-19  9:13 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-19 13:35 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula
2018-04-20  6:30   ` vathsala nagaraju [this message]
2018-04-27  7:52     ` Jani Nikula
  -- strict thread matches above, loose matches on Subject: below --
2018-05-23  3:05 vathsala nagaraju
2018-05-23 10:03 ` Jani Nikula
2018-05-23 12:55   ` Nagaraju, Vathsala
2018-05-23 13:10     ` Jani Nikula
2018-05-22  9:27 vathsala nagaraju
2018-05-22 12:46 ` Jani Nikula
2018-05-24 13:04   ` Jani Nikula
2018-05-18  8:55 vathsala nagaraju
2018-05-18  9:31 ` Jani Nikula
2018-05-22  4:48   ` Nagaraju, Vathsala
2018-05-22  8:05     ` Jani Nikula
2018-05-22  8:36       ` Nagaraju, Vathsala
2018-05-14  3:32 vathsala nagaraju
2018-05-15 22:55 ` Puthikorn Voravootivat
2018-05-16  3:48   ` vathsala nagaraju
2018-05-15 23:03 ` Dhinakaran Pandiyan
2018-05-16  3:44   ` vathsala nagaraju
2018-05-16  8:08     ` Jani Nikula
2018-05-16 17:44       ` Dhinakaran Pandiyan
2018-05-17  8:02         ` Jani Nikula
2018-05-17 20:12           ` Dhinakaran Pandiyan
2018-05-16  8:13     ` Jani Nikula
2018-05-16 22:04     ` Dhinakaran Pandiyan
2018-05-03 11:36 vathsala nagaraju
2018-05-03 15:44 ` Rodrigo Vivi
2018-05-03 17:13   ` Nagaraju, Vathsala
2018-05-04 23:13     ` Puthikorn Voravootivat
2018-05-03  9:08 vathsala nagaraju
2018-05-03  9:39 ` Jani Nikula
2018-05-02  9:13 vathsala nagaraju
2018-05-02 21:15 ` Rodrigo Vivi
2018-05-03  3:21   ` vathsala nagaraju
2018-05-03  6:59   ` Jani Nikula
2018-05-03  7:07 ` Jani Nikula
2018-04-11 17:57 vathsala nagaraju
2018-04-12  9:26 ` Jani Nikula
2018-04-06 17:28 vathsala nagaraju
2018-04-06 17:41 ` Rodrigo Vivi
2018-04-09 13:57   ` Jani Nikula

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5AD98921.9080306@intel.com \
    --to=vathsala.nagaraju@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jani.nikula@linux.intel.com \
    --cc=maulik.v.vaghela@intel.com \
    --cc=puthik@chromium.org \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).