From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72C90C433EF for ; Mon, 13 Sep 2021 06:26:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 391B360FC0 for ; Mon, 13 Sep 2021 06:26:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 391B360FC0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7AB3989FE8; Mon, 13 Sep 2021 06:26:06 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5502489FE3; Mon, 13 Sep 2021 06:26:05 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10105"; a="307137938" X-IronPort-AV: E=Sophos;i="5.85,288,1624345200"; d="scan'208";a="307137938" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2021 23:26:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,288,1624345200"; d="scan'208";a="543019897" Received: from irsmsx603.ger.corp.intel.com ([163.33.146.9]) by FMSMGA003.fm.intel.com with ESMTP; 12 Sep 2021 23:26:04 -0700 Received: from bgsmsx604.gar.corp.intel.com (10.67.234.6) by irsmsx603.ger.corp.intel.com (163.33.146.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Mon, 13 Sep 2021 07:26:02 +0100 Received: from bgsmsx604.gar.corp.intel.com ([10.67.234.6]) by BGSMSX604.gar.corp.intel.com ([10.67.234.6]) with mapi id 15.01.2242.012; Mon, 13 Sep 2021 11:56:01 +0530 From: "Shankar, Uma" To: "Nikula, Jani" , "intel-gfx@lists.freedesktop.org" CC: "dri-devel@lists.freedesktop.org" , "ville.syrjala@linux.intel.com" , "Nikula, Jani" Thread-Topic: [Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from DisplayID data Thread-Index: AQHXnnMRYfT60hCnxkmXHPx5ESPrdauhk2/A Date: Mon, 13 Sep 2021 06:26:01 +0000 Message-ID: <5a3ed8934466442895654a9adb1af9f3@intel.com> References: <87d8d80ba205eb2ecb50f613219e0a821a842616.1630419362.git.jani.nikula@intel.com> In-Reply-To: <87d8d80ba205eb2ecb50f613219e0a821a842616.1630419362.git.jani.nikula@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.223.10.1] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from DisplayID data X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Intel-gfx On Behalf Of Ja= ni Nikula > Sent: Tuesday, August 31, 2021 7:48 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikul= a, Jani > > Subject: [Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap f= rom > DisplayID data >=20 > Now that we have MSO pixel overlap in display info, use it. >=20 Looks ok to me. Reviewed-by: Uma Shankar > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index df402f63b741..baf21f9aa40e 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2420,6 +2420,8 @@ static void intel_edp_mso_mode_fixup(struct > intel_connector *connector, static void intel_edp_mso_init(struct intel_= dp > *intel_dp) { > struct drm_i915_private *i915 =3D dp_to_i915(intel_dp); > + struct intel_connector *connector =3D intel_dp->attached_connector; > + struct drm_display_info *info =3D &connector->base.display_info; > u8 mso; >=20 > if (intel_dp->edp_dpcd[0] < DP_EDP_14) @@ -2438,8 +2440,9 @@ static > void intel_edp_mso_init(struct intel_dp *intel_dp) > } >=20 > if (mso) { > - drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n", > - mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso); > + drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel > overlap %u\n", > + mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, > + info->mso_pixel_overlap); > if (!HAS_MSO(i915)) { > drm_err(&i915->drm, "No source MSO support, > disabling\n"); > mso =3D 0; > @@ -2447,7 +2450,7 @@ static void intel_edp_mso_init(struct intel_dp *int= el_dp) > } >=20 > intel_dp->mso_link_count =3D mso; > - intel_dp->mso_pixel_overlap =3D 0; /* FIXME: read from DisplayID v2.0 *= / > + intel_dp->mso_pixel_overlap =3D mso ? info->mso_pixel_overlap : 0; > } >=20 > static bool > -- > 2.30.2