From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BA94CCD194 for ; Wed, 15 Oct 2025 15:15:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A510410E824; Wed, 15 Oct 2025 15:15:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Y+yHd0To"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id ECBCE10E824; Wed, 15 Oct 2025 15:15:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1760541343; x=1792077343; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=4NcEdckshK7UGL1mGkxhEwa9Hx4kNkI98fsj8lG35rc=; b=Y+yHd0TovcYIK94yybXV4TA66GvYUz2Ze/7/awKpQC3mDihsUKW/83wd XhDb33cDHpvzOdKeuSEAgVGurr5aNUEsazUSpFpPIzkr/6q+uuNFOFKaf AShmFjke3wa0QAAmw/Qz/Z5JRSVAidfO59W4lBXlJwAXTMrYtmA77XDLK ZYOiZX0ecgRcYs41cCGHWHU4o+iREO+PrZ2qYN22ixJYqY3jOpW7XSIC9 i1oGwfLnEzqn0SThoktXyIboMQlrjSH6DgmWA4uPq9YoFyyW3HoFNhuzN olGBTLb0Ee4i6i1j99HWeROoV8CkCS6mN8SDTM8q845ISKs3r3+SGT0kB Q==; X-CSE-ConnectionGUID: jU0AoJ+8R8qDdi1EEChAVA== X-CSE-MsgGUID: d0LtIJKfSXytiKBEPEMSOQ== X-IronPort-AV: E=McAfee;i="6800,10657,11583"; a="61750421" X-IronPort-AV: E=Sophos;i="6.19,231,1754982000"; d="scan'208";a="61750421" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2025 08:15:42 -0700 X-CSE-ConnectionGUID: T5Peom97Sgm2lBafS7N+sg== X-CSE-MsgGUID: RkWXNZiRRuWPTq/T8tgnFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,231,1754982000"; d="scan'208";a="212810061" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.100]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2025 08:15:37 -0700 From: Jani Nikula To: Gustavo Sousa , intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal , Dnyaneshwar Bhadane , Gustavo Sousa , Jouni =?utf-8?Q?H=C3=B6gander?= , Juha-pekka Heikkila , Luca Coelho , Lucas De Marchi , Matt Atwood , Matt Roper , Ravi Kumar Vodapalli , Sai Teja Pottumuttu , Shekhar Chauhan , Vinod Govindapillai Subject: Re: [PATCH 26/32] drm/i915/xe3p_lpd: Enable pixel normalizer for fp16 formats for FBC In-Reply-To: <20251015-xe3p_lpd-basic-enabling-v1-26-d2d1e26520aa@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251015-xe3p_lpd-basic-enabling-v1-0-d2d1e26520aa@intel.com> <20251015-xe3p_lpd-basic-enabling-v1-26-d2d1e26520aa@intel.com> Date: Wed, 15 Oct 2025 18:15:34 +0300 Message-ID: <5dadb6bb5aa99400dbc6da05523d6979b2c9b099@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 15 Oct 2025, Gustavo Sousa wrote: > From: Vinod Govindapillai > > There is a hw restriction that we could enable the FBC for FP16 > formats only if the pixel normalization block is enabled. Hence > enable the pixel normalizer block with normalzation factor as > 1.0 for the supported FP16 formats to get the FBC enabled. Two > existing helper function definitions are moved up to avoid the > forward declarations as part of this patch as well. > > Bspec: 69863, 68881 > Cc: Shekhar Chauhan > Signed-off-by: Vinod Govindapillai > Signed-off-by: Gustavo Sousa > --- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 50 ++++++++++++++-------- > .../drm/i915/display/skl_universal_plane_regs.h | 1 + > 2 files changed, 33 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 16a9c141281b..ae1bf6beac95 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -486,6 +486,23 @@ static int skl_plane_max_height(const struct drm_framebuffer *fb, > return 4096; > } > > +static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) > +{ > + return pipe - PIPE_A + INTEL_FBC_A; > +} > + > +static bool skl_plane_has_fbc(struct intel_display *display, > + enum intel_fbc_id fbc_id, enum plane_id plane_id) > +{ > + if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0) > + return false; > + > + if (DISPLAY_VER(display) >= 20) > + return icl_is_hdr_plane(display, plane_id); > + else > + return plane_id == PLANE_1; > +} > + > static int icl_plane_max_height(const struct drm_framebuffer *fb, > int color_plane, > unsigned int rotation) > @@ -896,7 +913,21 @@ static void skl_write_plane_wm(struct intel_dsb *dsb, > static void > xe3p_lpd_plane_check_pixel_normalizer(struct intel_plane_state *plane_state) > { > - plane_state->pixel_normalizer = 0; > + struct intel_display *display = to_intel_display(plane_state); > + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); > + enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe); > + u32 reg = 0; > + > + /* > + * To enable FBC for FP16 formats, enable pixel normalizer with > + * normalization factor as 1.0 > + */ > + if (skl_plane_has_fbc(display, fbc_id, plane->id) && > + intel_fbc_is_fp16_format_supported(plane_state)) > + reg = PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0) | > + PLANE_PIXEL_NORMALIZE_ENABLE; Again, this functions should be about software state, and shouldn't have to concern itself with the register macros. The function name still doesn't make sense. > + > + plane_state->pixel_normalizer = reg; > } > > static void > @@ -2449,23 +2480,6 @@ void icl_link_nv12_planes(struct intel_plane_state *uv_plane_state, > } > } > > -static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) > -{ > - return pipe - PIPE_A + INTEL_FBC_A; > -} > - > -static bool skl_plane_has_fbc(struct intel_display *display, > - enum intel_fbc_id fbc_id, enum plane_id plane_id) > -{ > - if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0) > - return false; > - > - if (DISPLAY_VER(display) >= 20) > - return icl_is_hdr_plane(display, plane_id); > - else > - return plane_id == PLANE_1; > -} > - > static struct intel_fbc *skl_plane_fbc(struct intel_display *display, > enum pipe pipe, enum plane_id plane_id) > { > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index 11c713f9b237..eb25de5d1778 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -466,5 +466,6 @@ > #define PLANE_PIXEL_NORMALIZE_ENABLE REG_BIT(31) > #define PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK REG_GENMASK(15, 0) > #define PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val) REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK, (val)) > +#define PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0 0x3c00 > > #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */ -- Jani Nikula, Intel