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[2001:1c00:c1e:bf00:d69d:5353:dba5:ee81]) by smtp.gmail.com with ESMTPSA id s5-20020a508dc5000000b004241a4abbdfsm1311831edh.45.2022.04.20.08.32.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Apr 2022 08:32:44 -0700 (PDT) Message-ID: <60452154-8aab-b15d-1dff-29d3fa732f22@redhat.com> Date: Wed, 20 Apr 2022 17:32:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 To: =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= References: <20220418150936.5499-1-hdegoede@redhat.com> From: Hans de Goede In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=hdegoede@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix DISP_POS_Y and DISP_HEIGHT defines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi Ville, On 4/20/22 16:03, Ville Syrjälä wrote: > On Mon, Apr 18, 2022 at 05:09:36PM +0200, Hans de Goede wrote: >> Commit 428cb15d5b00 ("drm/i915: Clean up pre-skl primary plane registers") >> introduced DISP_POS_Y and DISP_HEIGHT defines but accidentally set these >> their masks to REG_GENMASK(31, 0) instead of REG_GENMASK(31, 16). >> >> This breaks the primary display pane on at least pineview machines, fix >> the mask to fix the primary display pane only showing black. >> >> Tested on an Acer One AO532h with an Intel N450 SoC. >> >> Fixes: 428cb15d5b00 ("drm/i915: Clean up pre-skl primary plane registers") >> Cc: José Roberto de Souza >> Cc: Ville Syrjälä >> Signed-off-by: Hans de Goede >> --- >> Note this fixes a regression in 5.18-rc# and I'm not entirely sure what >> the procedure is here. Once I get a Reviewed-by or Acked-by and I push >> this to drm-intel-next (where it also is necessary), should I then also >> push it to drm-intel-fixes or will the current drm-intel-fixes >> maintainer pick it up? >> --- >> drivers/gpu/drm/i915/i915_reg.h | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 51f46fe45c72..5f1f38684d65 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -4352,12 +4352,12 @@ >> #define _DSPAADDR 0x70184 >> #define _DSPASTRIDE 0x70188 >> #define _DSPAPOS 0x7018C /* reserved */ >> -#define DISP_POS_Y_MASK REG_GENMASK(31, 0) >> +#define DISP_POS_Y_MASK REG_GENMASK(31, 16) > > Doh. I guess I only tested it on plane A where the plane gets its size > from PIPESRC instead. And looks like the failure mode is such that > the likes of kms_plane/pixel-formats still gets consistent looking CRCs > even with the misconfigured plane size :/ > > Thanks for the fix. Pushed to drm-intel-next. Thank you pushing this out, will you (or someone else from Intel) also take care of getting this on its way to 5.18-rc# ? Regards, Hans > >> #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) >> #define DISP_POS_X_MASK REG_GENMASK(15, 0) >> #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) >> #define _DSPASIZE 0x70190 >> -#define DISP_HEIGHT_MASK REG_GENMASK(31, 0) >> +#define DISP_HEIGHT_MASK REG_GENMASK(31, 16) >> #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) >> #define DISP_WIDTH_MASK REG_GENMASK(15, 0) >> #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) >> -- >> 2.35.1 >