[PATCH v3 0/6] Ring frequency & Rpe changes for SKL

[PATCH v3 0/6] Ring frequency & Rpe changes for SKL

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

This patch series adds the changes for supporting the Ring frequency table
programming and retrieving the efficient frequency (aka RPe) value from the
pcode for SKL.
Addressed review comments & suggestion from Daniel in this version.

Akash Goel (6):
  drm/i915/skl: Retrieve the Rpe value from Pcode
  drm/i915/skl: Ring frequency table programming changes
  drm/i915/skl: Restrict the ring frequency table programming to SKL
  drm/i915/skl: Updated the i915_ring_freq_table debugfs function
  drm/i915: Add HAS_CORE_RING_FREQ macro
  drm/i915: Added BXT check in HAS_CORE_RING_FREQ macro

 drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++----
 drivers/gpu/drm/i915/i915_drv.h     |  3 +++
 drivers/gpu/drm/i915/intel_pm.c     | 47 ++++++++++++++++++++++++++-----------
 3 files changed, 52 insertions(+), 19 deletions(-)

-- 
1.9.2

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[PATCH 1/6] drm/i915/skl: Retrieve the Rpe value from Pcode

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Read the efficient frequency (aka RPe) value through the the mailbox
command (0x1A) from the pcode, as done on Haswell and Broadwell.
The turbo minimum frequency softlimit is not revised as per the
efficient frequency value.

v2: Replaced the conditional expression operator with 'if' statement (Tom)
v3: Corrected the derivation of efficient frequency & shifted the
    GEN9_FREQ_SCALER multiplications downwards (Ville)

Issue: VIZ-5143
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..8185a23 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4295,18 +4295,11 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
 	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
 	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
 	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
-	if (IS_SKYLAKE(dev)) {
-		/* Store the frequency values in 16.66 MHZ units, which is
-		   the natural hardware unit for SKL */
-		dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
-		dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
-		dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
-	}
 	/* hw_max = RP0 until we check for overclocking */
 	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
 
 	dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
-	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
 		ret = sandybridge_pcode_read(dev_priv,
 					HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
 					&ddcc_status);
@@ -4318,6 +4311,16 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
 					dev_priv->rps.max_freq);
 	}
 
+	if (IS_SKYLAKE(dev)) {
+		/* Store the frequency values in 16.66 MHZ units, which is
+		   the natural hardware unit for SKL */
+		dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
+	}
+
 	dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
 
 	/* Preserve min/max settings in case of re-init */
-- 
1.9.2

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Re: [PATCH 1/6] drm/i915/skl: Retrieve the Rpe value from Pcode

[Rodrigo Vivi]

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I don't have the spec so I can just assume it was like previous platforms.

For me this 50MHz x 16.6MHz is still confusing (like clamp in 50 than
convert to 16.6)... but nevermind...  apparently we are not mixing stuff in
the sense we compare values in different scales...

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



On Mon, Jun 29, 2015 at 2:11 AM <akash.goel@intel.com> wrote:

> From: Akash Goel <akash.goel@intel.com>
>
> Read the efficient frequency (aka RPe) value through the the mailbox
> command (0x1A) from the pcode, as done on Haswell and Broadwell.
> The turbo minimum frequency softlimit is not revised as per the
> efficient frequency value.
>
> v2: Replaced the conditional expression operator with 'if' statement (Tom)
> v3: Corrected the derivation of efficient frequency & shifted the
>     GEN9_FREQ_SCALER multiplications downwards (Ville)
>
> Issue: VIZ-5143
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++--------
>  1 file changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 32ff034..8185a23 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4295,18 +4295,11 @@ static void gen6_init_rps_frequencies(struct
> drm_device *dev)
>         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
>         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
>         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
> -       if (IS_SKYLAKE(dev)) {
> -               /* Store the frequency values in 16.66 MHZ units, which is
> -                  the natural hardware unit for SKL */
> -               dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
> -               dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
> -               dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
> -       }
>         /* hw_max = RP0 until we check for overclocking */
>         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
>
>         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
> -       if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> +       if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
>                 ret = sandybridge_pcode_read(dev_priv,
>
> HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
>                                         &ddcc_status);
> @@ -4318,6 +4311,16 @@ static void gen6_init_rps_frequencies(struct
> drm_device *dev)
>                                         dev_priv->rps.max_freq);
>         }
>
> +       if (IS_SKYLAKE(dev)) {
> +               /* Store the frequency values in 16.66 MHZ units, which is
> +                  the natural hardware unit for SKL */
> +               dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
> +               dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
> +               dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
> +               dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
> +               dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
> +       }
> +
>         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
>
>         /* Preserve min/max settings in case of re-init */
> --
> 1.9.2
>
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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[PATCH 2/6] drm/i915/skl: Ring frequency table programming changes

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Ring frequency table programming changes for SKL. No need for a
floor on ring frequency, as the issue of performance impact with
ring running below DDR frequency, is believed to be fixed on SKL

v2: Removed the check for avoiding ring frequency programming for BXT (Rodrigo)

Issue: VIZ-5144
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8185a23..89c1b73 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4613,6 +4613,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev)
 	int min_freq = 15;
 	unsigned int gpu_freq;
 	unsigned int max_ia_freq, min_ring_freq;
+	unsigned int max_gpu_freq, min_gpu_freq;
 	int scaling_factor = 180;
 	struct cpufreq_policy *policy;
 
@@ -4637,17 +4638,31 @@ static void __gen6_update_ring_freq(struct drm_device *dev)
 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 
+	if (IS_SKYLAKE(dev)) {
+		/* Convert GT frequency to 50 HZ units */
+		min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
+		max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
+	} else {
+		min_gpu_freq = dev_priv->rps.min_freq;
+		max_gpu_freq = dev_priv->rps.max_freq;
+	}
+
 	/*
 	 * For each potential GPU frequency, load a ring frequency we'd like
 	 * to use for memory access.  We do this by specifying the IA frequency
 	 * the PCU should use as a reference to determine the ring frequency.
 	 */
-	for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
-	     gpu_freq--) {
-		int diff = dev_priv->rps.max_freq - gpu_freq;
+	for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
+		int diff = max_gpu_freq - gpu_freq;
 		unsigned int ia_freq = 0, ring_freq = 0;
 
-		if (INTEL_INFO(dev)->gen >= 8) {
+		if (IS_SKYLAKE(dev)) {
+			/*
+			 * ring_freq = 2 * GT. ring_freq is in 100MHz units
+			 * No floor required for ring frequency on SKL.
+			 */
+			ring_freq = gpu_freq;
+		} else if (INTEL_INFO(dev)->gen >= 8) {
 			/* max(2 * GT, DDR). NB: GT is 50MHz units */
 			ring_freq = max(min_ring_freq, gpu_freq);
 		} else if (IS_HASWELL(dev)) {
-- 
1.9.2

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[PATCH 3/6] drm/i915/skl: Restrict the ring frequency table programming to SKL

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Ring frequency table programming is not required on BXT. Added separate
checks to enable the programming only for SKL & skip for BXT.

v2: Removed the BXT check from gen6_update_ring_freq function

Issue: VIZ-5144
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89c1b73..daca7e7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5811,7 +5811,8 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 	} else if (INTEL_INFO(dev)->gen >= 9) {
 		gen9_enable_rc6(dev);
 		gen9_enable_rps(dev);
-		__gen6_update_ring_freq(dev);
+		if (IS_SKYLAKE(dev))
+			__gen6_update_ring_freq(dev);
 	} else if (IS_BROADWELL(dev)) {
 		gen8_enable_rps(dev);
 		__gen6_update_ring_freq(dev);
-- 
1.9.2

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Re: [PATCH 3/6] drm/i915/skl: Restrict the ring frequency table programming to SKL

[Daniel Vetter]

On Mon, Jun 29, 2015 at 02:50:21PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Ring frequency table programming is not required on BXT. Added separate
> checks to enable the programming only for SKL & skip for BXT.
> 
> v2: Removed the BXT check from gen6_update_ring_freq function
> 
> Issue: VIZ-5144
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Queued for -next with Rodrigo's r-b from archives (somehow that mail
didn't make it to me), thanks for the patch.
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 89c1b73..daca7e7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5811,7 +5811,8 @@ static void intel_gen6_powersave_work(struct work_struct *work)
>  	} else if (INTEL_INFO(dev)->gen >= 9) {
>  		gen9_enable_rc6(dev);
>  		gen9_enable_rps(dev);
> -		__gen6_update_ring_freq(dev);
> +		if (IS_SKYLAKE(dev))
> +			__gen6_update_ring_freq(dev);
>  	} else if (IS_BROADWELL(dev)) {
>  		gen8_enable_rps(dev);
>  		__gen6_update_ring_freq(dev);
> -- 
> 1.9.2
> 
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-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 4/6] drm/i915/skl: Updated the i915_ring_freq_table debugfs function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Updated the i915_ring_freq_table debugfs function to support the read
of ring frequency table, through Punit interface, for SKL also.

Issue: VIZ-5144
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e40e479..f8df5f2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1760,6 +1760,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret = 0;
 	int gpu_freq, ia_freq;
+	unsigned int max_gpu_freq, min_gpu_freq;
 
 	if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
 		seq_puts(m, "unsupported on this chipset\n");
@@ -1774,17 +1775,27 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	if (ret)
 		goto out;
 
+	if (IS_SKYLAKE(dev)) {
+		/* Convert GT frequency to 50 HZ units */
+		min_gpu_freq =
+			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
+		max_gpu_freq =
+			dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
+	} else {
+		min_gpu_freq = dev_priv->rps.min_freq_softlimit;
+		max_gpu_freq = dev_priv->rps.max_freq_softlimit;
+	}
+
 	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
 
-	for (gpu_freq = dev_priv->rps.min_freq_softlimit;
-	     gpu_freq <= dev_priv->rps.max_freq_softlimit;
-	     gpu_freq++) {
+	for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
 		ia_freq = gpu_freq;
 		sandybridge_pcode_read(dev_priv,
 				       GEN6_PCODE_READ_MIN_FREQ_TABLE,
 				       &ia_freq);
 		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
-			   intel_gpu_freq(dev_priv, gpu_freq),
+			   intel_gpu_freq(dev_priv, (gpu_freq *
+				(IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
 			   ((ia_freq >> 0) & 0xff) * 100,
 			   ((ia_freq >> 8) & 0xff) * 100);
 	}
-- 
1.9.2

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Re: [PATCH 4/6] drm/i915/skl: Updated the i915_ring_freq_table debugfs function

[Daniel Vetter]

On Mon, Jun 29, 2015 at 02:50:22PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Updated the i915_ring_freq_table debugfs function to support the read
> of ring frequency table, through Punit interface, for SKL also.
> 
> Issue: VIZ-5144
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Merged patches 1, 3&4 from this series, thanks.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index e40e479..f8df5f2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1760,6 +1760,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int ret = 0;
>  	int gpu_freq, ia_freq;
> +	unsigned int max_gpu_freq, min_gpu_freq;
>  
>  	if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
>  		seq_puts(m, "unsupported on this chipset\n");
> @@ -1774,17 +1775,27 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
>  	if (ret)
>  		goto out;
>  
> +	if (IS_SKYLAKE(dev)) {
> +		/* Convert GT frequency to 50 HZ units */
> +		min_gpu_freq =
> +			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
> +		max_gpu_freq =
> +			dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
> +	} else {
> +		min_gpu_freq = dev_priv->rps.min_freq_softlimit;
> +		max_gpu_freq = dev_priv->rps.max_freq_softlimit;
> +	}
> +
>  	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
>  
> -	for (gpu_freq = dev_priv->rps.min_freq_softlimit;
> -	     gpu_freq <= dev_priv->rps.max_freq_softlimit;
> -	     gpu_freq++) {
> +	for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
>  		ia_freq = gpu_freq;
>  		sandybridge_pcode_read(dev_priv,
>  				       GEN6_PCODE_READ_MIN_FREQ_TABLE,
>  				       &ia_freq);
>  		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
> -			   intel_gpu_freq(dev_priv, gpu_freq),
> +			   intel_gpu_freq(dev_priv, (gpu_freq *
> +				(IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
>  			   ((ia_freq >> 0) & 0xff) * 100,
>  			   ((ia_freq >> 8) & 0xff) * 100);
>  	}
> -- 
> 1.9.2
> 
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-- 
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[PATCH 5/6] drm/i915: Add HAS_CORE_RING_FREQ macro

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Added a new HAS_CORE_RING_FREQ macro, currently used in
gen6_update_ring_freq & i915_ring_freq_table debugfs function.
The programming & read of ring frequency table is needed for newer
GEN(>=6) platforms, except VLV/CHV.

Issue: VIZ-5144
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h     | 3 +++
 drivers/gpu/drm/i915/intel_pm.c     | 2 +-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f8df5f2..ae36b40 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1762,7 +1762,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	int gpu_freq, ia_freq;
 	unsigned int max_gpu_freq, min_gpu_freq;
 
-	if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
+	if (!HAS_CORE_RING_FREQ(dev)) {
 		seq_puts(m, "unsupported on this chipset\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea9caf2..7b6aa71 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2520,6 +2520,9 @@ struct drm_i915_cmd_table {
 
 #define HAS_CSR(dev)	(IS_SKYLAKE(dev))
 
+#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
+				 !IS_VALLEYVIEW(dev))
+
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index daca7e7..31f178d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4696,7 +4696,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
+	if (!HAS_CORE_RING_FREQ(dev))
 		return;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
-- 
1.9.2

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[PATCH 6/6] drm/i915: Added BXT check in HAS_CORE_RING_FREQ macro

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Updated the HAS_CORE_RING_FREQ macro to add the broxton check,
so as to disallow the programming & read of ring frequency
table for it.

Issue: VIZ-5144
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7b6aa71..6f927b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2521,7 +2521,7 @@ struct drm_i915_cmd_table {
 #define HAS_CSR(dev)	(IS_SKYLAKE(dev))
 
 #define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
-				 !IS_VALLEYVIEW(dev))
+				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
-- 
1.9.2

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Re: [PATCH 6/6] drm/i915: Added BXT check in HAS_CORE_RING_FREQ macro

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6658
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  302/302              302/302
SNB                                  312/316              312/316
IVB                                  343/343              343/343
BYT                 -4              287/287              283/287
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*BYT  igt@gem_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
*BYT  igt@gem_partial_pwrite_pread@reads-display      PASS(1)      FAIL(1)
*BYT  igt@gem_partial_pwrite_pread@reads-uncached      PASS(1)      FAIL(1)
*BYT  igt@gem_tiled_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 6/6] drm/i915: Added BXT check in HAS_CORE_RING_FREQ macro

[Rodrigo Vivi]

[-- Attachment #1.1: Type: text/plain, Size: 1360 bytes --]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


On Mon, Jun 29, 2015 at 1:28 PM <shuang.he@intel.com> wrote:

> Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
> shuang.he@intel.com)
> Task id: 6658
>
> -------------------------------------Summary-------------------------------------
> Platform          Delta          drm-intel-nightly          Series Applied
> ILK                                  302/302              302/302
> SNB                                  312/316              312/316
> IVB                                  343/343              343/343
> BYT                 -4              287/287              283/287
>
> -------------------------------------Detailed-------------------------------------
> Platform  Test                                drm-intel-nightly
> Series Applied
> *BYT  igt@gem_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
> *BYT  igt@gem_partial_pwrite_pread@reads-display      PASS(1)      FAIL(1)
> *BYT  igt@gem_partial_pwrite_pread@reads-uncached      PASS(1)
> FAIL(1)
> *BYT  igt@gem_tiled_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
> Note: You need to pay more attention to line start with '*'
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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