From mboxrd@z Thu Jan  1 00:00:00 1970
From: shuang.he@intel.com
Subject: Re: [PATCH 9/9] drm/i915: Check pixel clock when
 setting mode for DP-MST
Date: 04 Jul 2015 16:24:30 -0700
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References: <1435923357-3821-10-git-send-email-mika.kahola@intel.com>
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VGVzdGVkLUJ5OiBJbnRlbCBHcmFwaGljcyBRQSBQUlRTIChQYXRjaCBSZWdyZXNzaW9uIFRlc3Qg
U3lzdGVtIENvbnRhY3Q6IHNodWFuZy5oZUBpbnRlbC5jb20pClRhc2sgaWQ6IDY3MTcKLS0tLS0t
LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLVN1bW1hcnktLS0tLS0tLS0tLS0tLS0tLS0t
LS0tLS0tLS0tLS0tLS0tLS0tClBsYXRmb3JtICAgICAgICAgIERlbHRhICAgICAgICAgIGRybS1p
bnRlbC1uaWdodGx5ICAgICAgICAgIFNlcmllcyBBcHBsaWVkCklMSyAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAzMDIvMzAyICAgICAgICAgICAgICAzMDIvMzAyClNOQiAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAzMTIvMzE2ICAgICAgICAgICAgICAzMTIvMzE2CklW
QiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAzNDMvMzQzICAgICAgICAgICAgICAz
NDMvMzQzCkJZVCAgICAgICAgICAgICAgICAgLTMgICAgICAgICAgICAgIDI4Ny8yODcgICAgICAg
ICAgICAgIDI4NC8yODcKSFNXICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDM4MC8z
ODAgICAgICAgICAgICAgIDM4MC8zODAKLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t
LS0tLURldGFpbGVkLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQpQbGF0Zm9y
bSAgVGVzdCAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgZHJtLWludGVsLW5pZ2h0bHkg
ICAgICAgICAgU2VyaWVzIEFwcGxpZWQKKkJZVCAgaWd0QGdlbV9wYXJ0aWFsX3B3cml0ZV9wcmVh
ZEByZWFkcyAgICAgIFBBU1MoMSkgICAgICBGQUlMKDEpCipCWVQgIGlndEBnZW1fcGFydGlhbF9w
d3JpdGVfcHJlYWRAcmVhZHMtdW5jYWNoZWQgICAgICBQQVNTKDEpICAgICAgRkFJTCgxKQoqQllU
ICBpZ3RAZ2VtX3RpbGVkX3BhcnRpYWxfcHdyaXRlX3ByZWFkQHJlYWRzICAgICAgUEFTUygxKSAg
ICAgIEZBSUwoMSkKTm90ZTogWW91IG5lZWQgdG8gcGF5IG1vcmUgYXR0ZW50aW9uIHRvIGxpbmUg
c3RhcnQgd2l0aCAnKicKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Au
b3JnCmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1n
ZngK