From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v3 5/6] drm/i915: Disable PSR2 while getting pipe CRC Date: Thu, 28 Feb 2019 23:07:04 +0000 Message-ID: <63cd0960213479d7bb2096668ac8fccf17830491.camel@intel.com> References: <20190228013259.30026-1-jose.souza@intel.com> <20190228013259.30026-5-jose.souza@intel.com> <20190228165821.GN20097@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1038920546==" Return-path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id D11896E248 for ; Thu, 28 Feb 2019 23:07:06 +0000 (UTC) In-Reply-To: <20190228165821.GN20097@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "ville.syrjala@linux.intel.com" Cc: "intel-gfx@lists.freedesktop.org" , "Pandiyan, Dhinakaran" List-Id: intel-gfx@lists.freedesktop.org --===============1038920546== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-6eEv7T7UydOZUpwBDJup" --=-6eEv7T7UydOZUpwBDJup Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2019-02-28 at 18:58 +0200, Ville Syrj=C3=A4l=C3=A4 wrote: > On Wed, Feb 27, 2019 at 05:32:58PM -0800, Jos=C3=A9 Roberto de Souza > wrote: > > When PSR2 is active aka after the number of frames programmed in > > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC > > interruptions causing IGT tests to fail due timeout. > >=20 > > Oddly that don't happen when PSR1 active, so here it switches from > > PSR2 to PSR1 while user is requesting pipe CRC. > >=20 > > Force setting mode_changed as true is necessary to atomic checks > > functions compute new PSR state, that is why it was added to > > intel_crtc_crc_prepare(). > >=20 > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > >=20 > > v2: Changed commit description to describe that PSR2 inhibit CRC > > calculations. > >=20 > > Cc: Dhinakaran Pandiyan > > Cc: Ville Syrj=C3=A4l=C3=A4 > > Signed-off-by: Jos=C3=A9 Roberto de Souza > > --- > > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > > 2 files changed, 4 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c > > b/drivers/gpu/drm/i915/intel_pipe_crc.c > > index f6d0b2aaffe2..e7ac24c33650 100644 > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private > > *dev_priv, struct drm_crtc *crtc, > > goto put_state; > > } > > =20 > > + pipe_config->base.mode_changed =3D pipe_config->crc_enabled !=3D > > enable; >=20 > Do we really want to set that unconditionally? Without it atomic helpers will return ealier as there is no state changes, I was wondering if the IPS was being applied in the bellow connectors_changed is not set. Anyways to triggers the code paths to disable PSR2 it is needed, and with fastboot enable by default in gen9+ it will do a fastset so not much drawbacks. >=20 > > pipe_config->crc_enabled =3D enable; > > =20 > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe =3D=3D PIPE_A) { > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 6175b1d2e0c8..f7730b8b2ec0 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > return false; > > } > > =20 > > + if (crtc_state->crc_enabled) > > + return false; > > + > > return true; > > } > > =20 > > --=20 > > 2.21.0 --=-6eEv7T7UydOZUpwBDJup Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlx4aZYACgkQVenbO/mO WkkqnQf9EKyzpRNP4unteFjyKPdeM8pvGhA1uzizRgW4qa2Bljt7d51n/9UK8nz9 0c0sKs+PW/qRZuyIdteEVRM8Sr73rUO/GkXJRaaSqknahDjZ8ivFUtoIXKCHKuI1 UjVNI6LezR1wqox2BTMWrUD9gGnDxYGrHAbmk6PkpCHEbserWMX7Re8aNxrO7H80 k9WM+SMxRSyGrVjFFFmoONYLpwrrXPYslzai5AjC2vTCgneGn2nWKvAlrqW6mqxF 4QWAFHIiEiwJdK0+cuy7UfB/rxrqhItcwwxsC5Rh8/skLmLXFK8ZaDCVakB5tOpF 7A4G9Pfa0tv9dUDVBR/OXjb0ezC+DA== =BXxU -----END PGP SIGNATURE----- --=-6eEv7T7UydOZUpwBDJup-- --===============1038920546== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 --===============1038920546==--