[Intel-gfx] [PULL] drm-intel-gt-next

Joonas Lahtinen
2022-09-09T11:20:52Z

Hi Dave & Daniel,

Here goes second drm-intel-gt-next PR towards 6.1.

As the top item we're now aligning the GuC/HuC firmware versioning
to meet the expectations recorded under firmware-usage-guidelines.rst.
A revert of a previous (incorrect) userspace register removal for DG2
and addition of new DG2 workaround. Reject suspend on DG2 on low
system memory condition.

Fix for Gitlab #6639 h264 hardware video decoding regression, GuC SLPC
improvements, PXP fix, ATS-M thread tuning settings and tiny bit of
Meteorlake enabling,

Regards, Joonas

PS. Still not the top of drm-intel-gt-next as need your comments on
fixing(?) the Acked-by's on the MEI/GSC patches.

***

drm-intel-gt-next-2022-09-09:

UAPI Changes:

- Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"

The intent of Wa_14015141709 was to inform us that userspace can no
longer control object-level preemption as it has on past platforms
(i.e., by twiddling register bit CS_CHICKEN1[0]). The description of
the workaround in the spec wasn't terribly well-written, and when we
requested clarification from the hardware teams we were told that on the
kernel side we should also probably stop setting
FF_SLICE_CS_CHICKEN1[14], which is the register bit that directs the
hardware to honor the settings in per-context register CS_CHICKEN1. It
turns out that this guidance about FF_SLICE_CS_CHICKEN1[14] was a
mistake; even though CS_CHICKEN1[0] is non-operational and useless to
userspace, there are other bits in the register that do still work and
might need to be adjusted by userspace in the future (e.g., to implement
other workarounds that show up). If we don't set
FF_SLICE_CS_CHICKEN1[14] in i915, then those future workarounds would
not take effect.

Even more details at:

https://lists.freedesktop.org/archives/intel-gfx/2022-September/305478.html

Driver Changes:

- Align GuC/HuC firmware versioning scheme to kernel practices (John)
- Fix #6639: h264 hardware video decoding broken in 5.19 on Intel(R)
Celeron(R) N3060 (Nirmoy)
- Meteorlake (MTL) enabling (Matt R)
- GuC SLPC improvements (Vinay, Rodrigo)
- Add thread execution tuning setting for ATS-M (Matt R)
- Don't start PXP without mei_pxp bind (Juston)
- Remove leftover verbose debug logging from GuC error capture (John)
- Abort suspend on low system memory conditions (Nirmoy, Matt A, Chris)
- Add DG2 Wa_16014892111 (Matt R)

- Rename ggtt_view as gtt_view (Niranjana)
- Consider HAS_FLAT_CCS() in needs_ccs_pages (Matt A)
- Don't try to disable host RPS when this was never enabled. (Rodrigo)
- Clear stalled GuC CT request after a reset (Daniele)
- Remove runtime info printing from GuC time stamp logging (Jani)
- Skip Bit12 fw domain reset for gen12+ (Sushma, Radhakrishna)

- Make GuC log sizes runtime configurable (John)
- Selftest improvements (Daniele, Matt B, Andrzej)

The following changes since commit 5ece208ab05e4042c80ed1e6fe6d7ce236eee89b:

drm/i915/guc: Use streaming loads to speed up dumping the guc log (2022-08-17 10:07:03 -0700)

are available in the Git repository at:

git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-gt-next-2022-09-09

for you to fetch changes up to 04f7eb3d4582a0a4da67c86e55fda7de2df86d91:

drm/i915: Set correct domains values at _i915_vma_move_to_active (2022-09-08 11:06:35 +0100)

----------------------------------------------------------------
UAPI Changes:

- Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"

The intent of Wa_14015141709 was to inform us that userspace can no
longer control object-level preemption as it has on past platforms
(i.e., by twiddling register bit CS_CHICKEN1[0]). The description of
the workaround in the spec wasn't terribly well-written, and when we
requested clarification from the hardware teams we were told that on the
kernel side we should also probably stop setting
FF_SLICE_CS_CHICKEN1[14], which is the register bit that directs the
hardware to honor the settings in per-context register CS_CHICKEN1. It
turns out that this guidance about FF_SLICE_CS_CHICKEN1[14] was a
mistake; even though CS_CHICKEN1[0] is non-operational and useless to
userspace, there are other bits in the register that do still work and
might need to be adjusted by userspace in the future (e.g., to implement
other workarounds that show up). If we don't set
FF_SLICE_CS_CHICKEN1[14] in i915, then those future workarounds would
not take effect.

Even more details at:

https://lists.freedesktop.org/archives/intel-gfx/2022-September/305478.html

Driver Changes:

- Align GuC/HuC firmware versioning scheme to kernel practices (John)
- Fix #6639: h264 hardware video decoding broken in 5.19 on Intel(R)
Celeron(R) N3060 (Nirmoy)
- Meteorlake (MTL) enabling (Matt R)
- GuC SLPC improvements (Vinay, Rodrigo)
- Add thread execution tuning setting for ATS-M (Matt R)
- Don't start PXP without mei_pxp bind (Juston)
- Remove leftover verbose debug logging from GuC error capture (John)
- Abort suspend on low system memory conditions (Nirmoy, Matt A, Chris)
- Add DG2 Wa_16014892111 (Matt R)

- Rename ggtt_view as gtt_view (Niranjana)
- Consider HAS_FLAT_CCS() in needs_ccs_pages (Matt A)
- Don't try to disable host RPS when this was never enabled. (Rodrigo)
- Clear stalled GuC CT request after a reset (Daniele)
- Remove runtime info printing from GuC time stamp logging (Jani)
- Skip Bit12 fw domain reset for gen12+ (Sushma, Radhakrishna)

- Make GuC log sizes runtime configurable (John)
- Selftest improvements (Daniele, Matt B, Andrzej)

----------------------------------------------------------------
Andrzej Hajda (1):
drm/i915/selftests: allow misaligned_pin test work with unmappable memory

Daniele Ceraolo Spurio (2):
drm/i915/guc: skip scrub_ctbs selftest if reset is disabled
drm/i915/guc: clear stalled request after a reset

Jani Nikula (1):
drm/i915/guc: remove runtime info printing from time stamp logging

John Harrison (4):
drm/i915/guc: Make GuC log sizes runtime configurable
drm/i915/guc: Reduce spam from error capture
drm/i915/uc: Support for version reduced and multiple firmware files
drm/i915/uc: Add patch level version number support

Joonas Lahtinen (1):
drm/i915/guc: Remove log size module parameters

Juston Li (1):
drm/i915/pxp: don't start pxp without mei_pxp bind

Matt Roper (5):
drm/i915/mtl: MMIO range is now 4MB
drm/i915/mtl: Don't mask off CCS according to DSS fusing
drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning
Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"
drm/i915/ats-m: Add thread execution tuning setting

Matthew Auld (2):
Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages

Matthew Brost (2):
drm/i915/selftests: Use correct selfest calls for live tests
drm/i915/guc: Add delay to disable scheduling after pin count goes to zero

Niranjana Vishwanathapura (1):
drm/i915: Rename ggtt_view as gtt_view

Nirmoy Das (2):
drm/i915/ttm: Abort suspend on i915_ttm_backup failure
drm/i915: Set correct domains values at _i915_vma_move_to_active

Radhakrishna Sripada (1):
drm/i915: Skip Bit12 fw domain reset for gen12+

Rodrigo Vivi (3):
drm/i915/slpc: Fix inconsistent locked return
drm/i915/slpc: Let's fix the PCODE min freq table setup for SLPC
drm/i915: Don't try to disable host RPS when this was never enabled.

Vinay Belgaumkar (1):
drm/i915/guc/slpc: Allow SLPC to use efficient frequency

drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_fb.c | 18 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 4 +-
drivers/gpu/drm/i915/display/intel_fb_pin.h | 4 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 16 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c | 3 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 7 +-
.../drm/i915/gem/selftests/i915_gem_coherency.c | 2 +-
.../gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +-
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 +-
.../gpu/drm/i915/gem/selftests/i915_gem_object.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
drivers/gpu/drm/i915/gt/intel_llc.c | 19 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 60 ++-
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +-
drivers/gpu/drm/i915/gt/selftest_slpc.c | 9 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 55 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 81 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 175 +++++++-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 42 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 86 +---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 17 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 462 ++++++++++++++-------
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 39 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 8 +-
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 3 +
drivers/gpu/drm/i915/i915_debugfs.c | 56 +--
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/i915_gem.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 16 +-
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_vma.c | 43 +-
drivers/gpu/drm/i915/i915_vma.h | 18 +-
drivers/gpu/drm/i915/i915_vma_types.h | 42 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_mchbar_regs.h | 3 +
drivers/gpu/drm/i915/intel_uncore.c | 18 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 15 +
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 70 ++--
53 files changed, 937 insertions(+), 555 deletions(-)