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[91.155.102.19]) by smtp.gmail.com with ESMTPSA id u6sm699992lfr.158.2022.01.17.10.03.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Jan 2022 10:03:50 -0800 (PST) Message-ID: <66835d0f-fe80-aa80-0347-cb7fd00696fc@gmail.com> Date: Mon, 17 Jan 2022 20:03:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Content-Language: en-US To: Andi Shyti , Matt Roper References: <20220112222031.82883-1-andi.shyti@linux.intel.com> <20220112222031.82883-2-andi.shyti@linux.intel.com> From: Abdiel Janulgue In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 18 Jan 2022 13:27:05 +0000 Subject: Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Prepare for multiple GTs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Intel GFX , Lucas De Marchi , DRI Devel , Matthew Auld Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 14.1.2022 19.59, Andi Shyti wrote: > Hi Matt, > > [...] > >>> -int intel_uncore_setup_mmio(struct intel_uncore *uncore) >>> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr) >>> { >>> struct drm_i915_private *i915 = uncore->i915; >>> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); >>> - int mmio_bar; >>> int mmio_size; >>> >>> - mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0; >>> /* >>> * Before gen4, the registers and the GTT are behind different BARs. >>> * However, from gen4 onwards, the registers and the GTT are shared >>> @@ -2044,7 +2041,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore) >>> else >>> mmio_size = 2 * 1024 * 1024; >>> >>> - uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); >>> + uncore->regs = ioremap(phys_addr, mmio_size); >> >> Is there a specific reason we switch to ioremap() instead of >> pci_iomap_range()? I.e., we could pass 'phys_offset' rather than >> 'phys_addr' and call >> >> pci_iomap_range(pdev, mmio_bar, phys_offset, mmio_size); >> >> Not that it really matters too much either way as far as I can see; >> ioremap()/iounmap() should work fine too. > > this was originally changed by Abdiel (I think) and I left as it > is as I tried to change as less as I could from the original > work. Hey, It’s been awhile and this code has changed a lot! I remember needing the unmapped phys_addr of each tile’s mmio_bar as well when I refactored this spot (setup_mmio) so its GGTT portion can be ioremapped according to ggtt_probe_common. Cheers! Abdiel > >> Reviewed-by: Matt Roper > > Thank you! > > Andi