* [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only
@ 2015-02-03 14:25 Damien Lespiau
2015-02-03 14:25 ` [PATCH 2/2] drm/i915/skl: Also detect eDRAM on SKL Damien Lespiau
2015-02-11 15:27 ` [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only Paulo Zanoni
0 siblings, 2 replies; 5+ messages in thread
From: Damien Lespiau @ 2015-02-03 14:25 UTC (permalink / raw)
To: intel-gfx
At the moment we compare the whole EDRAM_PRESENT/EDRAMCAP register value
to 1 while EDRAM_PRESENT is only bit 0 (the rest may be used to describe
eDRAM capabilities).
To be more future proof, only look at bit 0 to detect eDRAM presence.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33b3d0a2..0aeaf7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5980,6 +5980,7 @@ enum punit_power_well {
#define HSW_IDICR 0x9008
#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
#define HSW_EDRAM_PRESENT 0x120010
+#define EDRAM_ENABLED 0x1
#define GEN6_UCGCTL1 0x9400
# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 76b60a3..00c91be 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -328,7 +328,7 @@ static void intel_uncore_ellc_detect(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
- (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
+ (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
/* The docs do not explain exactly how the calculation can be
* made. It is somewhat guessable, but for now, it's always
* 128MB.
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] drm/i915/skl: Also detect eDRAM on SKL
2015-02-03 14:25 [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only Damien Lespiau
@ 2015-02-03 14:25 ` Damien Lespiau
2015-02-04 12:33 ` shuang.he
2015-02-11 15:27 ` [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only Paulo Zanoni
1 sibling, 1 reply; 5+ messages in thread
From: Damien Lespiau @ 2015-02-03 14:25 UTC (permalink / raw)
To: intel-gfx
Suggested-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 00c91be..d67346c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -327,7 +327,8 @@ static void intel_uncore_ellc_detect(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
+ if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
+ INTEL_INFO(dev)->gen >= 9) &&
(__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
/* The docs do not explain exactly how the calculation can be
* made. It is somewhat guessable, but for now, it's always
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 2/2] drm/i915/skl: Also detect eDRAM on SKL
2015-02-03 14:25 ` [PATCH 2/2] drm/i915/skl: Also detect eDRAM on SKL Damien Lespiau
@ 2015-02-04 12:33 ` shuang.he
0 siblings, 0 replies; 5+ messages in thread
From: shuang.he @ 2015-02-04 12:33 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, damien.lespiau
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5707
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV +1 282/283 283/283
ILK -3 316/319 313/319
SNB 322/346 322/346
IVB -2 382/384 380/384
BYT 296/296 296/296
HSW 425/428 425/428
BDW 318/333 318/333
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gen3_render_linear_blits CRASH(1, M23)PASS(1, M25) PASS(1, M25)
ILK igt_drv_suspend_fence-restore-tiled2untiled DMESG_WARN(1, M37)PASS(1, M26) DMESG_WARN(1, M37)
ILK igt_drv_suspend_fence-restore-untiled DMESG_WARN(1, M37)PASS(1, M26) DMESG_WARN(1, M37)
*ILK igt_kms_flip_vblank-vs-hang PASS(2, M26M37) TIMEOUT(1, M37)
IVB igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1, M34)PASS(1, M21) DMESG_WARN(1, M34)
*IVB igt_gem_storedw_batches_loop_secure-dispatch PASS(2, M21M34) DMESG_WARN(1, M34)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only
2015-02-03 14:25 [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only Damien Lespiau
2015-02-03 14:25 ` [PATCH 2/2] drm/i915/skl: Also detect eDRAM on SKL Damien Lespiau
@ 2015-02-11 15:27 ` Paulo Zanoni
2015-02-11 15:47 ` Daniel Vetter
1 sibling, 1 reply; 5+ messages in thread
From: Paulo Zanoni @ 2015-02-11 15:27 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Intel Graphics Development
2015-02-03 12:25 GMT-02:00 Damien Lespiau <damien.lespiau@intel.com>:
> At the moment we compare the whole EDRAM_PRESENT/EDRAMCAP register value
> to 1 while EDRAM_PRESENT is only bit 0 (the rest may be used to describe
> eDRAM capabilities).
>
> To be more future proof, only look at bit 0 to detect eDRAM presence.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
For both patches: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 33b3d0a2..0aeaf7d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5980,6 +5980,7 @@ enum punit_power_well {
> #define HSW_IDICR 0x9008
> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
> #define HSW_EDRAM_PRESENT 0x120010
> +#define EDRAM_ENABLED 0x1
>
> #define GEN6_UCGCTL1 0x9400
> # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 76b60a3..00c91be 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -328,7 +328,7 @@ static void intel_uncore_ellc_detect(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
> - (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
> + (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
> /* The docs do not explain exactly how the calculation can be
> * made. It is somewhat guessable, but for now, it's always
> * 128MB.
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only
2015-02-11 15:27 ` [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only Paulo Zanoni
@ 2015-02-11 15:47 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2015-02-11 15:47 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: Intel Graphics Development
On Wed, Feb 11, 2015 at 01:27:14PM -0200, Paulo Zanoni wrote:
> 2015-02-03 12:25 GMT-02:00 Damien Lespiau <damien.lespiau@intel.com>:
> > At the moment we compare the whole EDRAM_PRESENT/EDRAMCAP register value
> > to 1 while EDRAM_PRESENT is only bit 0 (the rest may be used to describe
> > eDRAM capabilities).
> >
> > To be more future proof, only look at bit 0 to detect eDRAM presence.
> >
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>
> For both patches: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Both merged, thanks for patches&review.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2015-02-03 14:25 [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only Damien Lespiau
2015-02-03 14:25 ` [PATCH 2/2] drm/i915/skl: Also detect eDRAM on SKL Damien Lespiau
2015-02-04 12:33 ` shuang.he
2015-02-11 15:27 ` [PATCH 1/2] drm/i915: Detect eDRAM with the enabled bit only Paulo Zanoni
2015-02-11 15:47 ` Daniel Vetter
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