From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56E71C433DB for ; Mon, 22 Feb 2021 09:21:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DFA6C601FE for ; Mon, 22 Feb 2021 09:21:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DFA6C601FE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 441A36E927; Mon, 22 Feb 2021 09:21:55 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 651C26E927 for ; Mon, 22 Feb 2021 09:21:53 +0000 (UTC) IronPort-SDR: LmXbxNupgAtYzLV6FLNTmrNMjVNgLy/PYzrGkd+i+M5zqSLhIiPac6Xpjc9fSKZ6feZOWpzUy4 Ce2ozhePgCKw== X-IronPort-AV: E=McAfee;i="6000,8403,9902"; a="180938740" X-IronPort-AV: E=Sophos;i="5.81,196,1610438400"; d="scan'208";a="180938740" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2021 01:21:52 -0800 IronPort-SDR: jnT0zjIH47YTE2B8S7+iCJHOZgyusRHtOfACXap+a9jRuPF3gjAI61GZXcqxrtjbCCwPZXzYXN Ci9W8MzSOWAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,196,1610438400"; d="scan'208";a="514730288" Received: from irsmsx605.ger.corp.intel.com ([163.33.146.138]) by orsmga004.jf.intel.com with ESMTP; 22 Feb 2021 01:21:50 -0800 Received: from bgsmsx604.gar.corp.intel.com (10.67.234.6) by IRSMSX605.ger.corp.intel.com (163.33.146.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Mon, 22 Feb 2021 09:21:49 +0000 Received: from bgsmsx604.gar.corp.intel.com ([10.67.234.6]) by BGSMSX604.gar.corp.intel.com ([10.67.234.6]) with mapi id 15.01.2106.002; Mon, 22 Feb 2021 14:51:47 +0530 From: "Shankar, Uma" To: "Nikula, Jani" , "intel-gfx@lists.freedesktop.org" Thread-Topic: [Intel-gfx] [PATCH v3 8/9] drm/i915/edp: modify fixed and downclock modes for MSO Thread-Index: AQHXAIWlYsXSgdqwBEy90bfAUAMW5qpj9uHQ Date: Mon, 22 Feb 2021 09:21:47 +0000 Message-ID: <6f00a4db0fc741c8b7b54491dd8ed645@intel.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.223.10.1] MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH v3 8/9] drm/i915/edp: modify fixed and downclock modes for MSO X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Nikula, Jani" , "Varide, Nischal" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Intel-gfx On Behalf Of Jani Nikula > Sent: Thursday, February 11, 2021 8:22 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani ; Varide, Nischal > Subject: [Intel-gfx] [PATCH v3 8/9] drm/i915/edp: modify fixed and downclock > modes for MSO > > In the case of MSO (Multi-SST Operation), the EDID contains the timings for a single > panel segment. We'll want to hide the fact from userspace, and expose modes that > span the entire display. > > Don't modify the EDID, as the userspace should not use that for modesetting, only > modify the actual modes. > > v3: Use pixel overlap if available. Looks Good to me. Reviewed-by: Uma Shankar > v2: Rename intel_dp_mso_mode_fixup -> intel_edp_mso_mode_fixup > > Cc: Nischal Varide > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_dp.c | 29 +++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 48e65b9a967a..5d5b16f70ed2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -3516,6 +3516,31 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp > *intel_dp) > } > } > > +static void intel_edp_mso_mode_fixup(struct intel_connector *connector, > + struct drm_display_mode *mode) { > + struct intel_dp *intel_dp = intel_attached_dp(connector); > + struct drm_i915_private *i915 = to_i915(connector->base.dev); > + int n = intel_dp->mso_link_count; > + int overlap = intel_dp->mso_pixel_overlap; > + > + if (!mode || !n) > + return; > + > + mode->hdisplay = (mode->hdisplay - overlap) * n; > + mode->hsync_start = (mode->hsync_start - overlap) * n; > + mode->hsync_end = (mode->hsync_end - overlap) * n; > + mode->htotal = (mode->htotal - overlap) * n; > + mode->clock *= n; > + > + drm_mode_set_name(mode); > + > + drm_dbg_kms(&i915->drm, > + "[CONNECTOR:%d:%s] using generated MSO mode: ", > + connector->base.base.id, connector->base.name); > + drm_mode_debug_printmodeline(mode); > +} > + > static void intel_edp_mso_init(struct intel_dp *intel_dp) { > struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -6493,6 > +6518,10 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > if (fixed_mode) > downclock_mode = intel_dp_drrs_init(intel_connector, > fixed_mode); > > + /* multiply the mode clock and horizontal timings for MSO */ > + intel_edp_mso_mode_fixup(intel_connector, fixed_mode); > + intel_edp_mso_mode_fixup(intel_connector, downclock_mode); > + > /* fallback to VBT if available for eDP */ > if (!fixed_mode) > fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx