From: Jani Nikula <jani.nikula@intel.com>
To: Jonathan Cavitt <jonathan.cavitt@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: saurabhg.gupta@intel.com, alex.zuo@intel.com, jonathan.cavitt@intel.com
Subject: Re: [PATCH] drm/i915/gvt: Swap read and write checks
Date: Tue, 17 Mar 2026 11:28:04 +0200 [thread overview]
Message-ID: <705230c4372a7feb62d4a2f8038e07224a5599ab@intel.com> (raw)
In-Reply-To: <20260204161945.8127-2-jonathan.cavitt@intel.com>
On Wed, 04 Feb 2026, Jonathan Cavitt <jonathan.cavitt@intel.com> wrote:
> The function intel_gvt_i2c_handle_aux_ch_write currently does not
> support the DP_AUX_I2C_WRITE operation. Notably, we check if
> op & 0x1 == DP_AUX_I2C_WRITE (one), and if it does not, assert that
> op & 0x1 == DP_AUX_I2C_READ (zero). This is unnecessary because if
> op & 0x1 != 1, then op & 0x1 == 0. But beyond that, it probably makes
> more sense to check for the condition that is implemented, rather than
> check for the condition that is not.
>
> Swap the conditions. We can also get rid of the unnecessary drm_WARN_ON
> while we're here.
>
> Suggested-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Thanks for the patch, pushed to drm-intel-next.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/gvt/edid.c | 18 ++++++++----------
> 1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
> index 021afff1cd5d..ca5b54466a65 100644
> --- a/drivers/gpu/drm/i915/gvt/edid.c
> +++ b/drivers/gpu/drm/i915/gvt/edid.c
> @@ -535,16 +535,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
> i2c_edid->edid_available = true;
> }
> }
> - } else if ((op & 0x1) == DP_AUX_I2C_WRITE) {
> - /* TODO
> - * We only support EDID reading from I2C_over_AUX. And
> - * we do not expect the index mode to be used. Right now
> - * the WRITE operation is ignored. It is good enough to
> - * support the gfx driver to do EDID access.
> - */
> - } else {
> - if (drm_WARN_ON(&i915->drm, (op & 0x1) != DP_AUX_I2C_READ))
> - return;
> + } else if ((op & 0x1) == DP_AUX_I2C_READ) {
> if (drm_WARN_ON(&i915->drm, msg_length != 4))
> return;
> if (i2c_edid->edid_available && i2c_edid->target_selected) {
> @@ -553,6 +544,13 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
> aux_data_for_write = (val << 16);
> } else
> aux_data_for_write = (0xff << 16);
> + } else {
> + /* TODO
> + * We only support EDID reading from I2C_over_AUX. And
> + * we do not expect the index mode to be used. Right now
> + * the WRITE operation is ignored. It is good enough to
> + * support the gfx driver to do EDID access.
> + */
> }
> /* write the return value in AUX_CH_DATA reg which includes:
> * ACK of I2C_WRITE
--
Jani Nikula, Intel
prev parent reply other threads:[~2026-03-17 9:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-04 16:19 [PATCH] drm/i915/gvt: Swap read and write checks Jonathan Cavitt
2026-02-04 16:50 ` Jani Nikula
2026-02-04 17:11 ` ✓ i915.CI.BAT: success for " Patchwork
2026-02-05 5:22 ` ✗ i915.CI.Full: failure " Patchwork
2026-02-20 22:56 ` Cavitt, Jonathan
2026-03-17 9:28 ` Jani Nikula [this message]
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