From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1050C77B7F for ; Wed, 17 May 2023 08:02:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1071810E3C9; Wed, 17 May 2023 08:02:15 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id A3D6A10E3E1; Wed, 17 May 2023 08:02:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684310532; x=1715846532; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=YepLT8IbaEyWWo7Xjnfzi/Zny2qstF+4SOKfpZcqUAY=; b=BIBooG2e606dnPl7HEVMIsvsAxkFtLBOa+vp4cHMUvk+I7p4I2Z7atFk wM3jUDlXhIwhhcTIby1DJ/0YYsFoXHU7rvVGkkteeEQty+Jp2QviZ687L p08zuZVktgf+2lYiul/ZVNTnxTUyURbzBDnoiNutKXreQbCtxwL4WTw2z HKf6x6+SZktDs+W8y3HrSwkmUgv7VsgDQdM614nf/335UX822uVCxNeBs tKpY/Bcs3/IvmkS69CE6itcpdNjI0W2fMj4duulWdUXTZMbORdAAFvhZy om3MU8tkwNyHpofGGW7f/Idup9nITy+6TSce7ek87XARViqomXWLedGlB g==; X-IronPort-AV: E=McAfee;i="6600,9927,10712"; a="417351693" X-IronPort-AV: E=Sophos;i="5.99,281,1677571200"; d="scan'208";a="417351693" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2023 01:02:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10712"; a="679172541" X-IronPort-AV: E=Sophos;i="5.99,281,1677571200"; d="scan'208";a="679172541" Received: from odonov3x-mobl1.ger.corp.intel.com (HELO [10.213.215.219]) ([10.213.215.219]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2023 01:02:10 -0700 Message-ID: <7085b59d-3f56-5b46-a853-f499a8498d99@linux.intel.com> Date: Wed, 17 May 2023 09:01:50 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 To: fei.yang@intel.com, intel-gfx@lists.freedesktop.org References: <20230516181140.1372245-1-fei.yang@intel.com> <20230516181140.1372245-3-fei.yang@intel.com> Content-Language: en-US From: Tvrtko Ursulin Organization: Intel Corporation UK Plc In-Reply-To: <20230516181140.1372245-3-fei.yang@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Allow user to set cache at BO creation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matt Roper , Chris Wilson , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 16/05/2023 19:11, fei.yang@intel.com wrote: > From: Fei Yang > > To comply with the design that buffer objects shall have immutable > cache setting through out their life cycle, {set, get}_caching ioctl's > are no longer supported from MTL onward. With that change caching > policy can only be set at object creation time. The current code > applies a default (platform dependent) cache setting for all objects. > However this is not optimal for performance tuning. The patch extends > the existing gem_create uAPI to let user set PAT index for the object > at creation time. > The new extension is platform independent, so UMD's can switch to using > this extension for older platforms as well, while {set, get}_caching are > still supported on these legacy paltforms for compatibility reason. > > Test igt@gem_create@create_ext_set_pat posted at > https://patchwork.freedesktop.org/series/117695/ > > Tested with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878 > > Signed-off-by: Fei Yang > Cc: Chris Wilson > Cc: Matt Roper > Cc: Andi Shyti > Reviewed-by: Andi Shyti > Tested-by: Jordan Justen > --- > drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++ > drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++ > include/uapi/drm/i915_drm.h | 42 ++++++++++++++++++++++ > tools/include/uapi/drm/i915_drm.h | 42 ++++++++++++++++++++++ > 4 files changed, 126 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c > index bfe1dbda4cb7..644a936248ad 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c > @@ -245,6 +245,7 @@ struct create_ext { > unsigned int n_placements; > unsigned int placement_mask; > unsigned long flags; > + unsigned int pat_index; > }; > > static void repr_placements(char *buf, size_t size, > @@ -394,11 +395,39 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data > return 0; > } > > +static int ext_set_pat(struct i915_user_extension __user *base, void *data) > +{ > + struct create_ext *ext_data = data; > + struct drm_i915_private *i915 = ext_data->i915; > + struct drm_i915_gem_create_ext_set_pat ext; > + unsigned int max_pat_index; > + > + BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) != > + offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd)); > + > + if (copy_from_user(&ext, base, sizeof(ext))) > + return -EFAULT; > + > + max_pat_index = INTEL_INFO(i915)->max_pat_index; > + > + if (ext.pat_index > max_pat_index) { > + drm_dbg(&i915->drm, "PAT index is invalid: %u\n", > + ext.pat_index); > + return -EINVAL; > + } > + > + ext_data->pat_index = ext.pat_index; > + > + return 0; > +} > + > static const i915_user_extension_fn create_extensions[] = { > [I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements, > [I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected, > + [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat, > }; > > +#define PAT_INDEX_NOT_SET 0xffff > /** > * i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle to it. > * @dev: drm device pointer > @@ -418,6 +447,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, > if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) > return -EINVAL; > > + ext_data.pat_index = PAT_INDEX_NOT_SET; > ret = i915_user_extensions(u64_to_user_ptr(args->extensions), > create_extensions, > ARRAY_SIZE(create_extensions), > @@ -454,5 +484,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, > if (IS_ERR(obj)) > return PTR_ERR(obj); > > + if (ext_data.pat_index != PAT_INDEX_NOT_SET) { > + i915_gem_object_set_pat_index(obj, ext_data.pat_index); > + /* Mark pat_index is set by UMD */ > + obj->pat_set_by_user = true; > + } > + > return i915_gem_publish(obj, file, &args->size, &args->handle); > } > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c > index 46a19b099ec8..97ac6fb37958 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c > @@ -208,6 +208,12 @@ bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj) > if (!(obj->flags & I915_BO_ALLOC_USER)) > return false; > > + /* > + * Always flush cache for UMD objects at creation time. > + */ > + if (obj->pat_set_by_user) > + return true; > + > /* > * EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it > * possible for userspace to bypass the GTT caching bits set by the > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index ba40855dbc93..4f3fd650e5e1 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -3664,9 +3664,13 @@ struct drm_i915_gem_create_ext { > * > * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see > * struct drm_i915_gem_create_ext_protected_content. > + * > + * For I915_GEM_CREATE_EXT_SET_PAT usage see > + * struct drm_i915_gem_create_ext_set_pat. > */ > #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 > #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 > +#define I915_GEM_CREATE_EXT_SET_PAT 2 > __u64 extensions; > }; > > @@ -3781,6 +3785,44 @@ struct drm_i915_gem_create_ext_protected_content { > __u32 flags; > }; > > +/** > + * struct drm_i915_gem_create_ext_set_pat - The > + * I915_GEM_CREATE_EXT_SET_PAT extension. > + * > + * If this extension is provided, the specified caching policy (PAT index) is > + * applied to the buffer object. > + * > + * Below is an example on how to create an object with specific caching policy: > + * > + * .. code-block:: C > + * > + * struct drm_i915_gem_create_ext_set_pat set_pat_ext = { > + * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT }, > + * .pat_index = 0, > + * }; > + * struct drm_i915_gem_create_ext create_ext = { > + * .size = PAGE_SIZE, > + * .extensions = (uintptr_t)&set_pat_ext, > + * }; > + * > + * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); > + * if (err) ... > + */ > +struct drm_i915_gem_create_ext_set_pat { > + /** @base: Extension link. See struct i915_user_extension. */ > + struct i915_user_extension base; > + /** > + * @pat_index: PAT index to be set > + * PAT index is a bit field in Page Table Entry to control caching > + * behaviors for GPU accesses. The definition of PAT index is > + * platform dependent and can be found in hardware specifications, > + * e.g. BSpec 45101. AFAIU BSpec numbers do not work from the outside so please put an url to the place where PRMs are hosted instead. > + */ > + __u32 pat_index; > + /** @rsvd: reserved for future use */ > + __u32 rsvd; > +}; > + > /* ID of the protected content session managed by i915 when PXP is active */ > #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf > > diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h > index 8df261c5ab9b..4fbfa472b9fc 100644 > --- a/tools/include/uapi/drm/i915_drm.h > +++ b/tools/include/uapi/drm/i915_drm.h Changes to this file I think you should drop. Looking at the log, it is mostly other folks who synchronise it. Regards, Tvrtko > @@ -3607,9 +3607,13 @@ struct drm_i915_gem_create_ext { > * > * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see > * struct drm_i915_gem_create_ext_protected_content. > + * > + * For I915_GEM_CREATE_EXT_SET_PAT usage see > + * struct drm_i915_gem_create_ext_set_pat. > */ > #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 > #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 > +#define I915_GEM_CREATE_EXT_SET_PAT 2 > __u64 extensions; > }; > > @@ -3724,6 +3728,44 @@ struct drm_i915_gem_create_ext_protected_content { > __u32 flags; > }; > > +/** > + * struct drm_i915_gem_create_ext_set_pat - The > + * I915_GEM_CREATE_EXT_SET_PAT extension. > + * > + * If this extension is provided, the specified caching policy (PAT index) is > + * applied to the buffer object. > + * > + * Below is an example on how to create an object with specific caching policy: > + * > + * .. code-block:: C > + * > + * struct drm_i915_gem_create_ext_set_pat set_pat_ext = { > + * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT }, > + * .pat_index = 0, > + * }; > + * struct drm_i915_gem_create_ext create_ext = { > + * .size = PAGE_SIZE, > + * .extensions = (uintptr_t)&set_pat_ext, > + * }; > + * > + * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); > + * if (err) ... > + */ > +struct drm_i915_gem_create_ext_set_pat { > + /** @base: Extension link. See struct i915_user_extension. */ > + struct i915_user_extension base; > + /** > + * @pat_index: PAT index to be set > + * PAT index is a bit field in Page Table Entry to control caching > + * behaviors for GPU accesses. The definition of PAT index is > + * platform dependent and can be found in hardware specifications, > + * e.g. BSpec 45101. > + */ > + __u32 pat_index; > + /** @rsvd: reserved for future use */ > + __u32 rsvd; > +}; > + > /* ID of the protected content session managed by i915 when PXP is active */ > #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf >