From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3148FC43334 for ; Thu, 7 Jul 2022 21:28:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1EDED11ADC3; Thu, 7 Jul 2022 21:28:25 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0968811A78E; Thu, 7 Jul 2022 21:28:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657229304; x=1688765304; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=7/TlorJDQoNGY2gktJY2UhvNcAgpTuh1cVKPBgUm+/0=; b=Tm50b4H42fMdz2sQmN4SvDtDe+eRjmBzo8Ec9WcriD9bB02AdNzrWGdU cqwzwBitEA9/U0qlRd1XKbuHmu3MvT3bm5qLQosjH+BG6pm4Z33aUcKIU Iln4bi1OX1WKsPouMw3QoNxWLFsJpo6Qd/zUUxxscZKLCjXmttSbBc1l1 ZyrNaC6eOFuL/ZAdXQI0yLS741aiczuOdNgbNk+M4NKcgWmLvhpmo+07q RKjSH6cayz9ECmcJO1LoYMF8EA3L9MwXSoGu9VRzqY4jDs3AmSouagI5j 70XF23yHC5VQzbOn5blopSNQ7Z2NbJyd6cIoVKCMZECFf97AFni16GfUE A==; X-IronPort-AV: E=McAfee;i="6400,9594,10401"; a="285254116" X-IronPort-AV: E=Sophos;i="5.92,253,1650956400"; d="scan'208";a="285254116" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2022 14:28:23 -0700 X-IronPort-AV: E=Sophos;i="5.92,253,1650956400"; d="scan'208";a="651297397" Received: from ahajda-mobl.ger.corp.intel.com (HELO [10.213.16.170]) ([10.213.16.170]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2022 14:28:20 -0700 Message-ID: <70a63b2e-23f5-9bf8-f782-5941f5cd01fc@intel.com> Date: Thu, 7 Jul 2022 23:28:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Firefox/91.0 Thunderbird/91.11.0 Content-Language: en-US To: Mauro Carvalho Chehab References: <3ecc1f94290a66b2e682f956b5232b4903c32a2c.1656921701.git.mchehab@kernel.org> From: Andrzej Hajda Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298 Gdansk - KRS 101882 - NIP 957-07-52-316 In-Reply-To: <3ecc1f94290a66b2e682f956b5232b4903c32a2c.1656921701.git.mchehab@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/gt: Serialize TLB invalidates with GT resets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Thomas_Hellstr=c3=b6m?= , Andi Shyti , David Airlie , intel-gfx@lists.freedesktop.org, Lucas De Marchi , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Chris Wilson , Rodrigo Vivi , Dave Airlie , stable@vger.kernel.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 04.07.2022 10:09, Mauro Carvalho Chehab wrote: > From: Chris Wilson > > Avoid trying to invalidate the TLB in the middle of performing an > engine reset, as this may result in the reset timing out. Currently, > the TLB invalidate is only serialised by its own mutex, forgoing the > uncore lock, but we can take the uncore->lock as well to serialise > the mmio access, thereby serialising with the GDRST. > > Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with > i915 selftest/hangcheck. > > Cc: stable@vger.kernel.org # Up to 4.4 > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > Reported-by: Mauro Carvalho Chehab > Tested-by: Mauro Carvalho Chehab > Reviewed-by: Mauro Carvalho Chehab > Cc: Chris Wilson > Cc: Tvrtko Ursulin > Cc: Thomas Hellström > Cc: Andi Shyti > Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Andrzej Hajda Regards Andrzej > --- > > To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. > See [PATCH v3 0/2] at: https://lore.kernel.org/all/cover.1656921701.git.mchehab@kernel.org/ > > drivers/gpu/drm/i915/gt/intel_gt.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 8da3314bb6bf..68c2b0d8f187 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -952,6 +952,20 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) > mutex_lock(>->tlb_invalidate_lock); > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); > > + spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */ > + > + for_each_engine(engine, gt, id) { > + struct reg_and_bit rb; > + > + rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); > + if (!i915_mmio_reg_offset(rb.reg)) > + continue; > + > + intel_uncore_write_fw(uncore, rb.reg, rb.bit); > + } > + > + spin_unlock_irq(&uncore->lock); > + > for_each_engine(engine, gt, id) { > /* > * HW architecture suggest typical invalidation time at 40us, > @@ -966,7 +980,6 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) > if (!i915_mmio_reg_offset(rb.reg)) > continue; > > - intel_uncore_write_fw(uncore, rb.reg, rb.bit); > if (__intel_wait_for_register_fw(uncore, > rb.reg, rb.bit, 0, > timeout_us, timeout_ms,