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header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 819566E098; Mon, 2 Aug 2021 20:52:53 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F1296E098 for ; Mon, 2 Aug 2021 20:52:52 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10064"; a="274592855" X-IronPort-AV: E=Sophos;i="5.84,289,1620716400"; d="scan'208";a="274592855" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2021 13:52:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,289,1620716400"; d="scan'208";a="520694513" Received: from irsmsx606.ger.corp.intel.com ([163.33.146.139]) by fmsmga002.fm.intel.com with ESMTP; 02 Aug 2021 13:52:44 -0700 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by IRSMSX606.ger.corp.intel.com (163.33.146.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.10; Mon, 2 Aug 2021 21:52:42 +0100 Received: from orsmsx610.amr.corp.intel.com ([10.22.229.23]) by ORSMSX610.amr.corp.intel.com ([10.22.229.23]) with mapi id 15.01.2242.010; Mon, 2 Aug 2021 13:52:41 -0700 From: "Souza, Jose" To: "intel-gfx@lists.freedesktop.org" , "Deak, Imre" Thread-Topic: [PATCH] drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled Thread-Index: AQHXh9D7h4JyVYL2xkeudDnllxQeyKthJ62A Date: Mon, 2 Aug 2021 20:52:41 +0000 Message-ID: <70c089841d159b322f6c6749fad8e416766676dc.camel@intel.com> References: <20210802190148.2099625-1-imre.deak@intel.com> In-Reply-To: <20210802190148.2099625-1-imre.deak@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.22.254.132] Content-Type: text/plain; charset="utf-8" Content-ID: <6651876ECA665D4A8BE48EDD71521168@intel.com> Content-Transfer-Encoding: base64 MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" T24gTW9uLCAyMDIxLTA4LTAyIGF0IDIyOjAxICswMzAwLCBJbXJlIERlYWsgd3JvdGU6DQo+IENJ IHRlc3QgcmVzdWx0cy9mdXJ0aGVyIGV4cGVyaW1lbnRzIHNob3cgdGhhdCB0aGUgd29ya2Fyb3Vu ZCBhZGRlZCBpbg0KPiANCj4gY29tbWl0IDU3M2Q3Y2U0ZjY5YSAoImRybS9pOTE1L2FkbHA6IEFk ZCB3b3JrYXJvdW5kIHRvIGRpc2FibGUgQ01URyBjbG9jayBnYXRpbmciKQ0KPiANCj4gY2FuIGJl IGFwcGxpZWQgb25seSB3aGlsZSBEUExMMCBpcyBlbmFibGVkLiBJZiBpdCdzIGRpc2FibGVkIHRo ZQ0KPiBUUkFOU19DTVRHX0NISUNLRU4gcmVnaXN0ZXIgaXMgbm90IGFjY2Vzc2libGUuIEFjY29y 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