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d="scan'208";a="465296187" Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86]) by orsmga004.jf.intel.com with ESMTP; 18 Oct 2020 13:47:31 -0700 Received: from bgsmsx604.gar.corp.intel.com (10.67.234.6) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Sun, 18 Oct 2020 13:47:29 -0700 Received: from bgsmsx604.gar.corp.intel.com (10.67.234.6) by BGSMSX604.gar.corp.intel.com (10.67.234.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 19 Oct 2020 02:17:27 +0530 Received: from bgsmsx604.gar.corp.intel.com ([10.67.234.6]) by BGSMSX604.gar.corp.intel.com ([10.67.234.6]) with mapi id 15.01.1713.004; Mon, 19 Oct 2020 02:17:27 +0530 From: "Shankar, Uma" To: "Nautiyal, Ankit K" , "intel-gfx@lists.freedesktop.org" Thread-Topic: [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 Thread-Index: AQHWouJZAJK76sJHwUKa0Yk1CIyeV6md1IPw Date: Sun, 18 Oct 2020 20:47:27 +0000 Message-ID: <7137c1244ee3409da343a6c4a1de38ee@intel.com> References: <20201015105259.27934-1-ankit.k.nautiyal@intel.com> <20201015105259.27934-2-ankit.k.nautiyal@intel.com> In-Reply-To: <20201015105259.27934-2-ankit.k.nautiyal@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.223.10.1] MIME-Version: 1.0 Subject: Re: [Intel-gfx] [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "dri-devel@lists.freedesktop.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Nautiyal, Ankit K > Sent: Thursday, October 15, 2020 4:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma ; > Kulkarni, Vandita ; ville.syrjala@linux.intel.com; > Sharma, Swati2 > Subject: [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 > > From: Swati Sharma > > The HDMI2.1 extends HFVSBD (HDMI Forum Vendor Specific Data block) to have Typo in HFVSDB > fields related to newly defined methods of FRL (Fixed Rate Link) levels, number > of lanes supported, DSC Color bit depth, VRR min/max, FVA (Fast Vactive), ALLM > etc. > > This patch adds the new HFVSDB fields that are required for HDMI2.1. > > Signed-off-by: Sharma, Swati2 > Signed-off-by: Ankit Nautiyal > --- > include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index > b27a0e2169c8..1cc5c2c73282 100644 > --- a/include/drm/drm_edid.h > +++ b/include/drm/drm_edid.h > @@ -229,6 +229,36 @@ struct detailed_timing { > DRM_EDID_YCBCR420_DC_36 | \ > DRM_EDID_YCBCR420_DC_30) > > +/* HDMI 2.1 additional fields */ > +#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 > +#define DRM_EDID_FAPA_START_LOCATION (1 << 0) > +#define DRM_EDID_ALLM (1 << 1) > +#define DRM_EDID_FVA (1 << 2) > + > +/* Deep Color specific */ > +#define DRM_EDID_DC_30BIT_420 (1 << 0) > +#define DRM_EDID_DC_36BIT_420 (1 << 1) > +#define DRM_EDID_DC_48BIT_420 (1 << 2) > + > +/* VRR specific */ > +#define DRM_EDID_CNMVRR (1 << 3) > +#define DRM_EDID_CINEMA_VRR (1 << 4) > +#define DRM_EDID_MDELTA (1 << 5) > +#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 > +#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff > +#define DRM_EDID_VRR_MIN_MASK 0x3f > + > +/* DSC specific */ > +#define DRM_EDID_DSC_10BPC (1 << 0) > +#define DRM_EDID_DSC_12BPC (1 << 1) > +#define DRM_EDID_DSC_16BPC (1 << 2) > +#define DRM_EDID_DSC_ALL_BPP (1 << 3) > +#define DRM_EDID_DSC_NATIVE_420 (1 << 6) > +#define DRM_EDID_DSC_1P2 (1 << 7) > +#define DRM_EDID_DSC_MAX_FRL_RATE 0xf This should be set as mask and made it as 0xf0 > +#define DRM_EDID_DSC_MAX_SLICES 0xf > +#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f > + > /* ELD Header Block */ > #define DRM_ELD_HEADER_BLOCK_SIZE 4 > > -- > 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx