From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, shobhit.kumar@intel.com
Subject: Re: [PATCH] drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL
Date: 05 Feb 2015 11:41:16 -0800 [thread overview]
Message-ID: <71e320$fivk8h@orsmga003.jf.intel.com> (raw)
In-Reply-To: <1423136325-16532-1-git-send-email-shobhit.kumar@intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5718
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -8 282/283 274/283
ILK +1 316/319 317/319
SNB 322/346 322/346
IVB -1 382/384 381/384
BYT 296/296 296/296
HSW 425/428 425/428
BDW 318/333 318/333
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gem_fence_thrash_bo-write-verify-y PASS(2, M23M7) FAIL(1, M7)
PNV igt_gem_userptr_blits_coherency-sync CRASH(2, M7)PASS(1, M23) CRASH(1, M7)
PNV igt_gem_userptr_blits_coherency-unsync CRASH(2, M7)PASS(1, M23) CRASH(1, M7)
*PNV igt_gem_userptr_blits_forked-sync-interruptible PASS(2, M23M7) DMESG_WARN(1, M7)
*PNV igt_gem_userptr_blits_forked-sync-multifd-interruptible PASS(2, M23M7) NO_RESULT(1, M7)
PNV igt_gen3_render_linear_blits FAIL(3, M7)CRASH(1, M23)PASS(4, M25M23) FAIL(1, M7)
PNV igt_gen3_render_mixed_blits FAIL(3, M7)PASS(1, M23) FAIL(1, M7)
PNV igt_gen3_render_tiledx_blits FAIL(2, M7)PASS(1, M23) FAIL(1, M7)
PNV igt_gem_tiled_pread_pwrite FAIL(2, M7)PASS(1, M23) FAIL(1, M7)
*ILK igt_drv_suspend_forcewake DMESG_WARN(5, M26M37) PASS(1, M26)
IVB igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(2, M34)PASS(5, M21M34) DMESG_WARN(1, M21)
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-02-05 19:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-05 11:38 [PATCH] drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL Shobhit Kumar
2015-02-05 19:41 ` shuang.he [this message]
2015-02-09 11:13 ` Shobhit Kumar
2015-02-09 14:13 ` Jani Nikula
2015-02-09 18:23 ` Jani Nikula
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